1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2021, Martin Botka <martin.botka@somainline.org> 4 */ 5 6#include <dt-bindings/clock/qcom,gcc-sm6125.h> 7#include <dt-bindings/clock/qcom,rpmcc.h> 8#include <dt-bindings/dma/qcom-gpi.h> 9#include <dt-bindings/gpio/gpio.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/power/qcom-rpmpd.h> 12 13/ { 14 interrupt-parent = <&intc>; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 18 chosen { }; 19 20 clocks { 21 xo_board: xo-board { 22 compatible = "fixed-clock"; 23 #clock-cells = <0>; 24 clock-frequency = <19200000>; 25 clock-output-names = "xo_board"; 26 }; 27 28 sleep_clk: sleep-clk { 29 compatible = "fixed-clock"; 30 #clock-cells = <0>; 31 clock-frequency = <32000>; 32 clock-output-names = "sleep_clk"; 33 }; 34 }; 35 36 cpus { 37 #address-cells = <2>; 38 #size-cells = <0>; 39 40 CPU0: cpu@0 { 41 device_type = "cpu"; 42 compatible = "qcom,kryo260"; 43 reg = <0x0 0x0>; 44 enable-method = "psci"; 45 capacity-dmips-mhz = <1024>; 46 next-level-cache = <&L2_0>; 47 L2_0: l2-cache { 48 compatible = "cache"; 49 cache-level = <2>; 50 }; 51 }; 52 53 CPU1: cpu@1 { 54 device_type = "cpu"; 55 compatible = "qcom,kryo260"; 56 reg = <0x0 0x1>; 57 enable-method = "psci"; 58 capacity-dmips-mhz = <1024>; 59 next-level-cache = <&L2_0>; 60 }; 61 62 CPU2: cpu@2 { 63 device_type = "cpu"; 64 compatible = "qcom,kryo260"; 65 reg = <0x0 0x2>; 66 enable-method = "psci"; 67 capacity-dmips-mhz = <1024>; 68 next-level-cache = <&L2_0>; 69 }; 70 71 CPU3: cpu@3 { 72 device_type = "cpu"; 73 compatible = "qcom,kryo260"; 74 reg = <0x0 0x3>; 75 enable-method = "psci"; 76 capacity-dmips-mhz = <1024>; 77 next-level-cache = <&L2_0>; 78 }; 79 80 CPU4: cpu@100 { 81 device_type = "cpu"; 82 compatible = "qcom,kryo260"; 83 reg = <0x0 0x100>; 84 enable-method = "psci"; 85 capacity-dmips-mhz = <1638>; 86 next-level-cache = <&L2_1>; 87 L2_1: l2-cache { 88 compatible = "cache"; 89 cache-level = <2>; 90 }; 91 }; 92 93 CPU5: cpu@101 { 94 device_type = "cpu"; 95 compatible = "qcom,kryo260"; 96 reg = <0x0 0x101>; 97 enable-method = "psci"; 98 capacity-dmips-mhz = <1638>; 99 next-level-cache = <&L2_1>; 100 }; 101 102 CPU6: cpu@102 { 103 device_type = "cpu"; 104 compatible = "qcom,kryo260"; 105 reg = <0x0 0x102>; 106 enable-method = "psci"; 107 capacity-dmips-mhz = <1638>; 108 next-level-cache = <&L2_1>; 109 }; 110 111 CPU7: cpu@103 { 112 device_type = "cpu"; 113 compatible = "qcom,kryo260"; 114 reg = <0x0 0x103>; 115 enable-method = "psci"; 116 capacity-dmips-mhz = <1638>; 117 next-level-cache = <&L2_1>; 118 }; 119 120 cpu-map { 121 cluster0 { 122 core0 { 123 cpu = <&CPU0>; 124 }; 125 126 core1 { 127 cpu = <&CPU1>; 128 }; 129 130 core2 { 131 cpu = <&CPU2>; 132 }; 133 134 core3 { 135 cpu = <&CPU3>; 136 }; 137 }; 138 139 cluster1 { 140 core0 { 141 cpu = <&CPU4>; 142 }; 143 144 core1 { 145 cpu = <&CPU5>; 146 }; 147 148 core2 { 149 cpu = <&CPU6>; 150 }; 151 152 core3 { 153 cpu = <&CPU7>; 154 }; 155 }; 156 }; 157 }; 158 159 firmware { 160 scm: scm { 161 compatible = "qcom,scm-sm6125", "qcom,scm"; 162 #reset-cells = <1>; 163 }; 164 }; 165 166 memory@40000000 { 167 /* We expect the bootloader to fill in the size */ 168 reg = <0x0 0x40000000 0x0 0x0>; 169 device_type = "memory"; 170 }; 171 172 pmu { 173 compatible = "arm,armv8-pmuv3"; 174 interrupts = <GIC_PPI 6 IRQ_TYPE_LEVEL_HIGH>; 175 }; 176 177 psci { 178 compatible = "arm,psci-1.0"; 179 method = "smc"; 180 }; 181 182 reserved_memory: reserved-memory { 183 #address-cells = <2>; 184 #size-cells = <2>; 185 ranges; 186 187 hyp_mem: memory@45700000 { 188 reg = <0x0 0x45700000 0x0 0x600000>; 189 no-map; 190 }; 191 192 xbl_aop_mem: memory@45e00000 { 193 reg = <0x0 0x45e00000 0x0 0x140000>; 194 no-map; 195 }; 196 197 sec_apps_mem: memory@45fff000 { 198 reg = <0x0 0x45fff000 0x0 0x1000>; 199 no-map; 200 }; 201 202 smem_mem: memory@46000000 { 203 reg = <0x0 0x46000000 0x0 0x200000>; 204 no-map; 205 }; 206 207 reserved_mem1: memory@46200000 { 208 reg = <0x0 0x46200000 0x0 0x2d00000>; 209 no-map; 210 }; 211 212 camera_mem: memory@4ab00000 { 213 reg = <0x0 0x4ab00000 0x0 0x500000>; 214 no-map; 215 }; 216 217 modem_mem: memory@4b000000 { 218 reg = <0x0 0x4b000000 0x0 0x7e00000>; 219 no-map; 220 }; 221 222 venus_mem: memory@52e00000 { 223 reg = <0x0 0x52e00000 0x0 0x500000>; 224 no-map; 225 }; 226 227 wlan_msa_mem: memory@53300000 { 228 reg = <0x0 0x53300000 0x0 0x200000>; 229 no-map; 230 }; 231 232 cdsp_mem: memory@53500000 { 233 reg = <0x0 0x53500000 0x0 0x1e00000>; 234 no-map; 235 }; 236 237 adsp_pil_mem: memory@55300000 { 238 reg = <0x0 0x55300000 0x0 0x1e00000>; 239 no-map; 240 }; 241 242 ipa_fw_mem: memory@57100000 { 243 reg = <0x0 0x57100000 0x0 0x10000>; 244 no-map; 245 }; 246 247 ipa_gsi_mem: memory@57110000 { 248 reg = <0x0 0x57110000 0x0 0x5000>; 249 no-map; 250 }; 251 252 gpu_mem: memory@57115000 { 253 reg = <0x0 0x57115000 0x0 0x2000>; 254 no-map; 255 }; 256 257 cont_splash_mem: memory@5c000000 { 258 reg = <0x0 0x5c000000 0x0 0x00f00000>; 259 no-map; 260 }; 261 262 dfps_data_mem: memory@5cf00000 { 263 reg = <0x0 0x5cf00000 0x0 0x0100000>; 264 no-map; 265 }; 266 267 cdsp_sec_mem: memory@5f800000 { 268 reg = <0x0 0x5f800000 0x0 0x1e00000>; 269 no-map; 270 }; 271 272 qseecom_mem: memory@5e400000 { 273 reg = <0x0 0x5e400000 0x0 0x1400000>; 274 no-map; 275 }; 276 277 sdsp_mem: memory@f3000000 { 278 reg = <0x0 0xf3000000 0x0 0x400000>; 279 no-map; 280 }; 281 282 adsp_mem: memory@f3400000 { 283 reg = <0x0 0xf3400000 0x0 0x800000>; 284 no-map; 285 }; 286 287 qseecom_ta_mem: memory@13fc00000 { 288 reg = <0x1 0x3fc00000 0x0 0x400000>; 289 no-map; 290 }; 291 }; 292 293 rpm-glink { 294 compatible = "qcom,glink-rpm"; 295 296 interrupts = <GIC_SPI 194 IRQ_TYPE_EDGE_RISING>; 297 qcom,rpm-msg-ram = <&rpm_msg_ram>; 298 mboxes = <&apcs_glb 0>; 299 300 rpm_requests: rpm-requests { 301 compatible = "qcom,rpm-sm6125"; 302 qcom,glink-channels = "rpm_requests"; 303 304 rpmcc: clock-controller { 305 compatible = "qcom,rpmcc-sm6125", "qcom,rpmcc"; 306 #clock-cells = <1>; 307 }; 308 309 rpmpd: power-controller { 310 compatible = "qcom,sm6125-rpmpd"; 311 #power-domain-cells = <1>; 312 operating-points-v2 = <&rpmpd_opp_table>; 313 314 rpmpd_opp_table: opp-table { 315 compatible = "operating-points-v2"; 316 317 rpmpd_opp_ret: opp1 { 318 opp-level = <RPM_SMD_LEVEL_RETENTION>; 319 }; 320 321 rpmpd_opp_ret_plus: opp2 { 322 opp-level = <RPM_SMD_LEVEL_RETENTION_PLUS>; 323 }; 324 325 rpmpd_opp_min_svs: opp3 { 326 opp-level = <RPM_SMD_LEVEL_MIN_SVS>; 327 }; 328 329 rpmpd_opp_low_svs: opp4 { 330 opp-level = <RPM_SMD_LEVEL_LOW_SVS>; 331 }; 332 333 rpmpd_opp_svs: opp5 { 334 opp-level = <RPM_SMD_LEVEL_SVS>; 335 }; 336 337 rpmpd_opp_svs_plus: opp6 { 338 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>; 339 }; 340 341 rpmpd_opp_nom: opp7 { 342 opp-level = <RPM_SMD_LEVEL_NOM>; 343 }; 344 345 rpmpd_opp_nom_plus: opp8 { 346 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>; 347 }; 348 349 rpmpd_opp_turbo: opp9 { 350 opp-level = <RPM_SMD_LEVEL_TURBO>; 351 }; 352 353 rpmpd_opp_turbo_no_cpr: opp10 { 354 opp-level = <RPM_SMD_LEVEL_TURBO_NO_CPR>; 355 }; 356 }; 357 }; 358 }; 359 }; 360 361 smem: smem { 362 compatible = "qcom,smem"; 363 memory-region = <&smem_mem>; 364 hwlocks = <&tcsr_mutex 3>; 365 }; 366 367 soc { 368 #address-cells = <1>; 369 #size-cells = <1>; 370 ranges = <0x00 0x00 0x00 0xffffffff>; 371 compatible = "simple-bus"; 372 373 tcsr_mutex: hwlock@340000 { 374 compatible = "qcom,tcsr-mutex"; 375 reg = <0x00340000 0x20000>; 376 #hwlock-cells = <1>; 377 }; 378 379 tlmm: pinctrl@500000 { 380 compatible = "qcom,sm6125-tlmm"; 381 reg = <0x00500000 0x400000>, 382 <0x00900000 0x400000>, 383 <0x00d00000 0x400000>; 384 reg-names = "west", "south", "east"; 385 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; 386 gpio-controller; 387 gpio-ranges = <&tlmm 0 0 134>; 388 #gpio-cells = <2>; 389 interrupt-controller; 390 #interrupt-cells = <2>; 391 392 sdc2_off_state: sdc2-off-state { 393 clk-pins { 394 pins = "sdc2_clk"; 395 drive-strength = <2>; 396 bias-disable; 397 }; 398 399 cmd-pins { 400 pins = "sdc2_cmd"; 401 drive-strength = <2>; 402 bias-pull-up; 403 }; 404 405 data-pins { 406 pins = "sdc2_data"; 407 drive-strength = <2>; 408 bias-pull-up; 409 }; 410 }; 411 412 sdc2_on_state: sdc2-on-state { 413 clk-pins { 414 pins = "sdc2_clk"; 415 drive-strength = <16>; 416 bias-disable; 417 }; 418 419 cmd-pins { 420 pins = "sdc2_cmd"; 421 drive-strength = <10>; 422 bias-pull-up; 423 }; 424 425 data-pins { 426 pins = "sdc2_data"; 427 drive-strength = <10>; 428 bias-pull-up; 429 }; 430 }; 431 }; 432 433 gcc: clock-controller@1400000 { 434 compatible = "qcom,gcc-sm6125"; 435 reg = <0x01400000 0x1f0000>; 436 #clock-cells = <1>; 437 #reset-cells = <1>; 438 #power-domain-cells = <1>; 439 clock-names = "bi_tcxo", "sleep_clk"; 440 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&sleep_clk>; 441 }; 442 443 hsusb_phy1: phy@1613000 { 444 compatible = "qcom,msm8996-qusb2-phy"; 445 reg = <0x01613000 0x180>; 446 #phy-cells = <0>; 447 448 clocks = <&gcc GCC_AHB2PHY_USB_CLK>, 449 <&rpmcc RPM_SMD_XO_CLK_SRC>; 450 clock-names = "cfg_ahb", "ref"; 451 452 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 453 status = "disabled"; 454 }; 455 456 rpm_msg_ram: sram@45f0000 { 457 compatible = "qcom,rpm-msg-ram"; 458 reg = <0x045f0000 0x7000>; 459 }; 460 461 sdhc_1: mmc@4744000 { 462 compatible = "qcom,sm6125-sdhci", "qcom,sdhci-msm-v5"; 463 reg = <0x04744000 0x1000>, <0x04745000 0x1000>; 464 reg-names = "hc", "cqhci"; 465 466 interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>, 467 <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; 468 interrupt-names = "hc_irq", "pwr_irq"; 469 470 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 471 <&gcc GCC_SDCC1_APPS_CLK>, 472 <&xo_board>; 473 clock-names = "iface", "core", "xo"; 474 iommus = <&apps_smmu 0x160 0x0>; 475 476 power-domains = <&rpmpd SM6125_VDDCX>; 477 478 qcom,dll-config = <0x000f642c>; 479 qcom,ddr-config = <0x80040873>; 480 481 bus-width = <8>; 482 non-removable; 483 supports-cqe; 484 485 status = "disabled"; 486 }; 487 488 sdhc_2: mmc@4784000 { 489 compatible = "qcom,sm6125-sdhci", "qcom,sdhci-msm-v5"; 490 reg = <0x04784000 0x1000>; 491 reg-names = "hc"; 492 493 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>, 494 <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 495 interrupt-names = "hc_irq", "pwr_irq"; 496 497 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 498 <&gcc GCC_SDCC2_APPS_CLK>, 499 <&xo_board>; 500 clock-names = "iface", "core", "xo"; 501 iommus = <&apps_smmu 0x180 0x0>; 502 503 pinctrl-0 = <&sdc2_on_state>; 504 pinctrl-1 = <&sdc2_off_state>; 505 pinctrl-names = "default", "sleep"; 506 507 power-domains = <&rpmpd SM6125_VDDCX>; 508 509 qcom,dll-config = <0x0007642c>; 510 qcom,ddr-config = <0x80040873>; 511 512 bus-width = <4>; 513 status = "disabled"; 514 }; 515 516 gpi_dma0: dma-controller@4a00000 { 517 compatible = "qcom,sm6125-gpi-dma", "qcom,sdm845-gpi-dma"; 518 reg = <0x04a00000 0x60000>; 519 interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 520 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 521 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 522 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 523 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 524 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 525 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 526 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>; 527 dma-channels = <8>; 528 dma-channel-mask = <0x1f>; 529 iommus = <&apps_smmu 0x136 0x0>; 530 #dma-cells = <3>; 531 status = "disabled"; 532 }; 533 534 gpi_dma1: dma-controller@4c00000 { 535 compatible = "qcom,sm6125-gpi-dma", "qcom,sdm845-gpi-dma"; 536 reg = <0x04c00000 0x60000>; 537 interrupts = <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 538 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 539 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 540 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 541 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 542 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 543 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 544 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>; 545 dma-channels = <8>; 546 dma-channel-mask = <0x0f>; 547 iommus = <&apps_smmu 0x156 0x0>; 548 #dma-cells = <3>; 549 status = "disabled"; 550 }; 551 552 usb3: usb@4ef8800 { 553 compatible = "qcom,sm6125-dwc3", "qcom,dwc3"; 554 reg = <0x04ef8800 0x400>; 555 #address-cells = <1>; 556 #size-cells = <1>; 557 ranges; 558 559 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 560 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 561 <&gcc GCC_SYS_NOC_USB3_PRIM_AXI_CLK>, 562 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 563 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 564 <&gcc GCC_USB3_PRIM_CLKREF_CLK>; 565 clock-names = "cfg_noc", 566 "core", 567 "iface", 568 "sleep", 569 "mock_utmi", 570 "xo"; 571 572 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 573 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 574 assigned-clock-rates = <19200000>, <66666667>; 575 576 power-domains = <&gcc USB30_PRIM_GDSC>; 577 qcom,select-utmi-as-pipe-clk; 578 status = "disabled"; 579 580 usb3_dwc3: usb@4e00000 { 581 compatible = "snps,dwc3"; 582 reg = <0x04e00000 0xcd00>; 583 interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; 584 iommus = <&apps_smmu 0x100 0x0>; 585 phys = <&hsusb_phy1>; 586 phy-names = "usb2-phy"; 587 snps,dis_u2_susphy_quirk; 588 snps,dis_enblslpm_quirk; 589 maximum-speed = "high-speed"; 590 dr_mode = "peripheral"; 591 }; 592 }; 593 594 sram@4690000 { 595 compatible = "qcom,rpm-stats"; 596 reg = <0x04690000 0x10000>; 597 }; 598 599 spmi_bus: spmi@1c40000 { 600 compatible = "qcom,spmi-pmic-arb"; 601 reg = <0x01c40000 0x1100>, 602 <0x01e00000 0x2000000>, 603 <0x03e00000 0x100000>, 604 <0x03f00000 0xa0000>, 605 <0x01c0a000 0x26000>; 606 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 607 interrupt-names = "periph_irq"; 608 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; 609 qcom,ee = <0>; 610 qcom,channel = <0>; 611 #address-cells = <2>; 612 #size-cells = <0>; 613 interrupt-controller; 614 #interrupt-cells = <4>; 615 cell-index = <0>; 616 }; 617 618 apps_smmu: iommu@c600000 { 619 compatible = "qcom,sm6125-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 620 reg = <0xc600000 0x80000>; 621 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, 622 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 623 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 624 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 625 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 626 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 627 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 628 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 629 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 630 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 631 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 632 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 633 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 634 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 635 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 636 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 637 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 638 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 639 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 640 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 641 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 642 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 643 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 644 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 645 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 646 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 647 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 648 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 649 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 650 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 651 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 652 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 653 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 654 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 655 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 656 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 657 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 658 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 659 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 660 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 661 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, 662 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 663 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 664 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 665 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 666 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 667 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 668 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 669 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 670 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 671 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 672 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 673 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 674 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 675 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 676 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 677 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 678 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 679 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 680 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 681 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 682 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 683 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 684 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 685 <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; 686 687 #global-interrupts = <1>; 688 #iommu-cells = <2>; 689 }; 690 691 apcs_glb: mailbox@f111000 { 692 compatible = "qcom,sm6125-apcs-hmss-global"; 693 reg = <0x0f111000 0x1000>; 694 695 #mbox-cells = <1>; 696 }; 697 698 timer@f120000 { 699 compatible = "arm,armv7-timer-mem"; 700 #address-cells = <1>; 701 #size-cells = <1>; 702 ranges; 703 reg = <0x0f120000 0x1000>; 704 clock-frequency = <19200000>; 705 706 frame@f121000 { 707 frame-number = <0>; 708 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 709 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 710 reg = <0x0f121000 0x1000>, 711 <0x0f122000 0x1000>; 712 }; 713 714 frame@f123000 { 715 frame-number = <1>; 716 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 717 reg = <0x0f123000 0x1000>; 718 status = "disabled"; 719 }; 720 721 frame@f124000 { 722 frame-number = <2>; 723 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 724 reg = <0x0f124000 0x1000>; 725 status = "disabled"; 726 }; 727 728 frame@f125000 { 729 frame-number = <3>; 730 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 731 reg = <0x0f125000 0x1000>; 732 status = "disabled"; 733 }; 734 735 frame@f126000 { 736 frame-number = <4>; 737 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 738 reg = <0x0f126000 0x1000>; 739 status = "disabled"; 740 }; 741 742 frame@f127000 { 743 frame-number = <5>; 744 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 745 reg = <0x0f127000 0x1000>; 746 status = "disabled"; 747 }; 748 749 frame@f128000 { 750 frame-number = <6>; 751 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 752 reg = <0x0f128000 0x1000>; 753 status = "disabled"; 754 }; 755 }; 756 757 intc: interrupt-controller@f200000 { 758 compatible = "arm,gic-v3"; 759 reg = <0x0f200000 0x20000>, 760 <0x0f300000 0x100000>; 761 #interrupt-cells = <3>; 762 interrupt-controller; 763 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 764 }; 765 }; 766 767 timer { 768 compatible = "arm,armv8-timer"; 769 interrupts = <GIC_PPI 1 0xf08 770 GIC_PPI 2 0xf08 771 GIC_PPI 3 0xf08 772 GIC_PPI 0 0xf08>; 773 clock-frequency = <19200000>; 774 }; 775}; 776