arm64: tegra: Add power-domain for Tegra210 HDA

HDA initialization is failing occasionally on Tegra210 and following
print is observed in the boot log. Because of this probe() fails and
no sound car

arm64: tegra: Add power-domain for Tegra210 HDA

HDA initialization is failing occasionally on Tegra210 and following
print is observed in the boot log. Because of this probe() fails and
no sound card is registered.

[16.800802] tegra-hda 70030000.hda: no codecs found!

Codecs request a state change and enumeration by the controller. In
failure cases this does not seem to happen as STATETS register reads 0.

The problem seems to be related to the HDA codec dependency on SOR
power domain. If it is gated during HDA probe then the failure is
observed. Building Tegra HDA driver into kernel image avoids this
failure but does not completely address the dependency part. Fix this
problem by adding 'power-domains' DT property for Tegra210 HDA. Note
that Tegra186 and Tegra194 HDA do this already.

Fixes: 742af7e7a0a1 ("arm64: tegra: Add Tegra210 support")
Depends-on: 96d1f078ff0 ("arm64: tegra: Add SOR power-domain for Tegra210")
Cc: <stable@vger.kernel.org>
Signed-off-by: Sameer Pujar <spujar@nvidia.com>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Change order of SATA resets for Tegra132 and Tegra210

Tegra AHCI dt-binding doc is converted from text based to yaml based.

dtbs_check valdiation strictly follows reset-names order sp

arm64: tegra: Change order of SATA resets for Tegra132 and Tegra210

Tegra AHCI dt-binding doc is converted from text based to yaml based.

dtbs_check valdiation strictly follows reset-names order specified
in yaml dt-binding.

Tegra124 thru Tegra210 has 3 resets sata, sata-oob and sata-cold.
Tegra186 has 2 resets sata and sata-cold.

This patch changes order of SATA resets to maintain proper resets
order for commonly available resets across Tegra124 thru Tegra186
for dtbs_check to pass.

Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Add XUSB pad controller interrupt

This commit adds "interrupts" property to Tegra210/Tegra186/Tegra194
XUSB PADCTL node. XUSB PADCTL interrupt will be raised when USB wake
event happen

arm64: tegra: Add XUSB pad controller interrupt

This commit adds "interrupts" property to Tegra210/Tegra186/Tegra194
XUSB PADCTL node. XUSB PADCTL interrupt will be raised when USB wake
event happens. This is required for supporting XUSB host controller
ELPG.

Signed-off-by: JC Kuo <jckuo@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Rename ADMA device nodes for Tegra210

DMA device nodes should follow regex pattern of "^dma-controller(@.*)?$".
This is a preparatory patch to use YAML doc format for ADMA.

Signed-off

arm64: tegra: Rename ADMA device nodes for Tegra210

DMA device nodes should follow regex pattern of "^dma-controller(@.*)?$".
This is a preparatory patch to use YAML doc format for ADMA.

Signed-off-by: Sameer Pujar <spujar@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Add missing hot temperatures to Tegra210 thermal-zones

According to dmesg, thermal-zones for mem and cpu are missing hot
temperatures properties.

throttrip: pll: missing hot tempera

arm64: tegra: Add missing hot temperatures to Tegra210 thermal-zones

According to dmesg, thermal-zones for mem and cpu are missing hot
temperatures properties.

throttrip: pll: missing hot temperature
...
throttrip: mem: missing hot temperature
...

Adding them will clear the messages.

Signed-off-by: Nicolas Chauvet <kwizart@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Add missing gpu-throt-level to Tegra210 soctherm

On Jetson TX1 the following message can be seen:

tegra_soctherm 700e2000.thermal-sensor: throttle-cfg: heavy: no throt prop or invali

arm64: tegra: Add missing gpu-throt-level to Tegra210 soctherm

On Jetson TX1 the following message can be seen:

tegra_soctherm 700e2000.thermal-sensor: throttle-cfg: heavy: no throt prop or invalid prop

This patch will fix the invalid prop issue according to the binding.

Signed-off-by: Nicolas Chauvet <kwizart@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Add power-domain for Tegra210 HDA

commit 1e0ca5467445bc1f41a9e403d6161a22f313dae7 upstream.

HDA initialization is failing occasionally on Tegra210 and following
print is observed in t

arm64: tegra: Add power-domain for Tegra210 HDA

commit 1e0ca5467445bc1f41a9e403d6161a22f313dae7 upstream.

HDA initialization is failing occasionally on Tegra210 and following
print is observed in the boot log. Because of this probe() fails and
no sound card is registered.

[16.800802] tegra-hda 70030000.hda: no codecs found!

Codecs request a state change and enumeration by the controller. In
failure cases this does not seem to happen as STATETS register reads 0.

The problem seems to be related to the HDA codec dependency on SOR
power domain. If it is gated during HDA probe then the failure is
observed. Building Tegra HDA driver into kernel image avoids this
failure but does not completely address the dependency part. Fix this
problem by adding 'power-domains' DT property for Tegra210 HDA. Note
that Tegra186 and Tegra194 HDA do this already.

Fixes: 742af7e7a0a1 ("arm64: tegra: Add Tegra210 support")
Depends-on: 96d1f078ff0 ("arm64: tegra: Add SOR power-domain for Tegra210")
Cc: <stable@vger.kernel.org>
Signed-off-by: Sameer Pujar <spujar@nvidia.com>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

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arm64: tegra: Add DT binding for AHUB components

This patch adds few AHUB modules for Tegra210, Tegra186 and Tegra194.
Bindings for following modules are added.
* AHUB added as a child node under A

arm64: tegra: Add DT binding for AHUB components

This patch adds few AHUB modules for Tegra210, Tegra186 and Tegra194.
Bindings for following modules are added.
* AHUB added as a child node under ACONNECT
* AHUB includes many HW accelerators and below components are added
as its children.
* ADMAIF
* I2S
* DMIC
* DSPK (added for Tegra186 and Tegra194 only, since Tegra210 does
not have this module)

Signed-off-by: Sameer Pujar <spujar@nvidia.com>
Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Add missing timeout clock to Tegra210 SDMMC

commit 742af7e7a0a1 ("arm64: tegra: Add Tegra210 support")

Tegra210 uses separate SDMMC_LEGACY_TM clock for data timeout and
this clock is

arm64: tegra: Add missing timeout clock to Tegra210 SDMMC

commit 742af7e7a0a1 ("arm64: tegra: Add Tegra210 support")

Tegra210 uses separate SDMMC_LEGACY_TM clock for data timeout and
this clock is not enabled currently which is not recommended.

Tegra SDMMC advertises 12Mhz as timeout clock frequency in host
capability register.

So, this clock should be kept enabled by SDMMC driver.

Fixes: 742af7e7a0a1 ("arm64: tegra: Add Tegra210 support")
Cc: stable <stable@vger.kernel.org> # 5.4
Tested-by: Jon Hunter <jonathanh@nvidia.com>
Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
Link: https://lore.kernel.org/r/1598548861-32373-5-git-send-email-skomatineni@nvidia.com
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>

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arm64: tegra: Describe display controller outputs for Tegra210

Both display controllers can drive both DSI and both SOR outputs on
Tegra210. Describe this in device tree so that the operating system

arm64: tegra: Describe display controller outputs for Tegra210

Both display controllers can drive both DSI and both SOR outputs on
Tegra210. Describe this in device tree so that the operating system
doesn't have to guess.

Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Add #{address,size}-cells for VI I2C on Tegra210

The VI I2C controller provides an I2C bus and therefore needs to define
the #address-cells and #size-cells properties.

Signed-off-by:

arm64: tegra: Add #{address,size}-cells for VI I2C on Tegra210

The VI I2C controller provides an I2C bus and therefore needs to define
the #address-cells and #size-cells properties.

Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Add missing clocks and power-domains to Tegra210 VI I2C

Tegra210 VI I2C is in VE power domain and i2c-vi node should have
power-domains property.

Current Tegra210 i2c-vi device node i

arm64: tegra: Add missing clocks and power-domains to Tegra210 VI I2C

Tegra210 VI I2C is in VE power domain and i2c-vi node should have
power-domains property.

Current Tegra210 i2c-vi device node is missing both VI I2C clocks
and power-domains property.

This patch adds them.

Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Add clocks and resets for ISP on Tegra210

The ISP blocks take a clock and a reset as inputs, so add those to the
device tree nodes.

Signed-off-by: Thierry Reding <treding@nvidia.com>

arm64: tegra: Fix compatible string for DPAUX on Tegra210

The Tegra210 DPAUX controller is not compatible with that found on
Tegra124, so it must have a separate compatible string.

Signed-off-by: T

arm64: tegra: Fix compatible string for DPAUX on Tegra210

The Tegra210 DPAUX controller is not compatible with that found on
Tegra124, so it must have a separate compatible string.

Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Fix order of XUSB controller clocks

This is purely to make the json-schema validation tools happy because
they cannot deal with string arrays that may be in arbitrary order.

Signed-of

arm64: tegra: Fix order of XUSB controller clocks

This is purely to make the json-schema validation tools happy because
they cannot deal with string arrays that may be in arbitrary order.

Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Rename agic -> interrupt-controller

Device tree nodes for interrupt controllers should be named "interrupt-
controller", so rename the AGIC accordingly.

Signed-off-by: Thierry Reding

arm64: tegra: Rename agic -> interrupt-controller

Device tree nodes for interrupt controllers should be named "interrupt-
controller", so rename the AGIC accordingly.

Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Do not mark host1x as simple bus

The host1x is not a simple bus, so drop the corresponding compatible
string.

Signed-off-by: Thierry Reding <treding@nvidia.com>

arm64: tegra: Use proper tuple notation

Tuple boundaries should be marked by < and > to make it clear which
cells are part of the same tuple. This also helps the json-schema based
validation tooling

arm64: tegra: Use proper tuple notation

Tuple boundaries should be marked by < and > to make it clear which
cells are part of the same tuple. This also helps the json-schema based
validation tooling to properly parse this data.

While at it, also remove the "immovable" bit from PCI addresses. All of
these addresses are in fact "movable".

Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Rename sdhci nodes to mmc

The new json-schema based validation tools require SD/MMC controller
nodes to be named mmc. Rename all references to them.

Signed-off-by: Thierry Reding <tre

arm64: tegra: Rename sdhci nodes to mmc

The new json-schema based validation tools require SD/MMC controller
nodes to be named mmc. Rename all references to them.

Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Remove parent clock from display controllers

The display controller's parent clock depends on the output that's
consuming data from the display controller, so it needs to be specified

arm64: tegra: Remove parent clock from display controllers

The display controller's parent clock depends on the output that's
consuming data from the display controller, so it needs to be specified
as the parent of the corresponding output. The device tree bindings do
specify this, so just correct the existing device trees that get this
wrong.

Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Add interrupt-names for host1x

Interrupt names are used to distinguish between the syncpoint and
general host1x interrupts. Make sure they are available in the DT so
that drivers can u

arm64: tegra: Add interrupt-names for host1x

Interrupt names are used to distinguish between the syncpoint and
general host1x interrupts. Make sure they are available in the DT so
that drivers can use them if necessary.

Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Remove extra compatible for Tegra210 SDHCI

The SDHCI on Tegra210 is in fact not compatible with the one found on
Tegra124. Remove the extra compatible string to reflect that.

Signed-o

arm64: tegra: Remove extra compatible for Tegra210 SDHCI

The SDHCI on Tegra210 is in fact not compatible with the one found on
Tegra124. Remove the extra compatible string to reflect that.

Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Add Tegra VI CSI support in device tree

Tegra210 contains VI controller for video input capture from MIPI
CSI camera sensors and also supports built-in test pattern generator.

CSI por

arm64: tegra: Add Tegra VI CSI support in device tree

Tegra210 contains VI controller for video input capture from MIPI
CSI camera sensors and also supports built-in test pattern generator.

CSI ports can be one-to-one mapped to VI channels for capturing from
an external sensor or from built-in test pattern generator.

This patch adds support for VI and CSI and enables them in Tegra210
device tree.

Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Add reset-cells to memory controller

Tegra210 device tree is missing reset-cells property for the memory
controller node. This patch adds it.

Signed-off-by: Sowjanya Komatineni <skoma

arm64: tegra: Add reset-cells to memory controller

Tegra210 device tree is missing reset-cells property for the memory
controller node. This patch adds it.

Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Fix SOR powergate clocks and reset

Tegra210 device tree lists CSI clock and reset under SOR powergate
node.

But Tegra210 has CSICIL in SOR partition and CSI in VENC partition.

So, th

arm64: tegra: Fix SOR powergate clocks and reset

Tegra210 device tree lists CSI clock and reset under SOR powergate
node.

But Tegra210 has CSICIL in SOR partition and CSI in VENC partition.

So, this patch includes fix for SOR powergate node.

Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

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