1// SPDX-License-Identifier: GPL-2.0 2#include <dt-bindings/clock/tegra210-car.h> 3#include <dt-bindings/gpio/tegra-gpio.h> 4#include <dt-bindings/memory/tegra210-mc.h> 5#include <dt-bindings/pinctrl/pinctrl-tegra.h> 6#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 7#include <dt-bindings/reset/tegra210-car.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/thermal/tegra124-soctherm.h> 10#include <dt-bindings/soc/tegra-pmc.h> 11 12/ { 13 compatible = "nvidia,tegra210"; 14 interrupt-parent = <&lic>; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 18 pcie@1003000 { 19 compatible = "nvidia,tegra210-pcie"; 20 device_type = "pci"; 21 reg = <0x0 0x01003000 0x0 0x00000800 /* PADS registers */ 22 0x0 0x01003800 0x0 0x00000800 /* AFI registers */ 23 0x0 0x02000000 0x0 0x10000000>; /* configuration space */ 24 reg-names = "pads", "afi", "cs"; 25 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 26 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 27 interrupt-names = "intr", "msi"; 28 29 #interrupt-cells = <1>; 30 interrupt-map-mask = <0 0 0 0>; 31 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 32 33 bus-range = <0x00 0xff>; 34 #address-cells = <3>; 35 #size-cells = <2>; 36 37 ranges = <0x82000000 0 0x01000000 0x0 0x01000000 0 0x00001000 /* port 0 configuration space */ 38 0x82000000 0 0x01001000 0x0 0x01001000 0 0x00001000 /* port 1 configuration space */ 39 0x81000000 0 0x0 0x0 0x12000000 0 0x00010000 /* downstream I/O (64 KiB) */ 40 0x82000000 0 0x13000000 0x0 0x13000000 0 0x0d000000 /* non-prefetchable memory (208 MiB) */ 41 0xc2000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */ 42 43 clocks = <&tegra_car TEGRA210_CLK_PCIE>, 44 <&tegra_car TEGRA210_CLK_AFI>, 45 <&tegra_car TEGRA210_CLK_PLL_E>, 46 <&tegra_car TEGRA210_CLK_CML0>; 47 clock-names = "pex", "afi", "pll_e", "cml"; 48 resets = <&tegra_car 70>, 49 <&tegra_car 72>, 50 <&tegra_car 74>; 51 reset-names = "pex", "afi", "pcie_x"; 52 53 pinctrl-names = "default", "idle"; 54 pinctrl-0 = <&pex_dpd_disable>; 55 pinctrl-1 = <&pex_dpd_enable>; 56 57 status = "disabled"; 58 59 pci@1,0 { 60 device_type = "pci"; 61 assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>; 62 reg = <0x000800 0 0 0 0>; 63 bus-range = <0x00 0xff>; 64 status = "disabled"; 65 66 #address-cells = <3>; 67 #size-cells = <2>; 68 ranges; 69 70 nvidia,num-lanes = <4>; 71 }; 72 73 pci@2,0 { 74 device_type = "pci"; 75 assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>; 76 reg = <0x001000 0 0 0 0>; 77 bus-range = <0x00 0xff>; 78 status = "disabled"; 79 80 #address-cells = <3>; 81 #size-cells = <2>; 82 ranges; 83 84 nvidia,num-lanes = <1>; 85 }; 86 }; 87 88 host1x@50000000 { 89 compatible = "nvidia,tegra210-host1x", "simple-bus"; 90 reg = <0x0 0x50000000 0x0 0x00034000>; 91 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */ 92 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */ 93 interrupt-names = "syncpt", "host1x"; 94 clocks = <&tegra_car TEGRA210_CLK_HOST1X>; 95 clock-names = "host1x"; 96 resets = <&tegra_car 28>; 97 reset-names = "host1x"; 98 99 #address-cells = <2>; 100 #size-cells = <2>; 101 102 ranges = <0x0 0x54000000 0x0 0x54000000 0x0 0x01000000>; 103 104 iommus = <&mc TEGRA_SWGROUP_HC>; 105 106 dpaux1: dpaux@54040000 { 107 compatible = "nvidia,tegra210-dpaux"; 108 reg = <0x0 0x54040000 0x0 0x00040000>; 109 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 110 clocks = <&tegra_car TEGRA210_CLK_DPAUX1>, 111 <&tegra_car TEGRA210_CLK_PLL_DP>; 112 clock-names = "dpaux", "parent"; 113 resets = <&tegra_car 207>; 114 reset-names = "dpaux"; 115 power-domains = <&pd_sor>; 116 status = "disabled"; 117 118 state_dpaux1_aux: pinmux-aux { 119 groups = "dpaux-io"; 120 function = "aux"; 121 }; 122 123 state_dpaux1_i2c: pinmux-i2c { 124 groups = "dpaux-io"; 125 function = "i2c"; 126 }; 127 128 state_dpaux1_off: pinmux-off { 129 groups = "dpaux-io"; 130 function = "off"; 131 }; 132 133 i2c-bus { 134 #address-cells = <1>; 135 #size-cells = <0>; 136 }; 137 }; 138 139 vi@54080000 { 140 compatible = "nvidia,tegra210-vi"; 141 reg = <0x0 0x54080000 0x0 0x700>; 142 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 143 status = "disabled"; 144 assigned-clocks = <&tegra_car TEGRA210_CLK_VI>; 145 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; 146 147 clocks = <&tegra_car TEGRA210_CLK_VI>; 148 power-domains = <&pd_venc>; 149 150 #address-cells = <1>; 151 #size-cells = <1>; 152 153 ranges = <0x0 0x0 0x54080000 0x2000>; 154 155 csi@838 { 156 compatible = "nvidia,tegra210-csi"; 157 reg = <0x838 0x1300>; 158 status = "disabled"; 159 assigned-clocks = <&tegra_car TEGRA210_CLK_CILAB>, 160 <&tegra_car TEGRA210_CLK_CILCD>, 161 <&tegra_car TEGRA210_CLK_CILE>, 162 <&tegra_car TEGRA210_CLK_CSI_TPG>; 163 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_P>, 164 <&tegra_car TEGRA210_CLK_PLL_P>, 165 <&tegra_car TEGRA210_CLK_PLL_P>; 166 assigned-clock-rates = <102000000>, 167 <102000000>, 168 <102000000>, 169 <972000000>; 170 171 clocks = <&tegra_car TEGRA210_CLK_CSI>, 172 <&tegra_car TEGRA210_CLK_CILAB>, 173 <&tegra_car TEGRA210_CLK_CILCD>, 174 <&tegra_car TEGRA210_CLK_CILE>, 175 <&tegra_car TEGRA210_CLK_CSI_TPG>; 176 clock-names = "csi", "cilab", "cilcd", "cile", "csi_tpg"; 177 power-domains = <&pd_sor>; 178 }; 179 }; 180 181 tsec@54100000 { 182 compatible = "nvidia,tegra210-tsec"; 183 reg = <0x0 0x54100000 0x0 0x00040000>; 184 }; 185 186 dc@54200000 { 187 compatible = "nvidia,tegra210-dc"; 188 reg = <0x0 0x54200000 0x0 0x00040000>; 189 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 190 clocks = <&tegra_car TEGRA210_CLK_DISP1>, 191 <&tegra_car TEGRA210_CLK_PLL_P>; 192 clock-names = "dc", "parent"; 193 resets = <&tegra_car 27>; 194 reset-names = "dc"; 195 196 iommus = <&mc TEGRA_SWGROUP_DC>; 197 198 nvidia,head = <0>; 199 }; 200 201 dc@54240000 { 202 compatible = "nvidia,tegra210-dc"; 203 reg = <0x0 0x54240000 0x0 0x00040000>; 204 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 205 clocks = <&tegra_car TEGRA210_CLK_DISP2>, 206 <&tegra_car TEGRA210_CLK_PLL_P>; 207 clock-names = "dc", "parent"; 208 resets = <&tegra_car 26>; 209 reset-names = "dc"; 210 211 iommus = <&mc TEGRA_SWGROUP_DCB>; 212 213 nvidia,head = <1>; 214 }; 215 216 dsi@54300000 { 217 compatible = "nvidia,tegra210-dsi"; 218 reg = <0x0 0x54300000 0x0 0x00040000>; 219 clocks = <&tegra_car TEGRA210_CLK_DSIA>, 220 <&tegra_car TEGRA210_CLK_DSIALP>, 221 <&tegra_car TEGRA210_CLK_PLL_D_OUT0>; 222 clock-names = "dsi", "lp", "parent"; 223 resets = <&tegra_car 48>; 224 reset-names = "dsi"; 225 power-domains = <&pd_sor>; 226 nvidia,mipi-calibrate = <&mipi 0x0c0>; /* DSIA & DSIB pads */ 227 228 status = "disabled"; 229 230 #address-cells = <1>; 231 #size-cells = <0>; 232 }; 233 234 vic@54340000 { 235 compatible = "nvidia,tegra210-vic"; 236 reg = <0x0 0x54340000 0x0 0x00040000>; 237 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 238 clocks = <&tegra_car TEGRA210_CLK_VIC03>; 239 clock-names = "vic"; 240 resets = <&tegra_car 178>; 241 reset-names = "vic"; 242 243 iommus = <&mc TEGRA_SWGROUP_VIC>; 244 power-domains = <&pd_vic>; 245 }; 246 247 nvjpg@54380000 { 248 compatible = "nvidia,tegra210-nvjpg"; 249 reg = <0x0 0x54380000 0x0 0x00040000>; 250 status = "disabled"; 251 }; 252 253 dsi@54400000 { 254 compatible = "nvidia,tegra210-dsi"; 255 reg = <0x0 0x54400000 0x0 0x00040000>; 256 clocks = <&tegra_car TEGRA210_CLK_DSIB>, 257 <&tegra_car TEGRA210_CLK_DSIBLP>, 258 <&tegra_car TEGRA210_CLK_PLL_D_OUT0>; 259 clock-names = "dsi", "lp", "parent"; 260 resets = <&tegra_car 82>; 261 reset-names = "dsi"; 262 power-domains = <&pd_sor>; 263 nvidia,mipi-calibrate = <&mipi 0x300>; /* DSIC & DSID pads */ 264 265 status = "disabled"; 266 267 #address-cells = <1>; 268 #size-cells = <0>; 269 }; 270 271 nvdec@54480000 { 272 compatible = "nvidia,tegra210-nvdec"; 273 reg = <0x0 0x54480000 0x0 0x00040000>; 274 status = "disabled"; 275 }; 276 277 nvenc@544c0000 { 278 compatible = "nvidia,tegra210-nvenc"; 279 reg = <0x0 0x544c0000 0x0 0x00040000>; 280 status = "disabled"; 281 }; 282 283 tsec@54500000 { 284 compatible = "nvidia,tegra210-tsec"; 285 reg = <0x0 0x54500000 0x0 0x00040000>; 286 status = "disabled"; 287 }; 288 289 sor@54540000 { 290 compatible = "nvidia,tegra210-sor"; 291 reg = <0x0 0x54540000 0x0 0x00040000>; 292 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 293 clocks = <&tegra_car TEGRA210_CLK_SOR0>, 294 <&tegra_car TEGRA210_CLK_SOR0_OUT>, 295 <&tegra_car TEGRA210_CLK_PLL_D_OUT0>, 296 <&tegra_car TEGRA210_CLK_PLL_DP>, 297 <&tegra_car TEGRA210_CLK_SOR_SAFE>; 298 clock-names = "sor", "out", "parent", "dp", "safe"; 299 resets = <&tegra_car 182>; 300 reset-names = "sor"; 301 pinctrl-0 = <&state_dpaux_aux>; 302 pinctrl-1 = <&state_dpaux_i2c>; 303 pinctrl-2 = <&state_dpaux_off>; 304 pinctrl-names = "aux", "i2c", "off"; 305 power-domains = <&pd_sor>; 306 status = "disabled"; 307 }; 308 309 sor@54580000 { 310 compatible = "nvidia,tegra210-sor1"; 311 reg = <0x0 0x54580000 0x0 0x00040000>; 312 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 313 clocks = <&tegra_car TEGRA210_CLK_SOR1>, 314 <&tegra_car TEGRA210_CLK_SOR1_OUT>, 315 <&tegra_car TEGRA210_CLK_PLL_D2_OUT0>, 316 <&tegra_car TEGRA210_CLK_PLL_DP>, 317 <&tegra_car TEGRA210_CLK_SOR_SAFE>; 318 clock-names = "sor", "out", "parent", "dp", "safe"; 319 resets = <&tegra_car 183>; 320 reset-names = "sor"; 321 pinctrl-0 = <&state_dpaux1_aux>; 322 pinctrl-1 = <&state_dpaux1_i2c>; 323 pinctrl-2 = <&state_dpaux1_off>; 324 pinctrl-names = "aux", "i2c", "off"; 325 power-domains = <&pd_sor>; 326 status = "disabled"; 327 }; 328 329 dpaux: dpaux@545c0000 { 330 compatible = "nvidia,tegra124-dpaux"; 331 reg = <0x0 0x545c0000 0x0 0x00040000>; 332 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 333 clocks = <&tegra_car TEGRA210_CLK_DPAUX>, 334 <&tegra_car TEGRA210_CLK_PLL_DP>; 335 clock-names = "dpaux", "parent"; 336 resets = <&tegra_car 181>; 337 reset-names = "dpaux"; 338 power-domains = <&pd_sor>; 339 status = "disabled"; 340 341 state_dpaux_aux: pinmux-aux { 342 groups = "dpaux-io"; 343 function = "aux"; 344 }; 345 346 state_dpaux_i2c: pinmux-i2c { 347 groups = "dpaux-io"; 348 function = "i2c"; 349 }; 350 351 state_dpaux_off: pinmux-off { 352 groups = "dpaux-io"; 353 function = "off"; 354 }; 355 356 i2c-bus { 357 #address-cells = <1>; 358 #size-cells = <0>; 359 }; 360 }; 361 362 isp@54600000 { 363 compatible = "nvidia,tegra210-isp"; 364 reg = <0x0 0x54600000 0x0 0x00040000>; 365 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 366 status = "disabled"; 367 }; 368 369 isp@54680000 { 370 compatible = "nvidia,tegra210-isp"; 371 reg = <0x0 0x54680000 0x0 0x00040000>; 372 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 373 status = "disabled"; 374 }; 375 376 i2c@546c0000 { 377 compatible = "nvidia,tegra210-i2c-vi"; 378 reg = <0x0 0x546c0000 0x0 0x00040000>; 379 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 380 status = "disabled"; 381 }; 382 }; 383 384 gic: interrupt-controller@50041000 { 385 compatible = "arm,gic-400"; 386 #interrupt-cells = <3>; 387 interrupt-controller; 388 reg = <0x0 0x50041000 0x0 0x1000>, 389 <0x0 0x50042000 0x0 0x2000>, 390 <0x0 0x50044000 0x0 0x2000>, 391 <0x0 0x50046000 0x0 0x2000>; 392 interrupts = <GIC_PPI 9 393 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 394 interrupt-parent = <&gic>; 395 }; 396 397 gpu@57000000 { 398 compatible = "nvidia,gm20b"; 399 reg = <0x0 0x57000000 0x0 0x01000000>, 400 <0x0 0x58000000 0x0 0x01000000>; 401 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 402 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 403 interrupt-names = "stall", "nonstall"; 404 clocks = <&tegra_car TEGRA210_CLK_GPU>, 405 <&tegra_car TEGRA210_CLK_PLL_P_OUT5>, 406 <&tegra_car TEGRA210_CLK_PLL_G_REF>; 407 clock-names = "gpu", "pwr", "ref"; 408 resets = <&tegra_car 184>; 409 reset-names = "gpu"; 410 411 iommus = <&mc TEGRA_SWGROUP_GPU>; 412 413 status = "disabled"; 414 }; 415 416 lic: interrupt-controller@60004000 { 417 compatible = "nvidia,tegra210-ictlr"; 418 reg = <0x0 0x60004000 0x0 0x40>, /* primary controller */ 419 <0x0 0x60004100 0x0 0x40>, /* secondary controller */ 420 <0x0 0x60004200 0x0 0x40>, /* tertiary controller */ 421 <0x0 0x60004300 0x0 0x40>, /* quaternary controller */ 422 <0x0 0x60004400 0x0 0x40>, /* quinary controller */ 423 <0x0 0x60004500 0x0 0x40>; /* senary controller */ 424 interrupt-controller; 425 #interrupt-cells = <3>; 426 interrupt-parent = <&gic>; 427 }; 428 429 timer@60005000 { 430 compatible = "nvidia,tegra210-timer"; 431 reg = <0x0 0x60005000 0x0 0x400>; 432 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, 433 <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 434 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 435 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 436 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 437 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 438 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 439 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 440 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 441 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 442 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 443 <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>, 444 <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>, 445 <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; 446 clocks = <&tegra_car TEGRA210_CLK_TIMER>; 447 clock-names = "timer"; 448 }; 449 450 tegra_car: clock@60006000 { 451 compatible = "nvidia,tegra210-car"; 452 reg = <0x0 0x60006000 0x0 0x1000>; 453 #clock-cells = <1>; 454 #reset-cells = <1>; 455 }; 456 457 flow-controller@60007000 { 458 compatible = "nvidia,tegra210-flowctrl"; 459 reg = <0x0 0x60007000 0x0 0x1000>; 460 }; 461 462 gpio: gpio@6000d000 { 463 compatible = "nvidia,tegra210-gpio", "nvidia,tegra30-gpio"; 464 reg = <0x0 0x6000d000 0x0 0x1000>; 465 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 466 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 467 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 468 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 469 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 470 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 471 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 472 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 473 #gpio-cells = <2>; 474 gpio-controller; 475 #interrupt-cells = <2>; 476 interrupt-controller; 477 }; 478 479 apbdma: dma@60020000 { 480 compatible = "nvidia,tegra210-apbdma", "nvidia,tegra148-apbdma"; 481 reg = <0x0 0x60020000 0x0 0x1400>; 482 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 483 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 484 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 485 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 486 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 487 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 488 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 489 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 490 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 491 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 492 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 493 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 494 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 495 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 496 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 497 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 498 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 499 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 500 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 501 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 502 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 503 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 504 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 505 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 506 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 507 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 508 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 509 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 510 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 511 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 512 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 513 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 514 clocks = <&tegra_car TEGRA210_CLK_APBDMA>; 515 clock-names = "dma"; 516 resets = <&tegra_car 34>; 517 reset-names = "dma"; 518 #dma-cells = <1>; 519 }; 520 521 apbmisc@70000800 { 522 compatible = "nvidia,tegra210-apbmisc", "nvidia,tegra20-apbmisc"; 523 reg = <0x0 0x70000800 0x0 0x64>, /* Chip revision */ 524 <0x0 0x70000008 0x0 0x04>; /* Strapping options */ 525 }; 526 527 pinmux: pinmux@700008d4 { 528 compatible = "nvidia,tegra210-pinmux"; 529 reg = <0x0 0x700008d4 0x0 0x29c>, /* Pad control registers */ 530 <0x0 0x70003000 0x0 0x294>; /* Mux registers */ 531 sdmmc1_3v3_drv: sdmmc1-3v3-drv { 532 sdmmc1 { 533 nvidia,pins = "drive_sdmmc1"; 534 nvidia,pull-down-strength = <0x8>; 535 nvidia,pull-up-strength = <0x8>; 536 }; 537 }; 538 sdmmc1_1v8_drv: sdmmc1-1v8-drv { 539 sdmmc1 { 540 nvidia,pins = "drive_sdmmc1"; 541 nvidia,pull-down-strength = <0x4>; 542 nvidia,pull-up-strength = <0x3>; 543 }; 544 }; 545 sdmmc2_1v8_drv: sdmmc2-1v8-drv { 546 sdmmc2 { 547 nvidia,pins = "drive_sdmmc2"; 548 nvidia,pull-down-strength = <0x10>; 549 nvidia,pull-up-strength = <0x10>; 550 }; 551 }; 552 sdmmc3_3v3_drv: sdmmc3-3v3-drv { 553 sdmmc3 { 554 nvidia,pins = "drive_sdmmc3"; 555 nvidia,pull-down-strength = <0x8>; 556 nvidia,pull-up-strength = <0x8>; 557 }; 558 }; 559 sdmmc3_1v8_drv: sdmmc3-1v8-drv { 560 sdmmc3 { 561 nvidia,pins = "drive_sdmmc3"; 562 nvidia,pull-down-strength = <0x4>; 563 nvidia,pull-up-strength = <0x3>; 564 }; 565 }; 566 sdmmc4_1v8_drv: sdmmc4-1v8-drv { 567 sdmmc4 { 568 nvidia,pins = "drive_sdmmc4"; 569 nvidia,pull-down-strength = <0x10>; 570 nvidia,pull-up-strength = <0x10>; 571 }; 572 }; 573 }; 574 575 /* 576 * There are two serial driver i.e. 8250 based simple serial 577 * driver and APB DMA based serial driver for higher baudrate 578 * and performance. To enable the 8250 based driver, the compatible 579 * is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable 580 * the APB DMA based serial driver, the compatible is 581 * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart". 582 */ 583 uarta: serial@70006000 { 584 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; 585 reg = <0x0 0x70006000 0x0 0x40>; 586 reg-shift = <2>; 587 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 588 clocks = <&tegra_car TEGRA210_CLK_UARTA>; 589 clock-names = "serial"; 590 resets = <&tegra_car 6>; 591 reset-names = "serial"; 592 dmas = <&apbdma 8>, <&apbdma 8>; 593 dma-names = "rx", "tx"; 594 status = "disabled"; 595 }; 596 597 uartb: serial@70006040 { 598 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; 599 reg = <0x0 0x70006040 0x0 0x40>; 600 reg-shift = <2>; 601 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 602 clocks = <&tegra_car TEGRA210_CLK_UARTB>; 603 clock-names = "serial"; 604 resets = <&tegra_car 7>; 605 reset-names = "serial"; 606 dmas = <&apbdma 9>, <&apbdma 9>; 607 dma-names = "rx", "tx"; 608 status = "disabled"; 609 }; 610 611 uartc: serial@70006200 { 612 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; 613 reg = <0x0 0x70006200 0x0 0x40>; 614 reg-shift = <2>; 615 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 616 clocks = <&tegra_car TEGRA210_CLK_UARTC>; 617 clock-names = "serial"; 618 resets = <&tegra_car 55>; 619 reset-names = "serial"; 620 dmas = <&apbdma 10>, <&apbdma 10>; 621 dma-names = "rx", "tx"; 622 status = "disabled"; 623 }; 624 625 uartd: serial@70006300 { 626 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; 627 reg = <0x0 0x70006300 0x0 0x40>; 628 reg-shift = <2>; 629 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 630 clocks = <&tegra_car TEGRA210_CLK_UARTD>; 631 clock-names = "serial"; 632 resets = <&tegra_car 65>; 633 reset-names = "serial"; 634 dmas = <&apbdma 19>, <&apbdma 19>; 635 dma-names = "rx", "tx"; 636 status = "disabled"; 637 }; 638 639 pwm: pwm@7000a000 { 640 compatible = "nvidia,tegra210-pwm", "nvidia,tegra20-pwm"; 641 reg = <0x0 0x7000a000 0x0 0x100>; 642 #pwm-cells = <2>; 643 clocks = <&tegra_car TEGRA210_CLK_PWM>; 644 clock-names = "pwm"; 645 resets = <&tegra_car 17>; 646 reset-names = "pwm"; 647 status = "disabled"; 648 }; 649 650 i2c@7000c000 { 651 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; 652 reg = <0x0 0x7000c000 0x0 0x100>; 653 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 654 #address-cells = <1>; 655 #size-cells = <0>; 656 clocks = <&tegra_car TEGRA210_CLK_I2C1>; 657 clock-names = "div-clk"; 658 resets = <&tegra_car 12>; 659 reset-names = "i2c"; 660 dmas = <&apbdma 21>, <&apbdma 21>; 661 dma-names = "rx", "tx"; 662 status = "disabled"; 663 }; 664 665 i2c@7000c400 { 666 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; 667 reg = <0x0 0x7000c400 0x0 0x100>; 668 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 669 #address-cells = <1>; 670 #size-cells = <0>; 671 clocks = <&tegra_car TEGRA210_CLK_I2C2>; 672 clock-names = "div-clk"; 673 resets = <&tegra_car 54>; 674 reset-names = "i2c"; 675 dmas = <&apbdma 22>, <&apbdma 22>; 676 dma-names = "rx", "tx"; 677 status = "disabled"; 678 }; 679 680 i2c@7000c500 { 681 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; 682 reg = <0x0 0x7000c500 0x0 0x100>; 683 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 684 #address-cells = <1>; 685 #size-cells = <0>; 686 clocks = <&tegra_car TEGRA210_CLK_I2C3>; 687 clock-names = "div-clk"; 688 resets = <&tegra_car 67>; 689 reset-names = "i2c"; 690 dmas = <&apbdma 23>, <&apbdma 23>; 691 dma-names = "rx", "tx"; 692 status = "disabled"; 693 }; 694 695 i2c@7000c700 { 696 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; 697 reg = <0x0 0x7000c700 0x0 0x100>; 698 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 699 #address-cells = <1>; 700 #size-cells = <0>; 701 clocks = <&tegra_car TEGRA210_CLK_I2C4>; 702 clock-names = "div-clk"; 703 resets = <&tegra_car 103>; 704 reset-names = "i2c"; 705 dmas = <&apbdma 26>, <&apbdma 26>; 706 dma-names = "rx", "tx"; 707 pinctrl-0 = <&state_dpaux1_i2c>; 708 pinctrl-1 = <&state_dpaux1_off>; 709 pinctrl-names = "default", "idle"; 710 status = "disabled"; 711 }; 712 713 i2c@7000d000 { 714 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; 715 reg = <0x0 0x7000d000 0x0 0x100>; 716 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 717 #address-cells = <1>; 718 #size-cells = <0>; 719 clocks = <&tegra_car TEGRA210_CLK_I2C5>; 720 clock-names = "div-clk"; 721 resets = <&tegra_car 47>; 722 reset-names = "i2c"; 723 dmas = <&apbdma 24>, <&apbdma 24>; 724 dma-names = "rx", "tx"; 725 status = "disabled"; 726 }; 727 728 i2c@7000d100 { 729 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; 730 reg = <0x0 0x7000d100 0x0 0x100>; 731 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 732 #address-cells = <1>; 733 #size-cells = <0>; 734 clocks = <&tegra_car TEGRA210_CLK_I2C6>; 735 clock-names = "div-clk"; 736 resets = <&tegra_car 166>; 737 reset-names = "i2c"; 738 dmas = <&apbdma 30>, <&apbdma 30>; 739 dma-names = "rx", "tx"; 740 pinctrl-0 = <&state_dpaux_i2c>; 741 pinctrl-1 = <&state_dpaux_off>; 742 pinctrl-names = "default", "idle"; 743 status = "disabled"; 744 }; 745 746 spi@7000d400 { 747 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 748 reg = <0x0 0x7000d400 0x0 0x200>; 749 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 750 #address-cells = <1>; 751 #size-cells = <0>; 752 clocks = <&tegra_car TEGRA210_CLK_SBC1>; 753 clock-names = "spi"; 754 resets = <&tegra_car 41>; 755 reset-names = "spi"; 756 dmas = <&apbdma 15>, <&apbdma 15>; 757 dma-names = "rx", "tx"; 758 status = "disabled"; 759 }; 760 761 spi@7000d600 { 762 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 763 reg = <0x0 0x7000d600 0x0 0x200>; 764 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 765 #address-cells = <1>; 766 #size-cells = <0>; 767 clocks = <&tegra_car TEGRA210_CLK_SBC2>; 768 clock-names = "spi"; 769 resets = <&tegra_car 44>; 770 reset-names = "spi"; 771 dmas = <&apbdma 16>, <&apbdma 16>; 772 dma-names = "rx", "tx"; 773 status = "disabled"; 774 }; 775 776 spi@7000d800 { 777 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 778 reg = <0x0 0x7000d800 0x0 0x200>; 779 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 780 #address-cells = <1>; 781 #size-cells = <0>; 782 clocks = <&tegra_car TEGRA210_CLK_SBC3>; 783 clock-names = "spi"; 784 resets = <&tegra_car 46>; 785 reset-names = "spi"; 786 dmas = <&apbdma 17>, <&apbdma 17>; 787 dma-names = "rx", "tx"; 788 status = "disabled"; 789 }; 790 791 spi@7000da00 { 792 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 793 reg = <0x0 0x7000da00 0x0 0x200>; 794 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 795 #address-cells = <1>; 796 #size-cells = <0>; 797 clocks = <&tegra_car TEGRA210_CLK_SBC4>; 798 clock-names = "spi"; 799 resets = <&tegra_car 68>; 800 reset-names = "spi"; 801 dmas = <&apbdma 18>, <&apbdma 18>; 802 dma-names = "rx", "tx"; 803 status = "disabled"; 804 }; 805 806 rtc@7000e000 { 807 compatible = "nvidia,tegra210-rtc", "nvidia,tegra20-rtc"; 808 reg = <0x0 0x7000e000 0x0 0x100>; 809 interrupts = <16 IRQ_TYPE_LEVEL_HIGH>; 810 interrupt-parent = <&tegra_pmc>; 811 clocks = <&tegra_car TEGRA210_CLK_RTC>; 812 clock-names = "rtc"; 813 }; 814 815 tegra_pmc: pmc@7000e400 { 816 compatible = "nvidia,tegra210-pmc"; 817 reg = <0x0 0x7000e400 0x0 0x400>; 818 clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>; 819 clock-names = "pclk", "clk32k_in"; 820 #clock-cells = <1>; 821 #interrupt-cells = <2>; 822 interrupt-controller; 823 824 powergates { 825 pd_audio: aud { 826 clocks = <&tegra_car TEGRA210_CLK_APE>, 827 <&tegra_car TEGRA210_CLK_APB2APE>; 828 resets = <&tegra_car 198>; 829 #power-domain-cells = <0>; 830 }; 831 832 pd_sor: sor { 833 clocks = <&tegra_car TEGRA210_CLK_SOR0>, 834 <&tegra_car TEGRA210_CLK_SOR1>, 835 <&tegra_car TEGRA210_CLK_CILAB>, 836 <&tegra_car TEGRA210_CLK_CILCD>, 837 <&tegra_car TEGRA210_CLK_CILE>, 838 <&tegra_car TEGRA210_CLK_DSIA>, 839 <&tegra_car TEGRA210_CLK_DSIB>, 840 <&tegra_car TEGRA210_CLK_DPAUX>, 841 <&tegra_car TEGRA210_CLK_DPAUX1>, 842 <&tegra_car TEGRA210_CLK_MIPI_CAL>; 843 resets = <&tegra_car TEGRA210_CLK_SOR0>, 844 <&tegra_car TEGRA210_CLK_SOR1>, 845 <&tegra_car TEGRA210_CLK_DSIA>, 846 <&tegra_car TEGRA210_CLK_DSIB>, 847 <&tegra_car TEGRA210_CLK_DPAUX>, 848 <&tegra_car TEGRA210_CLK_DPAUX1>, 849 <&tegra_car TEGRA210_CLK_MIPI_CAL>; 850 #power-domain-cells = <0>; 851 }; 852 853 pd_xusbss: xusba { 854 clocks = <&tegra_car TEGRA210_CLK_XUSB_SS>; 855 resets = <&tegra_car TEGRA210_CLK_XUSB_SS>; 856 #power-domain-cells = <0>; 857 }; 858 859 pd_xusbdev: xusbb { 860 clocks = <&tegra_car TEGRA210_CLK_XUSB_DEV>; 861 resets = <&tegra_car 95>; 862 #power-domain-cells = <0>; 863 }; 864 865 pd_xusbhost: xusbc { 866 clocks = <&tegra_car TEGRA210_CLK_XUSB_HOST>; 867 resets = <&tegra_car TEGRA210_CLK_XUSB_HOST>; 868 #power-domain-cells = <0>; 869 }; 870 871 pd_vic: vic { 872 clocks = <&tegra_car TEGRA210_CLK_VIC03>; 873 clock-names = "vic"; 874 resets = <&tegra_car 178>; 875 reset-names = "vic"; 876 #power-domain-cells = <0>; 877 }; 878 879 pd_venc: venc { 880 clocks = <&tegra_car TEGRA210_CLK_VI>, 881 <&tegra_car TEGRA210_CLK_CSI>; 882 resets = <&mc TEGRA210_MC_RESET_VI>, 883 <&tegra_car 20>, 884 <&tegra_car 52>; 885 #power-domain-cells = <0>; 886 }; 887 }; 888 889 sdmmc1_3v3: sdmmc1-3v3 { 890 pins = "sdmmc1"; 891 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 892 }; 893 894 sdmmc1_1v8: sdmmc1-1v8 { 895 pins = "sdmmc1"; 896 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 897 }; 898 899 sdmmc3_3v3: sdmmc3-3v3 { 900 pins = "sdmmc3"; 901 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 902 }; 903 904 sdmmc3_1v8: sdmmc3-1v8 { 905 pins = "sdmmc3"; 906 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 907 }; 908 909 pex_dpd_disable: pex_en { 910 pex-dpd-disable { 911 pins = "pex-bias", "pex-clk1", "pex-clk2"; 912 low-power-disable; 913 }; 914 }; 915 916 pex_dpd_enable: pex_dis { 917 pex-dpd-enable { 918 pins = "pex-bias", "pex-clk1", "pex-clk2"; 919 low-power-enable; 920 }; 921 }; 922 }; 923 924 fuse@7000f800 { 925 compatible = "nvidia,tegra210-efuse"; 926 reg = <0x0 0x7000f800 0x0 0x400>; 927 clocks = <&tegra_car TEGRA210_CLK_FUSE>; 928 clock-names = "fuse"; 929 resets = <&tegra_car 39>; 930 reset-names = "fuse"; 931 }; 932 933 mc: memory-controller@70019000 { 934 compatible = "nvidia,tegra210-mc"; 935 reg = <0x0 0x70019000 0x0 0x1000>; 936 clocks = <&tegra_car TEGRA210_CLK_MC>; 937 clock-names = "mc"; 938 939 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 940 941 #iommu-cells = <1>; 942 #reset-cells = <1>; 943 }; 944 945 emc: external-memory-controller@7001b000 { 946 compatible = "nvidia,tegra210-emc"; 947 reg = <0x0 0x7001b000 0x0 0x1000>, 948 <0x0 0x7001e000 0x0 0x1000>, 949 <0x0 0x7001f000 0x0 0x1000>; 950 clocks = <&tegra_car TEGRA210_CLK_EMC>; 951 clock-names = "emc"; 952 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 953 nvidia,memory-controller = <&mc>; 954 #cooling-cells = <2>; 955 }; 956 957 sata@70020000 { 958 compatible = "nvidia,tegra210-ahci"; 959 reg = <0x0 0x70027000 0x0 0x2000>, /* AHCI */ 960 <0x0 0x70020000 0x0 0x7000>, /* SATA */ 961 <0x0 0x70001100 0x0 0x1000>; /* SATA AUX */ 962 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 963 clocks = <&tegra_car TEGRA210_CLK_SATA>, 964 <&tegra_car TEGRA210_CLK_SATA_OOB>; 965 clock-names = "sata", "sata-oob"; 966 resets = <&tegra_car 124>, 967 <&tegra_car 123>, 968 <&tegra_car 129>; 969 reset-names = "sata", "sata-oob", "sata-cold"; 970 status = "disabled"; 971 }; 972 973 hda@70030000 { 974 compatible = "nvidia,tegra210-hda", "nvidia,tegra30-hda"; 975 reg = <0x0 0x70030000 0x0 0x10000>; 976 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 977 clocks = <&tegra_car TEGRA210_CLK_HDA>, 978 <&tegra_car TEGRA210_CLK_HDA2HDMI>, 979 <&tegra_car TEGRA210_CLK_HDA2CODEC_2X>; 980 clock-names = "hda", "hda2hdmi", "hda2codec_2x"; 981 resets = <&tegra_car 125>, /* hda */ 982 <&tegra_car 128>, /* hda2hdmi */ 983 <&tegra_car 111>; /* hda2codec_2x */ 984 reset-names = "hda", "hda2hdmi", "hda2codec_2x"; 985 status = "disabled"; 986 }; 987 988 usb@70090000 { 989 compatible = "nvidia,tegra210-xusb"; 990 reg = <0x0 0x70090000 0x0 0x8000>, 991 <0x0 0x70098000 0x0 0x1000>, 992 <0x0 0x70099000 0x0 0x1000>; 993 reg-names = "hcd", "fpci", "ipfs"; 994 995 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 996 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 997 998 clocks = <&tegra_car TEGRA210_CLK_XUSB_HOST>, 999 <&tegra_car TEGRA210_CLK_XUSB_HOST_SRC>, 1000 <&tegra_car TEGRA210_CLK_XUSB_FALCON_SRC>, 1001 <&tegra_car TEGRA210_CLK_XUSB_SS>, 1002 <&tegra_car TEGRA210_CLK_XUSB_SS_DIV2>, 1003 <&tegra_car TEGRA210_CLK_XUSB_SS_SRC>, 1004 <&tegra_car TEGRA210_CLK_XUSB_HS_SRC>, 1005 <&tegra_car TEGRA210_CLK_XUSB_FS_SRC>, 1006 <&tegra_car TEGRA210_CLK_PLL_U_480M>, 1007 <&tegra_car TEGRA210_CLK_CLK_M>, 1008 <&tegra_car TEGRA210_CLK_PLL_E>; 1009 clock-names = "xusb_host", "xusb_host_src", 1010 "xusb_falcon_src", "xusb_ss", 1011 "xusb_ss_div2", "xusb_ss_src", 1012 "xusb_hs_src", "xusb_fs_src", 1013 "pll_u_480m", "clk_m", "pll_e"; 1014 resets = <&tegra_car 89>, <&tegra_car 156>, 1015 <&tegra_car 143>; 1016 reset-names = "xusb_host", "xusb_ss", "xusb_src"; 1017 power-domains = <&pd_xusbhost>, <&pd_xusbss>; 1018 power-domain-names = "xusb_host", "xusb_ss"; 1019 1020 nvidia,xusb-padctl = <&padctl>; 1021 1022 status = "disabled"; 1023 }; 1024 1025 padctl: padctl@7009f000 { 1026 compatible = "nvidia,tegra210-xusb-padctl"; 1027 reg = <0x0 0x7009f000 0x0 0x1000>; 1028 resets = <&tegra_car 142>; 1029 reset-names = "padctl"; 1030 1031 status = "disabled"; 1032 1033 pads { 1034 usb2 { 1035 clocks = <&tegra_car TEGRA210_CLK_USB2_TRK>; 1036 clock-names = "trk"; 1037 status = "disabled"; 1038 1039 lanes { 1040 usb2-0 { 1041 status = "disabled"; 1042 #phy-cells = <0>; 1043 }; 1044 1045 usb2-1 { 1046 status = "disabled"; 1047 #phy-cells = <0>; 1048 }; 1049 1050 usb2-2 { 1051 status = "disabled"; 1052 #phy-cells = <0>; 1053 }; 1054 1055 usb2-3 { 1056 status = "disabled"; 1057 #phy-cells = <0>; 1058 }; 1059 }; 1060 }; 1061 1062 hsic { 1063 clocks = <&tegra_car TEGRA210_CLK_HSIC_TRK>; 1064 clock-names = "trk"; 1065 status = "disabled"; 1066 1067 lanes { 1068 hsic-0 { 1069 status = "disabled"; 1070 #phy-cells = <0>; 1071 }; 1072 1073 hsic-1 { 1074 status = "disabled"; 1075 #phy-cells = <0>; 1076 }; 1077 }; 1078 }; 1079 1080 pcie { 1081 clocks = <&tegra_car TEGRA210_CLK_PLL_E>; 1082 clock-names = "pll"; 1083 resets = <&tegra_car 205>; 1084 reset-names = "phy"; 1085 status = "disabled"; 1086 1087 lanes { 1088 pcie-0 { 1089 status = "disabled"; 1090 #phy-cells = <0>; 1091 }; 1092 1093 pcie-1 { 1094 status = "disabled"; 1095 #phy-cells = <0>; 1096 }; 1097 1098 pcie-2 { 1099 status = "disabled"; 1100 #phy-cells = <0>; 1101 }; 1102 1103 pcie-3 { 1104 status = "disabled"; 1105 #phy-cells = <0>; 1106 }; 1107 1108 pcie-4 { 1109 status = "disabled"; 1110 #phy-cells = <0>; 1111 }; 1112 1113 pcie-5 { 1114 status = "disabled"; 1115 #phy-cells = <0>; 1116 }; 1117 1118 pcie-6 { 1119 status = "disabled"; 1120 #phy-cells = <0>; 1121 }; 1122 }; 1123 }; 1124 1125 sata { 1126 clocks = <&tegra_car TEGRA210_CLK_PLL_E>; 1127 clock-names = "pll"; 1128 resets = <&tegra_car 204>; 1129 reset-names = "phy"; 1130 status = "disabled"; 1131 1132 lanes { 1133 sata-0 { 1134 status = "disabled"; 1135 #phy-cells = <0>; 1136 }; 1137 }; 1138 }; 1139 }; 1140 1141 ports { 1142 usb2-0 { 1143 status = "disabled"; 1144 }; 1145 1146 usb2-1 { 1147 status = "disabled"; 1148 }; 1149 1150 usb2-2 { 1151 status = "disabled"; 1152 }; 1153 1154 usb2-3 { 1155 status = "disabled"; 1156 }; 1157 1158 hsic-0 { 1159 status = "disabled"; 1160 }; 1161 1162 usb3-0 { 1163 status = "disabled"; 1164 }; 1165 1166 usb3-1 { 1167 status = "disabled"; 1168 }; 1169 1170 usb3-2 { 1171 status = "disabled"; 1172 }; 1173 1174 usb3-3 { 1175 status = "disabled"; 1176 }; 1177 }; 1178 }; 1179 1180 sdhci@700b0000 { 1181 compatible = "nvidia,tegra210-sdhci"; 1182 reg = <0x0 0x700b0000 0x0 0x200>; 1183 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1184 clocks = <&tegra_car TEGRA210_CLK_SDMMC1>; 1185 clock-names = "sdhci"; 1186 resets = <&tegra_car 14>; 1187 reset-names = "sdhci"; 1188 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8", 1189 "sdmmc-3v3-drv", "sdmmc-1v8-drv"; 1190 pinctrl-0 = <&sdmmc1_3v3>; 1191 pinctrl-1 = <&sdmmc1_1v8>; 1192 pinctrl-2 = <&sdmmc1_3v3_drv>; 1193 pinctrl-3 = <&sdmmc1_1v8_drv>; 1194 nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>; 1195 nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>; 1196 nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>; 1197 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7b>; 1198 nvidia,default-tap = <0x2>; 1199 nvidia,default-trim = <0x4>; 1200 assigned-clocks = <&tegra_car TEGRA210_CLK_SDMMC4>, 1201 <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>, 1202 <&tegra_car TEGRA210_CLK_PLL_C4>; 1203 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; 1204 assigned-clock-rates = <200000000>, <1000000000>, <1000000000>; 1205 status = "disabled"; 1206 }; 1207 1208 sdhci@700b0200 { 1209 compatible = "nvidia,tegra210-sdhci"; 1210 reg = <0x0 0x700b0200 0x0 0x200>; 1211 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 1212 clocks = <&tegra_car TEGRA210_CLK_SDMMC2>; 1213 clock-names = "sdhci"; 1214 resets = <&tegra_car 9>; 1215 reset-names = "sdhci"; 1216 pinctrl-names = "sdmmc-1v8-drv"; 1217 pinctrl-0 = <&sdmmc2_1v8_drv>; 1218 nvidia,pad-autocal-pull-up-offset-1v8 = <0x05>; 1219 nvidia,pad-autocal-pull-down-offset-1v8 = <0x05>; 1220 nvidia,default-tap = <0x8>; 1221 nvidia,default-trim = <0x0>; 1222 status = "disabled"; 1223 }; 1224 1225 sdhci@700b0400 { 1226 compatible = "nvidia,tegra210-sdhci"; 1227 reg = <0x0 0x700b0400 0x0 0x200>; 1228 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 1229 clocks = <&tegra_car TEGRA210_CLK_SDMMC3>; 1230 clock-names = "sdhci"; 1231 resets = <&tegra_car 69>; 1232 reset-names = "sdhci"; 1233 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8", 1234 "sdmmc-3v3-drv", "sdmmc-1v8-drv"; 1235 pinctrl-0 = <&sdmmc3_3v3>; 1236 pinctrl-1 = <&sdmmc3_1v8>; 1237 pinctrl-2 = <&sdmmc3_3v3_drv>; 1238 pinctrl-3 = <&sdmmc3_1v8_drv>; 1239 nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>; 1240 nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>; 1241 nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>; 1242 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7b>; 1243 nvidia,default-tap = <0x3>; 1244 nvidia,default-trim = <0x3>; 1245 status = "disabled"; 1246 }; 1247 1248 sdhci@700b0600 { 1249 compatible = "nvidia,tegra210-sdhci"; 1250 reg = <0x0 0x700b0600 0x0 0x200>; 1251 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 1252 clocks = <&tegra_car TEGRA210_CLK_SDMMC4>; 1253 clock-names = "sdhci"; 1254 resets = <&tegra_car 15>; 1255 reset-names = "sdhci"; 1256 pinctrl-names = "sdmmc-3v3-drv", "sdmmc-1v8-drv"; 1257 pinctrl-0 = <&sdmmc4_1v8_drv>; 1258 pinctrl-1 = <&sdmmc4_1v8_drv>; 1259 nvidia,pad-autocal-pull-up-offset-1v8 = <0x05>; 1260 nvidia,pad-autocal-pull-down-offset-1v8 = <0x05>; 1261 nvidia,default-tap = <0x8>; 1262 nvidia,default-trim = <0x0>; 1263 assigned-clocks = <&tegra_car TEGRA210_CLK_SDMMC4>, 1264 <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; 1265 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; 1266 nvidia,dqs-trim = <40>; 1267 mmc-hs400-1_8v; 1268 status = "disabled"; 1269 }; 1270 1271 usb@700d0000 { 1272 compatible = "nvidia,tegra210-xudc"; 1273 reg = <0x0 0x700d0000 0x0 0x8000>, 1274 <0x0 0x700d8000 0x0 0x1000>, 1275 <0x0 0x700d9000 0x0 0x1000>; 1276 reg-names = "base", "fpci", "ipfs"; 1277 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 1278 clocks = <&tegra_car TEGRA210_CLK_XUSB_DEV>, 1279 <&tegra_car TEGRA210_CLK_XUSB_SS>, 1280 <&tegra_car TEGRA210_CLK_XUSB_SSP_SRC>, 1281 <&tegra_car TEGRA210_CLK_XUSB_FS_SRC>, 1282 <&tegra_car TEGRA210_CLK_XUSB_HS_SRC>; 1283 clock-names = "dev", "ss", "ss_src", "fs_src", "hs_src"; 1284 power-domains = <&pd_xusbdev>, <&pd_xusbss>; 1285 power-domain-names = "dev", "ss"; 1286 nvidia,xusb-padctl = <&padctl>; 1287 status = "disabled"; 1288 }; 1289 1290 mipi: mipi@700e3000 { 1291 compatible = "nvidia,tegra210-mipi"; 1292 reg = <0x0 0x700e3000 0x0 0x100>; 1293 clocks = <&tegra_car TEGRA210_CLK_MIPI_CAL>; 1294 clock-names = "mipi-cal"; 1295 power-domains = <&pd_sor>; 1296 #nvidia,mipi-calibrate-cells = <1>; 1297 }; 1298 1299 dfll: clock@70110000 { 1300 compatible = "nvidia,tegra210-dfll"; 1301 reg = <0 0x70110000 0 0x100>, /* DFLL control */ 1302 <0 0x70110000 0 0x100>, /* I2C output control */ 1303 <0 0x70110100 0 0x100>, /* Integrated I2C controller */ 1304 <0 0x70110200 0 0x100>; /* Look-up table RAM */ 1305 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 1306 clocks = <&tegra_car TEGRA210_CLK_DFLL_SOC>, 1307 <&tegra_car TEGRA210_CLK_DFLL_REF>, 1308 <&tegra_car TEGRA210_CLK_I2C5>; 1309 clock-names = "soc", "ref", "i2c"; 1310 resets = <&tegra_car TEGRA210_RST_DFLL_DVCO>; 1311 reset-names = "dvco"; 1312 #clock-cells = <0>; 1313 clock-output-names = "dfllCPU_out"; 1314 status = "disabled"; 1315 }; 1316 1317 aconnect@702c0000 { 1318 compatible = "nvidia,tegra210-aconnect"; 1319 clocks = <&tegra_car TEGRA210_CLK_APE>, 1320 <&tegra_car TEGRA210_CLK_APB2APE>; 1321 clock-names = "ape", "apb2ape"; 1322 power-domains = <&pd_audio>; 1323 #address-cells = <1>; 1324 #size-cells = <1>; 1325 ranges = <0x702c0000 0x0 0x702c0000 0x00040000>; 1326 status = "disabled"; 1327 1328 adma: dma@702e2000 { 1329 compatible = "nvidia,tegra210-adma"; 1330 reg = <0x702e2000 0x2000>; 1331 interrupt-parent = <&agic>; 1332 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 1333 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 1334 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 1335 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 1336 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 1337 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 1338 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 1339 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 1340 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 1341 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 1342 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 1343 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 1344 <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, 1345 <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, 1346 <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, 1347 <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 1348 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 1349 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 1350 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 1351 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 1352 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 1353 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 1354 #dma-cells = <1>; 1355 clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>; 1356 clock-names = "d_audio"; 1357 status = "disabled"; 1358 }; 1359 1360 agic: agic@702f9000 { 1361 compatible = "nvidia,tegra210-agic"; 1362 #interrupt-cells = <3>; 1363 interrupt-controller; 1364 reg = <0x702f9000 0x1000>, 1365 <0x702fa000 0x2000>; 1366 interrupts = <GIC_SPI 102 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 1367 clocks = <&tegra_car TEGRA210_CLK_APE>; 1368 clock-names = "clk"; 1369 status = "disabled"; 1370 }; 1371 }; 1372 1373 spi@70410000 { 1374 compatible = "nvidia,tegra210-qspi"; 1375 reg = <0x0 0x70410000 0x0 0x1000>; 1376 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 1377 #address-cells = <1>; 1378 #size-cells = <0>; 1379 clocks = <&tegra_car TEGRA210_CLK_QSPI>; 1380 clock-names = "qspi"; 1381 resets = <&tegra_car 211>; 1382 reset-names = "qspi"; 1383 dmas = <&apbdma 5>, <&apbdma 5>; 1384 dma-names = "rx", "tx"; 1385 status = "disabled"; 1386 }; 1387 1388 usb@7d000000 { 1389 compatible = "nvidia,tegra210-ehci", "nvidia,tegra30-ehci", "usb-ehci"; 1390 reg = <0x0 0x7d000000 0x0 0x4000>; 1391 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 1392 phy_type = "utmi"; 1393 clocks = <&tegra_car TEGRA210_CLK_USBD>; 1394 clock-names = "usb"; 1395 resets = <&tegra_car 22>; 1396 reset-names = "usb"; 1397 nvidia,phy = <&phy1>; 1398 status = "disabled"; 1399 }; 1400 1401 phy1: usb-phy@7d000000 { 1402 compatible = "nvidia,tegra210-usb-phy", "nvidia,tegra30-usb-phy"; 1403 reg = <0x0 0x7d000000 0x0 0x4000>, 1404 <0x0 0x7d000000 0x0 0x4000>; 1405 phy_type = "utmi"; 1406 clocks = <&tegra_car TEGRA210_CLK_USBD>, 1407 <&tegra_car TEGRA210_CLK_PLL_U>, 1408 <&tegra_car TEGRA210_CLK_USBD>; 1409 clock-names = "reg", "pll_u", "utmi-pads"; 1410 resets = <&tegra_car 22>, <&tegra_car 22>; 1411 reset-names = "usb", "utmi-pads"; 1412 nvidia,hssync-start-delay = <0>; 1413 nvidia,idle-wait-delay = <17>; 1414 nvidia,elastic-limit = <16>; 1415 nvidia,term-range-adj = <6>; 1416 nvidia,xcvr-setup = <9>; 1417 nvidia,xcvr-lsfslew = <0>; 1418 nvidia,xcvr-lsrslew = <3>; 1419 nvidia,hssquelch-level = <2>; 1420 nvidia,hsdiscon-level = <5>; 1421 nvidia,xcvr-hsslew = <12>; 1422 nvidia,has-utmi-pad-registers; 1423 status = "disabled"; 1424 }; 1425 1426 usb@7d004000 { 1427 compatible = "nvidia,tegra210-ehci", "nvidia,tegra30-ehci", "usb-ehci"; 1428 reg = <0x0 0x7d004000 0x0 0x4000>; 1429 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 1430 phy_type = "utmi"; 1431 clocks = <&tegra_car TEGRA210_CLK_USB2>; 1432 clock-names = "usb"; 1433 resets = <&tegra_car 58>; 1434 reset-names = "usb"; 1435 nvidia,phy = <&phy2>; 1436 status = "disabled"; 1437 }; 1438 1439 phy2: usb-phy@7d004000 { 1440 compatible = "nvidia,tegra210-usb-phy", "nvidia,tegra30-usb-phy"; 1441 reg = <0x0 0x7d004000 0x0 0x4000>, 1442 <0x0 0x7d000000 0x0 0x4000>; 1443 phy_type = "utmi"; 1444 clocks = <&tegra_car TEGRA210_CLK_USB2>, 1445 <&tegra_car TEGRA210_CLK_PLL_U>, 1446 <&tegra_car TEGRA210_CLK_USBD>; 1447 clock-names = "reg", "pll_u", "utmi-pads"; 1448 resets = <&tegra_car 58>, <&tegra_car 22>; 1449 reset-names = "usb", "utmi-pads"; 1450 nvidia,hssync-start-delay = <0>; 1451 nvidia,idle-wait-delay = <17>; 1452 nvidia,elastic-limit = <16>; 1453 nvidia,term-range-adj = <6>; 1454 nvidia,xcvr-setup = <9>; 1455 nvidia,xcvr-lsfslew = <0>; 1456 nvidia,xcvr-lsrslew = <3>; 1457 nvidia,hssquelch-level = <2>; 1458 nvidia,hsdiscon-level = <5>; 1459 nvidia,xcvr-hsslew = <12>; 1460 status = "disabled"; 1461 }; 1462 1463 cpus { 1464 #address-cells = <1>; 1465 #size-cells = <0>; 1466 1467 cpu@0 { 1468 device_type = "cpu"; 1469 compatible = "arm,cortex-a57"; 1470 reg = <0>; 1471 clocks = <&tegra_car TEGRA210_CLK_CCLK_G>, 1472 <&tegra_car TEGRA210_CLK_PLL_X>, 1473 <&tegra_car TEGRA210_CLK_PLL_P_OUT4>, 1474 <&dfll>; 1475 clock-names = "cpu_g", "pll_x", "pll_p", "dfll"; 1476 clock-latency = <300000>; 1477 cpu-idle-states = <&CPU_SLEEP>; 1478 next-level-cache = <&L2>; 1479 }; 1480 1481 cpu@1 { 1482 device_type = "cpu"; 1483 compatible = "arm,cortex-a57"; 1484 reg = <1>; 1485 cpu-idle-states = <&CPU_SLEEP>; 1486 next-level-cache = <&L2>; 1487 }; 1488 1489 cpu@2 { 1490 device_type = "cpu"; 1491 compatible = "arm,cortex-a57"; 1492 reg = <2>; 1493 cpu-idle-states = <&CPU_SLEEP>; 1494 next-level-cache = <&L2>; 1495 }; 1496 1497 cpu@3 { 1498 device_type = "cpu"; 1499 compatible = "arm,cortex-a57"; 1500 reg = <3>; 1501 cpu-idle-states = <&CPU_SLEEP>; 1502 next-level-cache = <&L2>; 1503 }; 1504 1505 idle-states { 1506 entry-method = "psci"; 1507 1508 CPU_SLEEP: cpu-sleep { 1509 compatible = "arm,idle-state"; 1510 arm,psci-suspend-param = <0x40000007>; 1511 entry-latency-us = <100>; 1512 exit-latency-us = <30>; 1513 min-residency-us = <1000>; 1514 wakeup-latency-us = <130>; 1515 idle-state-name = "cpu-sleep"; 1516 status = "disabled"; 1517 }; 1518 }; 1519 1520 L2: l2-cache { 1521 compatible = "cache"; 1522 }; 1523 }; 1524 1525 pmu { 1526 compatible = "arm,armv8-pmuv3"; 1527 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 1528 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 1529 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 1530 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; 1531 interrupt-affinity = <&{/cpus/cpu@0} &{/cpus/cpu@1} 1532 &{/cpus/cpu@2} &{/cpus/cpu@3}>; 1533 }; 1534 1535 timer { 1536 compatible = "arm,armv8-timer"; 1537 interrupts = <GIC_PPI 13 1538 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1539 <GIC_PPI 14 1540 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1541 <GIC_PPI 11 1542 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1543 <GIC_PPI 10 1544 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 1545 interrupt-parent = <&gic>; 1546 arm,no-tick-in-suspend; 1547 }; 1548 1549 soctherm: thermal-sensor@700e2000 { 1550 compatible = "nvidia,tegra210-soctherm"; 1551 reg = <0x0 0x700e2000 0x0 0x600 /* SOC_THERM reg_base */ 1552 0x0 0x60006000 0x0 0x400>; /* CAR reg_base */ 1553 reg-names = "soctherm-reg", "car-reg"; 1554 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, 1555 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 1556 interrupt-names = "thermal", "edp"; 1557 clocks = <&tegra_car TEGRA210_CLK_TSENSOR>, 1558 <&tegra_car TEGRA210_CLK_SOC_THERM>; 1559 clock-names = "tsensor", "soctherm"; 1560 resets = <&tegra_car 78>; 1561 reset-names = "soctherm"; 1562 #thermal-sensor-cells = <1>; 1563 1564 throttle-cfgs { 1565 throttle_heavy: heavy { 1566 nvidia,priority = <100>; 1567 nvidia,cpu-throt-percent = <85>; 1568 1569 #cooling-cells = <2>; 1570 }; 1571 }; 1572 }; 1573 1574 thermal-zones { 1575 cpu { 1576 polling-delay-passive = <1000>; 1577 polling-delay = <0>; 1578 1579 thermal-sensors = 1580 <&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>; 1581 1582 trips { 1583 cpu-shutdown-trip { 1584 temperature = <102500>; 1585 hysteresis = <0>; 1586 type = "critical"; 1587 }; 1588 1589 cpu_throttle_trip: throttle-trip { 1590 temperature = <98500>; 1591 hysteresis = <1000>; 1592 type = "hot"; 1593 }; 1594 }; 1595 1596 cooling-maps { 1597 map0 { 1598 trip = <&cpu_throttle_trip>; 1599 cooling-device = <&throttle_heavy 1 1>; 1600 }; 1601 }; 1602 }; 1603 1604 mem { 1605 polling-delay-passive = <0>; 1606 polling-delay = <0>; 1607 1608 thermal-sensors = 1609 <&soctherm TEGRA124_SOCTHERM_SENSOR_MEM>; 1610 1611 trips { 1612 dram_nominal: mem-nominal-trip { 1613 temperature = <50000>; 1614 hysteresis = <1000>; 1615 type = "passive"; 1616 }; 1617 1618 dram_throttle: mem-throttle-trip { 1619 temperature = <70000>; 1620 hysteresis = <1000>; 1621 type = "active"; 1622 }; 1623 1624 mem-shutdown-trip { 1625 temperature = <103000>; 1626 hysteresis = <0>; 1627 type = "critical"; 1628 }; 1629 }; 1630 1631 cooling-maps { 1632 dram-passive { 1633 cooling-device = <&emc 0 0>; 1634 trip = <&dram_nominal>; 1635 }; 1636 1637 dram-active { 1638 cooling-device = <&emc 1 1>; 1639 trip = <&dram_throttle>; 1640 }; 1641 }; 1642 }; 1643 1644 gpu { 1645 polling-delay-passive = <1000>; 1646 polling-delay = <0>; 1647 1648 thermal-sensors = 1649 <&soctherm TEGRA124_SOCTHERM_SENSOR_GPU>; 1650 1651 trips { 1652 gpu-shutdown-trip { 1653 temperature = <103000>; 1654 hysteresis = <0>; 1655 type = "critical"; 1656 }; 1657 1658 gpu_throttle_trip: throttle-trip { 1659 temperature = <100000>; 1660 hysteresis = <1000>; 1661 type = "hot"; 1662 }; 1663 }; 1664 1665 cooling-maps { 1666 map0 { 1667 trip = <&gpu_throttle_trip>; 1668 cooling-device = <&throttle_heavy 1 1>; 1669 }; 1670 }; 1671 }; 1672 1673 pllx { 1674 polling-delay-passive = <0>; 1675 polling-delay = <0>; 1676 1677 thermal-sensors = 1678 <&soctherm TEGRA124_SOCTHERM_SENSOR_PLLX>; 1679 1680 trips { 1681 pllx-shutdown-trip { 1682 temperature = <103000>; 1683 hysteresis = <0>; 1684 type = "critical"; 1685 }; 1686 }; 1687 1688 cooling-maps { 1689 /* 1690 * There are currently no cooling maps, 1691 * because there are no cooling devices. 1692 */ 1693 }; 1694 }; 1695 }; 1696}; 1697