1// SPDX-License-Identifier: GPL-2.0 2#include <dt-bindings/clock/tegra210-car.h> 3#include <dt-bindings/gpio/tegra-gpio.h> 4#include <dt-bindings/memory/tegra210-mc.h> 5#include <dt-bindings/pinctrl/pinctrl-tegra.h> 6#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 7#include <dt-bindings/reset/tegra210-car.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/thermal/tegra124-soctherm.h> 10#include <dt-bindings/soc/tegra-pmc.h> 11 12/ { 13 compatible = "nvidia,tegra210"; 14 interrupt-parent = <&lic>; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 18 pcie@1003000 { 19 compatible = "nvidia,tegra210-pcie"; 20 device_type = "pci"; 21 reg = <0x0 0x01003000 0x0 0x00000800>, /* PADS registers */ 22 <0x0 0x01003800 0x0 0x00000800>, /* AFI registers */ 23 <0x0 0x02000000 0x0 0x10000000>; /* configuration space */ 24 reg-names = "pads", "afi", "cs"; 25 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 26 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 27 interrupt-names = "intr", "msi"; 28 29 #interrupt-cells = <1>; 30 interrupt-map-mask = <0 0 0 0>; 31 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 32 33 bus-range = <0x00 0xff>; 34 #address-cells = <3>; 35 #size-cells = <2>; 36 37 ranges = <0x02000000 0 0x01000000 0x0 0x01000000 0 0x00001000>, /* port 0 configuration space */ 38 <0x02000000 0 0x01001000 0x0 0x01001000 0 0x00001000>, /* port 1 configuration space */ 39 <0x01000000 0 0x0 0x0 0x12000000 0 0x00010000>, /* downstream I/O (64 KiB) */ 40 <0x02000000 0 0x13000000 0x0 0x13000000 0 0x0d000000>, /* non-prefetchable memory (208 MiB) */ 41 <0x42000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */ 42 43 clocks = <&tegra_car TEGRA210_CLK_PCIE>, 44 <&tegra_car TEGRA210_CLK_AFI>, 45 <&tegra_car TEGRA210_CLK_PLL_E>, 46 <&tegra_car TEGRA210_CLK_CML0>; 47 clock-names = "pex", "afi", "pll_e", "cml"; 48 resets = <&tegra_car 70>, 49 <&tegra_car 72>, 50 <&tegra_car 74>; 51 reset-names = "pex", "afi", "pcie_x"; 52 53 pinctrl-names = "default", "idle"; 54 pinctrl-0 = <&pex_dpd_disable>; 55 pinctrl-1 = <&pex_dpd_enable>; 56 57 status = "disabled"; 58 59 pci@1,0 { 60 device_type = "pci"; 61 assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>; 62 reg = <0x000800 0 0 0 0>; 63 bus-range = <0x00 0xff>; 64 status = "disabled"; 65 66 #address-cells = <3>; 67 #size-cells = <2>; 68 ranges; 69 70 nvidia,num-lanes = <4>; 71 }; 72 73 pci@2,0 { 74 device_type = "pci"; 75 assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>; 76 reg = <0x001000 0 0 0 0>; 77 bus-range = <0x00 0xff>; 78 status = "disabled"; 79 80 #address-cells = <3>; 81 #size-cells = <2>; 82 ranges; 83 84 nvidia,num-lanes = <1>; 85 }; 86 }; 87 88 host1x@50000000 { 89 compatible = "nvidia,tegra210-host1x"; 90 reg = <0x0 0x50000000 0x0 0x00034000>; 91 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */ 92 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */ 93 interrupt-names = "syncpt", "host1x"; 94 clocks = <&tegra_car TEGRA210_CLK_HOST1X>; 95 clock-names = "host1x"; 96 resets = <&tegra_car 28>; 97 reset-names = "host1x"; 98 99 #address-cells = <2>; 100 #size-cells = <2>; 101 102 ranges = <0x0 0x54000000 0x0 0x54000000 0x0 0x01000000>; 103 104 iommus = <&mc TEGRA_SWGROUP_HC>; 105 106 dpaux1: dpaux@54040000 { 107 compatible = "nvidia,tegra210-dpaux"; 108 reg = <0x0 0x54040000 0x0 0x00040000>; 109 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 110 clocks = <&tegra_car TEGRA210_CLK_DPAUX1>, 111 <&tegra_car TEGRA210_CLK_PLL_DP>; 112 clock-names = "dpaux", "parent"; 113 resets = <&tegra_car 207>; 114 reset-names = "dpaux"; 115 power-domains = <&pd_sor>; 116 status = "disabled"; 117 118 state_dpaux1_aux: pinmux-aux { 119 groups = "dpaux-io"; 120 function = "aux"; 121 }; 122 123 state_dpaux1_i2c: pinmux-i2c { 124 groups = "dpaux-io"; 125 function = "i2c"; 126 }; 127 128 state_dpaux1_off: pinmux-off { 129 groups = "dpaux-io"; 130 function = "off"; 131 }; 132 133 i2c-bus { 134 #address-cells = <1>; 135 #size-cells = <0>; 136 }; 137 }; 138 139 vi@54080000 { 140 compatible = "nvidia,tegra210-vi"; 141 reg = <0x0 0x54080000 0x0 0x700>; 142 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 143 status = "disabled"; 144 assigned-clocks = <&tegra_car TEGRA210_CLK_VI>; 145 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; 146 147 clocks = <&tegra_car TEGRA210_CLK_VI>; 148 power-domains = <&pd_venc>; 149 150 #address-cells = <1>; 151 #size-cells = <1>; 152 153 ranges = <0x0 0x0 0x54080000 0x2000>; 154 155 csi@838 { 156 compatible = "nvidia,tegra210-csi"; 157 reg = <0x838 0x1300>; 158 status = "disabled"; 159 assigned-clocks = <&tegra_car TEGRA210_CLK_CILAB>, 160 <&tegra_car TEGRA210_CLK_CILCD>, 161 <&tegra_car TEGRA210_CLK_CILE>, 162 <&tegra_car TEGRA210_CLK_CSI_TPG>; 163 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_P>, 164 <&tegra_car TEGRA210_CLK_PLL_P>, 165 <&tegra_car TEGRA210_CLK_PLL_P>; 166 assigned-clock-rates = <102000000>, 167 <102000000>, 168 <102000000>, 169 <972000000>; 170 171 clocks = <&tegra_car TEGRA210_CLK_CSI>, 172 <&tegra_car TEGRA210_CLK_CILAB>, 173 <&tegra_car TEGRA210_CLK_CILCD>, 174 <&tegra_car TEGRA210_CLK_CILE>, 175 <&tegra_car TEGRA210_CLK_CSI_TPG>; 176 clock-names = "csi", "cilab", "cilcd", "cile", "csi_tpg"; 177 power-domains = <&pd_sor>; 178 }; 179 }; 180 181 tsec@54100000 { 182 compatible = "nvidia,tegra210-tsec"; 183 reg = <0x0 0x54100000 0x0 0x00040000>; 184 }; 185 186 dc@54200000 { 187 compatible = "nvidia,tegra210-dc"; 188 reg = <0x0 0x54200000 0x0 0x00040000>; 189 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 190 clocks = <&tegra_car TEGRA210_CLK_DISP1>; 191 clock-names = "dc"; 192 resets = <&tegra_car 27>; 193 reset-names = "dc"; 194 195 iommus = <&mc TEGRA_SWGROUP_DC>; 196 197 nvidia,head = <0>; 198 }; 199 200 dc@54240000 { 201 compatible = "nvidia,tegra210-dc"; 202 reg = <0x0 0x54240000 0x0 0x00040000>; 203 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 204 clocks = <&tegra_car TEGRA210_CLK_DISP2>; 205 clock-names = "dc"; 206 resets = <&tegra_car 26>; 207 reset-names = "dc"; 208 209 iommus = <&mc TEGRA_SWGROUP_DCB>; 210 211 nvidia,head = <1>; 212 }; 213 214 dsi@54300000 { 215 compatible = "nvidia,tegra210-dsi"; 216 reg = <0x0 0x54300000 0x0 0x00040000>; 217 clocks = <&tegra_car TEGRA210_CLK_DSIA>, 218 <&tegra_car TEGRA210_CLK_DSIALP>, 219 <&tegra_car TEGRA210_CLK_PLL_D_OUT0>; 220 clock-names = "dsi", "lp", "parent"; 221 resets = <&tegra_car 48>; 222 reset-names = "dsi"; 223 power-domains = <&pd_sor>; 224 nvidia,mipi-calibrate = <&mipi 0x0c0>; /* DSIA & DSIB pads */ 225 226 status = "disabled"; 227 228 #address-cells = <1>; 229 #size-cells = <0>; 230 }; 231 232 vic@54340000 { 233 compatible = "nvidia,tegra210-vic"; 234 reg = <0x0 0x54340000 0x0 0x00040000>; 235 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 236 clocks = <&tegra_car TEGRA210_CLK_VIC03>; 237 clock-names = "vic"; 238 resets = <&tegra_car 178>; 239 reset-names = "vic"; 240 241 iommus = <&mc TEGRA_SWGROUP_VIC>; 242 power-domains = <&pd_vic>; 243 }; 244 245 nvjpg@54380000 { 246 compatible = "nvidia,tegra210-nvjpg"; 247 reg = <0x0 0x54380000 0x0 0x00040000>; 248 status = "disabled"; 249 }; 250 251 dsi@54400000 { 252 compatible = "nvidia,tegra210-dsi"; 253 reg = <0x0 0x54400000 0x0 0x00040000>; 254 clocks = <&tegra_car TEGRA210_CLK_DSIB>, 255 <&tegra_car TEGRA210_CLK_DSIBLP>, 256 <&tegra_car TEGRA210_CLK_PLL_D_OUT0>; 257 clock-names = "dsi", "lp", "parent"; 258 resets = <&tegra_car 82>; 259 reset-names = "dsi"; 260 power-domains = <&pd_sor>; 261 nvidia,mipi-calibrate = <&mipi 0x300>; /* DSIC & DSID pads */ 262 263 status = "disabled"; 264 265 #address-cells = <1>; 266 #size-cells = <0>; 267 }; 268 269 nvdec@54480000 { 270 compatible = "nvidia,tegra210-nvdec"; 271 reg = <0x0 0x54480000 0x0 0x00040000>; 272 status = "disabled"; 273 }; 274 275 nvenc@544c0000 { 276 compatible = "nvidia,tegra210-nvenc"; 277 reg = <0x0 0x544c0000 0x0 0x00040000>; 278 status = "disabled"; 279 }; 280 281 tsec@54500000 { 282 compatible = "nvidia,tegra210-tsec"; 283 reg = <0x0 0x54500000 0x0 0x00040000>; 284 status = "disabled"; 285 }; 286 287 sor@54540000 { 288 compatible = "nvidia,tegra210-sor"; 289 reg = <0x0 0x54540000 0x0 0x00040000>; 290 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 291 clocks = <&tegra_car TEGRA210_CLK_SOR0>, 292 <&tegra_car TEGRA210_CLK_SOR0_OUT>, 293 <&tegra_car TEGRA210_CLK_PLL_D_OUT0>, 294 <&tegra_car TEGRA210_CLK_PLL_DP>, 295 <&tegra_car TEGRA210_CLK_SOR_SAFE>; 296 clock-names = "sor", "out", "parent", "dp", "safe"; 297 resets = <&tegra_car 182>; 298 reset-names = "sor"; 299 pinctrl-0 = <&state_dpaux_aux>; 300 pinctrl-1 = <&state_dpaux_i2c>; 301 pinctrl-2 = <&state_dpaux_off>; 302 pinctrl-names = "aux", "i2c", "off"; 303 power-domains = <&pd_sor>; 304 status = "disabled"; 305 }; 306 307 sor@54580000 { 308 compatible = "nvidia,tegra210-sor1"; 309 reg = <0x0 0x54580000 0x0 0x00040000>; 310 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 311 clocks = <&tegra_car TEGRA210_CLK_SOR1>, 312 <&tegra_car TEGRA210_CLK_SOR1_OUT>, 313 <&tegra_car TEGRA210_CLK_PLL_D2_OUT0>, 314 <&tegra_car TEGRA210_CLK_PLL_DP>, 315 <&tegra_car TEGRA210_CLK_SOR_SAFE>; 316 clock-names = "sor", "out", "parent", "dp", "safe"; 317 resets = <&tegra_car 183>; 318 reset-names = "sor"; 319 pinctrl-0 = <&state_dpaux1_aux>; 320 pinctrl-1 = <&state_dpaux1_i2c>; 321 pinctrl-2 = <&state_dpaux1_off>; 322 pinctrl-names = "aux", "i2c", "off"; 323 power-domains = <&pd_sor>; 324 status = "disabled"; 325 }; 326 327 dpaux: dpaux@545c0000 { 328 compatible = "nvidia,tegra210-dpaux"; 329 reg = <0x0 0x545c0000 0x0 0x00040000>; 330 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 331 clocks = <&tegra_car TEGRA210_CLK_DPAUX>, 332 <&tegra_car TEGRA210_CLK_PLL_DP>; 333 clock-names = "dpaux", "parent"; 334 resets = <&tegra_car 181>; 335 reset-names = "dpaux"; 336 power-domains = <&pd_sor>; 337 status = "disabled"; 338 339 state_dpaux_aux: pinmux-aux { 340 groups = "dpaux-io"; 341 function = "aux"; 342 }; 343 344 state_dpaux_i2c: pinmux-i2c { 345 groups = "dpaux-io"; 346 function = "i2c"; 347 }; 348 349 state_dpaux_off: pinmux-off { 350 groups = "dpaux-io"; 351 function = "off"; 352 }; 353 354 i2c-bus { 355 #address-cells = <1>; 356 #size-cells = <0>; 357 }; 358 }; 359 360 isp@54600000 { 361 compatible = "nvidia,tegra210-isp"; 362 reg = <0x0 0x54600000 0x0 0x00040000>; 363 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 364 clocks = <&tegra_car TEGRA210_CLK_ISPA>; 365 resets = <&tegra_car 23>; 366 reset-names = "isp"; 367 status = "disabled"; 368 }; 369 370 isp@54680000 { 371 compatible = "nvidia,tegra210-isp"; 372 reg = <0x0 0x54680000 0x0 0x00040000>; 373 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 374 clocks = <&tegra_car TEGRA210_CLK_ISPB>; 375 resets = <&tegra_car 3>; 376 reset-names = "isp"; 377 status = "disabled"; 378 }; 379 380 i2c@546c0000 { 381 compatible = "nvidia,tegra210-i2c-vi"; 382 reg = <0x0 0x546c0000 0x0 0x00040000>; 383 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 384 clocks = <&tegra_car TEGRA210_CLK_VI_I2C>, 385 <&tegra_car TEGRA210_CLK_I2CSLOW>; 386 clock-names = "div-clk", "slow"; 387 resets = <&tegra_car 208>; 388 reset-names = "i2c"; 389 power-domains = <&pd_venc>; 390 status = "disabled"; 391 }; 392 }; 393 394 gic: interrupt-controller@50041000 { 395 compatible = "arm,gic-400"; 396 #interrupt-cells = <3>; 397 interrupt-controller; 398 reg = <0x0 0x50041000 0x0 0x1000>, 399 <0x0 0x50042000 0x0 0x2000>, 400 <0x0 0x50044000 0x0 0x2000>, 401 <0x0 0x50046000 0x0 0x2000>; 402 interrupts = <GIC_PPI 9 403 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 404 interrupt-parent = <&gic>; 405 }; 406 407 gpu@57000000 { 408 compatible = "nvidia,gm20b"; 409 reg = <0x0 0x57000000 0x0 0x01000000>, 410 <0x0 0x58000000 0x0 0x01000000>; 411 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 412 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 413 interrupt-names = "stall", "nonstall"; 414 clocks = <&tegra_car TEGRA210_CLK_GPU>, 415 <&tegra_car TEGRA210_CLK_PLL_P_OUT5>, 416 <&tegra_car TEGRA210_CLK_PLL_G_REF>; 417 clock-names = "gpu", "pwr", "ref"; 418 resets = <&tegra_car 184>; 419 reset-names = "gpu"; 420 421 iommus = <&mc TEGRA_SWGROUP_GPU>; 422 423 status = "disabled"; 424 }; 425 426 lic: interrupt-controller@60004000 { 427 compatible = "nvidia,tegra210-ictlr"; 428 reg = <0x0 0x60004000 0x0 0x40>, /* primary controller */ 429 <0x0 0x60004100 0x0 0x40>, /* secondary controller */ 430 <0x0 0x60004200 0x0 0x40>, /* tertiary controller */ 431 <0x0 0x60004300 0x0 0x40>, /* quaternary controller */ 432 <0x0 0x60004400 0x0 0x40>, /* quinary controller */ 433 <0x0 0x60004500 0x0 0x40>; /* senary controller */ 434 interrupt-controller; 435 #interrupt-cells = <3>; 436 interrupt-parent = <&gic>; 437 }; 438 439 timer@60005000 { 440 compatible = "nvidia,tegra210-timer"; 441 reg = <0x0 0x60005000 0x0 0x400>; 442 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, 443 <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 444 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 445 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 446 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 447 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 448 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 449 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 450 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 451 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 452 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 453 <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>, 454 <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>, 455 <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; 456 clocks = <&tegra_car TEGRA210_CLK_TIMER>; 457 clock-names = "timer"; 458 }; 459 460 tegra_car: clock@60006000 { 461 compatible = "nvidia,tegra210-car"; 462 reg = <0x0 0x60006000 0x0 0x1000>; 463 #clock-cells = <1>; 464 #reset-cells = <1>; 465 }; 466 467 flow-controller@60007000 { 468 compatible = "nvidia,tegra210-flowctrl"; 469 reg = <0x0 0x60007000 0x0 0x1000>; 470 }; 471 472 gpio: gpio@6000d000 { 473 compatible = "nvidia,tegra210-gpio", "nvidia,tegra30-gpio"; 474 reg = <0x0 0x6000d000 0x0 0x1000>; 475 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 476 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 477 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 478 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 479 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 480 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 481 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 482 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 483 #gpio-cells = <2>; 484 gpio-controller; 485 #interrupt-cells = <2>; 486 interrupt-controller; 487 }; 488 489 apbdma: dma@60020000 { 490 compatible = "nvidia,tegra210-apbdma", "nvidia,tegra148-apbdma"; 491 reg = <0x0 0x60020000 0x0 0x1400>; 492 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 493 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 494 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 495 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 496 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 497 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 498 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 499 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 500 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 501 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 502 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 503 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 504 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 505 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 506 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 507 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 508 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 509 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 510 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 511 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 512 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 513 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 514 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 515 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 516 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 517 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 518 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 519 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 520 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 521 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 522 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 523 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 524 clocks = <&tegra_car TEGRA210_CLK_APBDMA>; 525 clock-names = "dma"; 526 resets = <&tegra_car 34>; 527 reset-names = "dma"; 528 #dma-cells = <1>; 529 }; 530 531 apbmisc@70000800 { 532 compatible = "nvidia,tegra210-apbmisc", "nvidia,tegra20-apbmisc"; 533 reg = <0x0 0x70000800 0x0 0x64>, /* Chip revision */ 534 <0x0 0x70000008 0x0 0x04>; /* Strapping options */ 535 }; 536 537 pinmux: pinmux@700008d4 { 538 compatible = "nvidia,tegra210-pinmux"; 539 reg = <0x0 0x700008d4 0x0 0x29c>, /* Pad control registers */ 540 <0x0 0x70003000 0x0 0x294>; /* Mux registers */ 541 sdmmc1_3v3_drv: sdmmc1-3v3-drv { 542 sdmmc1 { 543 nvidia,pins = "drive_sdmmc1"; 544 nvidia,pull-down-strength = <0x8>; 545 nvidia,pull-up-strength = <0x8>; 546 }; 547 }; 548 sdmmc1_1v8_drv: sdmmc1-1v8-drv { 549 sdmmc1 { 550 nvidia,pins = "drive_sdmmc1"; 551 nvidia,pull-down-strength = <0x4>; 552 nvidia,pull-up-strength = <0x3>; 553 }; 554 }; 555 sdmmc2_1v8_drv: sdmmc2-1v8-drv { 556 sdmmc2 { 557 nvidia,pins = "drive_sdmmc2"; 558 nvidia,pull-down-strength = <0x10>; 559 nvidia,pull-up-strength = <0x10>; 560 }; 561 }; 562 sdmmc3_3v3_drv: sdmmc3-3v3-drv { 563 sdmmc3 { 564 nvidia,pins = "drive_sdmmc3"; 565 nvidia,pull-down-strength = <0x8>; 566 nvidia,pull-up-strength = <0x8>; 567 }; 568 }; 569 sdmmc3_1v8_drv: sdmmc3-1v8-drv { 570 sdmmc3 { 571 nvidia,pins = "drive_sdmmc3"; 572 nvidia,pull-down-strength = <0x4>; 573 nvidia,pull-up-strength = <0x3>; 574 }; 575 }; 576 sdmmc4_1v8_drv: sdmmc4-1v8-drv { 577 sdmmc4 { 578 nvidia,pins = "drive_sdmmc4"; 579 nvidia,pull-down-strength = <0x10>; 580 nvidia,pull-up-strength = <0x10>; 581 }; 582 }; 583 }; 584 585 /* 586 * There are two serial driver i.e. 8250 based simple serial 587 * driver and APB DMA based serial driver for higher baudrate 588 * and performance. To enable the 8250 based driver, the compatible 589 * is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable 590 * the APB DMA based serial driver, the compatible is 591 * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart". 592 */ 593 uarta: serial@70006000 { 594 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; 595 reg = <0x0 0x70006000 0x0 0x40>; 596 reg-shift = <2>; 597 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 598 clocks = <&tegra_car TEGRA210_CLK_UARTA>; 599 clock-names = "serial"; 600 resets = <&tegra_car 6>; 601 reset-names = "serial"; 602 dmas = <&apbdma 8>, <&apbdma 8>; 603 dma-names = "rx", "tx"; 604 status = "disabled"; 605 }; 606 607 uartb: serial@70006040 { 608 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; 609 reg = <0x0 0x70006040 0x0 0x40>; 610 reg-shift = <2>; 611 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 612 clocks = <&tegra_car TEGRA210_CLK_UARTB>; 613 clock-names = "serial"; 614 resets = <&tegra_car 7>; 615 reset-names = "serial"; 616 dmas = <&apbdma 9>, <&apbdma 9>; 617 dma-names = "rx", "tx"; 618 status = "disabled"; 619 }; 620 621 uartc: serial@70006200 { 622 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; 623 reg = <0x0 0x70006200 0x0 0x40>; 624 reg-shift = <2>; 625 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 626 clocks = <&tegra_car TEGRA210_CLK_UARTC>; 627 clock-names = "serial"; 628 resets = <&tegra_car 55>; 629 reset-names = "serial"; 630 dmas = <&apbdma 10>, <&apbdma 10>; 631 dma-names = "rx", "tx"; 632 status = "disabled"; 633 }; 634 635 uartd: serial@70006300 { 636 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; 637 reg = <0x0 0x70006300 0x0 0x40>; 638 reg-shift = <2>; 639 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 640 clocks = <&tegra_car TEGRA210_CLK_UARTD>; 641 clock-names = "serial"; 642 resets = <&tegra_car 65>; 643 reset-names = "serial"; 644 dmas = <&apbdma 19>, <&apbdma 19>; 645 dma-names = "rx", "tx"; 646 status = "disabled"; 647 }; 648 649 pwm: pwm@7000a000 { 650 compatible = "nvidia,tegra210-pwm", "nvidia,tegra20-pwm"; 651 reg = <0x0 0x7000a000 0x0 0x100>; 652 #pwm-cells = <2>; 653 clocks = <&tegra_car TEGRA210_CLK_PWM>; 654 clock-names = "pwm"; 655 resets = <&tegra_car 17>; 656 reset-names = "pwm"; 657 status = "disabled"; 658 }; 659 660 i2c@7000c000 { 661 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; 662 reg = <0x0 0x7000c000 0x0 0x100>; 663 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 664 #address-cells = <1>; 665 #size-cells = <0>; 666 clocks = <&tegra_car TEGRA210_CLK_I2C1>; 667 clock-names = "div-clk"; 668 resets = <&tegra_car 12>; 669 reset-names = "i2c"; 670 dmas = <&apbdma 21>, <&apbdma 21>; 671 dma-names = "rx", "tx"; 672 status = "disabled"; 673 }; 674 675 i2c@7000c400 { 676 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; 677 reg = <0x0 0x7000c400 0x0 0x100>; 678 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 679 #address-cells = <1>; 680 #size-cells = <0>; 681 clocks = <&tegra_car TEGRA210_CLK_I2C2>; 682 clock-names = "div-clk"; 683 resets = <&tegra_car 54>; 684 reset-names = "i2c"; 685 dmas = <&apbdma 22>, <&apbdma 22>; 686 dma-names = "rx", "tx"; 687 status = "disabled"; 688 }; 689 690 i2c@7000c500 { 691 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; 692 reg = <0x0 0x7000c500 0x0 0x100>; 693 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 694 #address-cells = <1>; 695 #size-cells = <0>; 696 clocks = <&tegra_car TEGRA210_CLK_I2C3>; 697 clock-names = "div-clk"; 698 resets = <&tegra_car 67>; 699 reset-names = "i2c"; 700 dmas = <&apbdma 23>, <&apbdma 23>; 701 dma-names = "rx", "tx"; 702 status = "disabled"; 703 }; 704 705 i2c@7000c700 { 706 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; 707 reg = <0x0 0x7000c700 0x0 0x100>; 708 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 709 #address-cells = <1>; 710 #size-cells = <0>; 711 clocks = <&tegra_car TEGRA210_CLK_I2C4>; 712 clock-names = "div-clk"; 713 resets = <&tegra_car 103>; 714 reset-names = "i2c"; 715 dmas = <&apbdma 26>, <&apbdma 26>; 716 dma-names = "rx", "tx"; 717 pinctrl-0 = <&state_dpaux1_i2c>; 718 pinctrl-1 = <&state_dpaux1_off>; 719 pinctrl-names = "default", "idle"; 720 status = "disabled"; 721 }; 722 723 i2c@7000d000 { 724 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; 725 reg = <0x0 0x7000d000 0x0 0x100>; 726 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 727 #address-cells = <1>; 728 #size-cells = <0>; 729 clocks = <&tegra_car TEGRA210_CLK_I2C5>; 730 clock-names = "div-clk"; 731 resets = <&tegra_car 47>; 732 reset-names = "i2c"; 733 dmas = <&apbdma 24>, <&apbdma 24>; 734 dma-names = "rx", "tx"; 735 status = "disabled"; 736 }; 737 738 i2c@7000d100 { 739 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; 740 reg = <0x0 0x7000d100 0x0 0x100>; 741 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 742 #address-cells = <1>; 743 #size-cells = <0>; 744 clocks = <&tegra_car TEGRA210_CLK_I2C6>; 745 clock-names = "div-clk"; 746 resets = <&tegra_car 166>; 747 reset-names = "i2c"; 748 dmas = <&apbdma 30>, <&apbdma 30>; 749 dma-names = "rx", "tx"; 750 pinctrl-0 = <&state_dpaux_i2c>; 751 pinctrl-1 = <&state_dpaux_off>; 752 pinctrl-names = "default", "idle"; 753 status = "disabled"; 754 }; 755 756 spi@7000d400 { 757 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 758 reg = <0x0 0x7000d400 0x0 0x200>; 759 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 760 #address-cells = <1>; 761 #size-cells = <0>; 762 clocks = <&tegra_car TEGRA210_CLK_SBC1>; 763 clock-names = "spi"; 764 resets = <&tegra_car 41>; 765 reset-names = "spi"; 766 dmas = <&apbdma 15>, <&apbdma 15>; 767 dma-names = "rx", "tx"; 768 status = "disabled"; 769 }; 770 771 spi@7000d600 { 772 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 773 reg = <0x0 0x7000d600 0x0 0x200>; 774 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 775 #address-cells = <1>; 776 #size-cells = <0>; 777 clocks = <&tegra_car TEGRA210_CLK_SBC2>; 778 clock-names = "spi"; 779 resets = <&tegra_car 44>; 780 reset-names = "spi"; 781 dmas = <&apbdma 16>, <&apbdma 16>; 782 dma-names = "rx", "tx"; 783 status = "disabled"; 784 }; 785 786 spi@7000d800 { 787 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 788 reg = <0x0 0x7000d800 0x0 0x200>; 789 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 790 #address-cells = <1>; 791 #size-cells = <0>; 792 clocks = <&tegra_car TEGRA210_CLK_SBC3>; 793 clock-names = "spi"; 794 resets = <&tegra_car 46>; 795 reset-names = "spi"; 796 dmas = <&apbdma 17>, <&apbdma 17>; 797 dma-names = "rx", "tx"; 798 status = "disabled"; 799 }; 800 801 spi@7000da00 { 802 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 803 reg = <0x0 0x7000da00 0x0 0x200>; 804 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 805 #address-cells = <1>; 806 #size-cells = <0>; 807 clocks = <&tegra_car TEGRA210_CLK_SBC4>; 808 clock-names = "spi"; 809 resets = <&tegra_car 68>; 810 reset-names = "spi"; 811 dmas = <&apbdma 18>, <&apbdma 18>; 812 dma-names = "rx", "tx"; 813 status = "disabled"; 814 }; 815 816 rtc@7000e000 { 817 compatible = "nvidia,tegra210-rtc", "nvidia,tegra20-rtc"; 818 reg = <0x0 0x7000e000 0x0 0x100>; 819 interrupts = <16 IRQ_TYPE_LEVEL_HIGH>; 820 interrupt-parent = <&tegra_pmc>; 821 clocks = <&tegra_car TEGRA210_CLK_RTC>; 822 clock-names = "rtc"; 823 }; 824 825 tegra_pmc: pmc@7000e400 { 826 compatible = "nvidia,tegra210-pmc"; 827 reg = <0x0 0x7000e400 0x0 0x400>; 828 clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>; 829 clock-names = "pclk", "clk32k_in"; 830 #clock-cells = <1>; 831 #interrupt-cells = <2>; 832 interrupt-controller; 833 834 powergates { 835 pd_audio: aud { 836 clocks = <&tegra_car TEGRA210_CLK_APE>, 837 <&tegra_car TEGRA210_CLK_APB2APE>; 838 resets = <&tegra_car 198>; 839 #power-domain-cells = <0>; 840 }; 841 842 pd_sor: sor { 843 clocks = <&tegra_car TEGRA210_CLK_SOR0>, 844 <&tegra_car TEGRA210_CLK_SOR1>, 845 <&tegra_car TEGRA210_CLK_CILAB>, 846 <&tegra_car TEGRA210_CLK_CILCD>, 847 <&tegra_car TEGRA210_CLK_CILE>, 848 <&tegra_car TEGRA210_CLK_DSIA>, 849 <&tegra_car TEGRA210_CLK_DSIB>, 850 <&tegra_car TEGRA210_CLK_DPAUX>, 851 <&tegra_car TEGRA210_CLK_DPAUX1>, 852 <&tegra_car TEGRA210_CLK_MIPI_CAL>; 853 resets = <&tegra_car TEGRA210_CLK_SOR0>, 854 <&tegra_car TEGRA210_CLK_SOR1>, 855 <&tegra_car TEGRA210_CLK_DSIA>, 856 <&tegra_car TEGRA210_CLK_DSIB>, 857 <&tegra_car TEGRA210_CLK_DPAUX>, 858 <&tegra_car TEGRA210_CLK_DPAUX1>, 859 <&tegra_car TEGRA210_CLK_MIPI_CAL>; 860 #power-domain-cells = <0>; 861 }; 862 863 pd_xusbss: xusba { 864 clocks = <&tegra_car TEGRA210_CLK_XUSB_SS>; 865 resets = <&tegra_car TEGRA210_CLK_XUSB_SS>; 866 #power-domain-cells = <0>; 867 }; 868 869 pd_xusbdev: xusbb { 870 clocks = <&tegra_car TEGRA210_CLK_XUSB_DEV>; 871 resets = <&tegra_car 95>; 872 #power-domain-cells = <0>; 873 }; 874 875 pd_xusbhost: xusbc { 876 clocks = <&tegra_car TEGRA210_CLK_XUSB_HOST>; 877 resets = <&tegra_car TEGRA210_CLK_XUSB_HOST>; 878 #power-domain-cells = <0>; 879 }; 880 881 pd_vic: vic { 882 clocks = <&tegra_car TEGRA210_CLK_VIC03>; 883 clock-names = "vic"; 884 resets = <&tegra_car 178>; 885 reset-names = "vic"; 886 #power-domain-cells = <0>; 887 }; 888 889 pd_venc: venc { 890 clocks = <&tegra_car TEGRA210_CLK_VI>, 891 <&tegra_car TEGRA210_CLK_CSI>; 892 resets = <&mc TEGRA210_MC_RESET_VI>, 893 <&tegra_car 20>, 894 <&tegra_car 52>; 895 #power-domain-cells = <0>; 896 }; 897 }; 898 899 sdmmc1_3v3: sdmmc1-3v3 { 900 pins = "sdmmc1"; 901 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 902 }; 903 904 sdmmc1_1v8: sdmmc1-1v8 { 905 pins = "sdmmc1"; 906 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 907 }; 908 909 sdmmc3_3v3: sdmmc3-3v3 { 910 pins = "sdmmc3"; 911 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 912 }; 913 914 sdmmc3_1v8: sdmmc3-1v8 { 915 pins = "sdmmc3"; 916 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 917 }; 918 919 pex_dpd_disable: pex_en { 920 pex-dpd-disable { 921 pins = "pex-bias", "pex-clk1", "pex-clk2"; 922 low-power-disable; 923 }; 924 }; 925 926 pex_dpd_enable: pex_dis { 927 pex-dpd-enable { 928 pins = "pex-bias", "pex-clk1", "pex-clk2"; 929 low-power-enable; 930 }; 931 }; 932 }; 933 934 fuse@7000f800 { 935 compatible = "nvidia,tegra210-efuse"; 936 reg = <0x0 0x7000f800 0x0 0x400>; 937 clocks = <&tegra_car TEGRA210_CLK_FUSE>; 938 clock-names = "fuse"; 939 resets = <&tegra_car 39>; 940 reset-names = "fuse"; 941 }; 942 943 mc: memory-controller@70019000 { 944 compatible = "nvidia,tegra210-mc"; 945 reg = <0x0 0x70019000 0x0 0x1000>; 946 clocks = <&tegra_car TEGRA210_CLK_MC>; 947 clock-names = "mc"; 948 949 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 950 951 #iommu-cells = <1>; 952 #reset-cells = <1>; 953 }; 954 955 emc: external-memory-controller@7001b000 { 956 compatible = "nvidia,tegra210-emc"; 957 reg = <0x0 0x7001b000 0x0 0x1000>, 958 <0x0 0x7001e000 0x0 0x1000>, 959 <0x0 0x7001f000 0x0 0x1000>; 960 clocks = <&tegra_car TEGRA210_CLK_EMC>; 961 clock-names = "emc"; 962 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 963 nvidia,memory-controller = <&mc>; 964 #cooling-cells = <2>; 965 }; 966 967 sata@70020000 { 968 compatible = "nvidia,tegra210-ahci"; 969 reg = <0x0 0x70027000 0x0 0x2000>, /* AHCI */ 970 <0x0 0x70020000 0x0 0x7000>, /* SATA */ 971 <0x0 0x70001100 0x0 0x1000>; /* SATA AUX */ 972 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 973 clocks = <&tegra_car TEGRA210_CLK_SATA>, 974 <&tegra_car TEGRA210_CLK_SATA_OOB>; 975 clock-names = "sata", "sata-oob"; 976 resets = <&tegra_car 124>, 977 <&tegra_car 123>, 978 <&tegra_car 129>; 979 reset-names = "sata", "sata-oob", "sata-cold"; 980 status = "disabled"; 981 }; 982 983 hda@70030000 { 984 compatible = "nvidia,tegra210-hda", "nvidia,tegra30-hda"; 985 reg = <0x0 0x70030000 0x0 0x10000>; 986 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 987 clocks = <&tegra_car TEGRA210_CLK_HDA>, 988 <&tegra_car TEGRA210_CLK_HDA2HDMI>, 989 <&tegra_car TEGRA210_CLK_HDA2CODEC_2X>; 990 clock-names = "hda", "hda2hdmi", "hda2codec_2x"; 991 resets = <&tegra_car 125>, /* hda */ 992 <&tegra_car 128>, /* hda2hdmi */ 993 <&tegra_car 111>; /* hda2codec_2x */ 994 reset-names = "hda", "hda2hdmi", "hda2codec_2x"; 995 status = "disabled"; 996 }; 997 998 usb@70090000 { 999 compatible = "nvidia,tegra210-xusb"; 1000 reg = <0x0 0x70090000 0x0 0x8000>, 1001 <0x0 0x70098000 0x0 0x1000>, 1002 <0x0 0x70099000 0x0 0x1000>; 1003 reg-names = "hcd", "fpci", "ipfs"; 1004 1005 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 1006 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 1007 1008 clocks = <&tegra_car TEGRA210_CLK_XUSB_HOST>, 1009 <&tegra_car TEGRA210_CLK_XUSB_HOST_SRC>, 1010 <&tegra_car TEGRA210_CLK_XUSB_FALCON_SRC>, 1011 <&tegra_car TEGRA210_CLK_XUSB_SS>, 1012 <&tegra_car TEGRA210_CLK_XUSB_SS_SRC>, 1013 <&tegra_car TEGRA210_CLK_XUSB_SS_DIV2>, 1014 <&tegra_car TEGRA210_CLK_XUSB_HS_SRC>, 1015 <&tegra_car TEGRA210_CLK_XUSB_FS_SRC>, 1016 <&tegra_car TEGRA210_CLK_PLL_U_480M>, 1017 <&tegra_car TEGRA210_CLK_CLK_M>, 1018 <&tegra_car TEGRA210_CLK_PLL_E>; 1019 clock-names = "xusb_host", "xusb_host_src", 1020 "xusb_falcon_src", "xusb_ss", 1021 "xusb_ss_src", "xusb_ss_div2", 1022 "xusb_hs_src", "xusb_fs_src", 1023 "pll_u_480m", "clk_m", "pll_e"; 1024 resets = <&tegra_car 89>, <&tegra_car 156>, 1025 <&tegra_car 143>; 1026 reset-names = "xusb_host", "xusb_ss", "xusb_src"; 1027 power-domains = <&pd_xusbhost>, <&pd_xusbss>; 1028 power-domain-names = "xusb_host", "xusb_ss"; 1029 1030 nvidia,xusb-padctl = <&padctl>; 1031 1032 status = "disabled"; 1033 }; 1034 1035 padctl: padctl@7009f000 { 1036 compatible = "nvidia,tegra210-xusb-padctl"; 1037 reg = <0x0 0x7009f000 0x0 0x1000>; 1038 resets = <&tegra_car 142>; 1039 reset-names = "padctl"; 1040 1041 status = "disabled"; 1042 1043 pads { 1044 usb2 { 1045 clocks = <&tegra_car TEGRA210_CLK_USB2_TRK>; 1046 clock-names = "trk"; 1047 status = "disabled"; 1048 1049 lanes { 1050 usb2-0 { 1051 status = "disabled"; 1052 #phy-cells = <0>; 1053 }; 1054 1055 usb2-1 { 1056 status = "disabled"; 1057 #phy-cells = <0>; 1058 }; 1059 1060 usb2-2 { 1061 status = "disabled"; 1062 #phy-cells = <0>; 1063 }; 1064 1065 usb2-3 { 1066 status = "disabled"; 1067 #phy-cells = <0>; 1068 }; 1069 }; 1070 }; 1071 1072 hsic { 1073 clocks = <&tegra_car TEGRA210_CLK_HSIC_TRK>; 1074 clock-names = "trk"; 1075 status = "disabled"; 1076 1077 lanes { 1078 hsic-0 { 1079 status = "disabled"; 1080 #phy-cells = <0>; 1081 }; 1082 1083 hsic-1 { 1084 status = "disabled"; 1085 #phy-cells = <0>; 1086 }; 1087 }; 1088 }; 1089 1090 pcie { 1091 clocks = <&tegra_car TEGRA210_CLK_PLL_E>; 1092 clock-names = "pll"; 1093 resets = <&tegra_car 205>; 1094 reset-names = "phy"; 1095 status = "disabled"; 1096 1097 lanes { 1098 pcie-0 { 1099 status = "disabled"; 1100 #phy-cells = <0>; 1101 }; 1102 1103 pcie-1 { 1104 status = "disabled"; 1105 #phy-cells = <0>; 1106 }; 1107 1108 pcie-2 { 1109 status = "disabled"; 1110 #phy-cells = <0>; 1111 }; 1112 1113 pcie-3 { 1114 status = "disabled"; 1115 #phy-cells = <0>; 1116 }; 1117 1118 pcie-4 { 1119 status = "disabled"; 1120 #phy-cells = <0>; 1121 }; 1122 1123 pcie-5 { 1124 status = "disabled"; 1125 #phy-cells = <0>; 1126 }; 1127 1128 pcie-6 { 1129 status = "disabled"; 1130 #phy-cells = <0>; 1131 }; 1132 }; 1133 }; 1134 1135 sata { 1136 clocks = <&tegra_car TEGRA210_CLK_PLL_E>; 1137 clock-names = "pll"; 1138 resets = <&tegra_car 204>; 1139 reset-names = "phy"; 1140 status = "disabled"; 1141 1142 lanes { 1143 sata-0 { 1144 status = "disabled"; 1145 #phy-cells = <0>; 1146 }; 1147 }; 1148 }; 1149 }; 1150 1151 ports { 1152 usb2-0 { 1153 status = "disabled"; 1154 }; 1155 1156 usb2-1 { 1157 status = "disabled"; 1158 }; 1159 1160 usb2-2 { 1161 status = "disabled"; 1162 }; 1163 1164 usb2-3 { 1165 status = "disabled"; 1166 }; 1167 1168 hsic-0 { 1169 status = "disabled"; 1170 }; 1171 1172 usb3-0 { 1173 status = "disabled"; 1174 }; 1175 1176 usb3-1 { 1177 status = "disabled"; 1178 }; 1179 1180 usb3-2 { 1181 status = "disabled"; 1182 }; 1183 1184 usb3-3 { 1185 status = "disabled"; 1186 }; 1187 }; 1188 }; 1189 1190 mmc@700b0000 { 1191 compatible = "nvidia,tegra210-sdhci"; 1192 reg = <0x0 0x700b0000 0x0 0x200>; 1193 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1194 clocks = <&tegra_car TEGRA210_CLK_SDMMC1>; 1195 clock-names = "sdhci"; 1196 resets = <&tegra_car 14>; 1197 reset-names = "sdhci"; 1198 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8", 1199 "sdmmc-3v3-drv", "sdmmc-1v8-drv"; 1200 pinctrl-0 = <&sdmmc1_3v3>; 1201 pinctrl-1 = <&sdmmc1_1v8>; 1202 pinctrl-2 = <&sdmmc1_3v3_drv>; 1203 pinctrl-3 = <&sdmmc1_1v8_drv>; 1204 nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>; 1205 nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>; 1206 nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>; 1207 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7b>; 1208 nvidia,default-tap = <0x2>; 1209 nvidia,default-trim = <0x4>; 1210 assigned-clocks = <&tegra_car TEGRA210_CLK_SDMMC4>, 1211 <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>, 1212 <&tegra_car TEGRA210_CLK_PLL_C4>; 1213 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; 1214 assigned-clock-rates = <200000000>, <1000000000>, <1000000000>; 1215 status = "disabled"; 1216 }; 1217 1218 mmc@700b0200 { 1219 compatible = "nvidia,tegra210-sdhci"; 1220 reg = <0x0 0x700b0200 0x0 0x200>; 1221 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 1222 clocks = <&tegra_car TEGRA210_CLK_SDMMC2>; 1223 clock-names = "sdhci"; 1224 resets = <&tegra_car 9>; 1225 reset-names = "sdhci"; 1226 pinctrl-names = "sdmmc-1v8-drv"; 1227 pinctrl-0 = <&sdmmc2_1v8_drv>; 1228 nvidia,pad-autocal-pull-up-offset-1v8 = <0x05>; 1229 nvidia,pad-autocal-pull-down-offset-1v8 = <0x05>; 1230 nvidia,default-tap = <0x8>; 1231 nvidia,default-trim = <0x0>; 1232 status = "disabled"; 1233 }; 1234 1235 mmc@700b0400 { 1236 compatible = "nvidia,tegra210-sdhci"; 1237 reg = <0x0 0x700b0400 0x0 0x200>; 1238 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 1239 clocks = <&tegra_car TEGRA210_CLK_SDMMC3>; 1240 clock-names = "sdhci"; 1241 resets = <&tegra_car 69>; 1242 reset-names = "sdhci"; 1243 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8", 1244 "sdmmc-3v3-drv", "sdmmc-1v8-drv"; 1245 pinctrl-0 = <&sdmmc3_3v3>; 1246 pinctrl-1 = <&sdmmc3_1v8>; 1247 pinctrl-2 = <&sdmmc3_3v3_drv>; 1248 pinctrl-3 = <&sdmmc3_1v8_drv>; 1249 nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>; 1250 nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>; 1251 nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>; 1252 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7b>; 1253 nvidia,default-tap = <0x3>; 1254 nvidia,default-trim = <0x3>; 1255 status = "disabled"; 1256 }; 1257 1258 mmc@700b0600 { 1259 compatible = "nvidia,tegra210-sdhci"; 1260 reg = <0x0 0x700b0600 0x0 0x200>; 1261 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 1262 clocks = <&tegra_car TEGRA210_CLK_SDMMC4>; 1263 clock-names = "sdhci"; 1264 resets = <&tegra_car 15>; 1265 reset-names = "sdhci"; 1266 pinctrl-names = "sdmmc-3v3-drv", "sdmmc-1v8-drv"; 1267 pinctrl-0 = <&sdmmc4_1v8_drv>; 1268 pinctrl-1 = <&sdmmc4_1v8_drv>; 1269 nvidia,pad-autocal-pull-up-offset-1v8 = <0x05>; 1270 nvidia,pad-autocal-pull-down-offset-1v8 = <0x05>; 1271 nvidia,default-tap = <0x8>; 1272 nvidia,default-trim = <0x0>; 1273 assigned-clocks = <&tegra_car TEGRA210_CLK_SDMMC4>, 1274 <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; 1275 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; 1276 nvidia,dqs-trim = <40>; 1277 mmc-hs400-1_8v; 1278 status = "disabled"; 1279 }; 1280 1281 usb@700d0000 { 1282 compatible = "nvidia,tegra210-xudc"; 1283 reg = <0x0 0x700d0000 0x0 0x8000>, 1284 <0x0 0x700d8000 0x0 0x1000>, 1285 <0x0 0x700d9000 0x0 0x1000>; 1286 reg-names = "base", "fpci", "ipfs"; 1287 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 1288 clocks = <&tegra_car TEGRA210_CLK_XUSB_DEV>, 1289 <&tegra_car TEGRA210_CLK_XUSB_SS>, 1290 <&tegra_car TEGRA210_CLK_XUSB_SSP_SRC>, 1291 <&tegra_car TEGRA210_CLK_XUSB_FS_SRC>, 1292 <&tegra_car TEGRA210_CLK_XUSB_HS_SRC>; 1293 clock-names = "dev", "ss", "ss_src", "fs_src", "hs_src"; 1294 power-domains = <&pd_xusbdev>, <&pd_xusbss>; 1295 power-domain-names = "dev", "ss"; 1296 nvidia,xusb-padctl = <&padctl>; 1297 status = "disabled"; 1298 }; 1299 1300 mipi: mipi@700e3000 { 1301 compatible = "nvidia,tegra210-mipi"; 1302 reg = <0x0 0x700e3000 0x0 0x100>; 1303 clocks = <&tegra_car TEGRA210_CLK_MIPI_CAL>; 1304 clock-names = "mipi-cal"; 1305 power-domains = <&pd_sor>; 1306 #nvidia,mipi-calibrate-cells = <1>; 1307 }; 1308 1309 dfll: clock@70110000 { 1310 compatible = "nvidia,tegra210-dfll"; 1311 reg = <0 0x70110000 0 0x100>, /* DFLL control */ 1312 <0 0x70110000 0 0x100>, /* I2C output control */ 1313 <0 0x70110100 0 0x100>, /* Integrated I2C controller */ 1314 <0 0x70110200 0 0x100>; /* Look-up table RAM */ 1315 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 1316 clocks = <&tegra_car TEGRA210_CLK_DFLL_SOC>, 1317 <&tegra_car TEGRA210_CLK_DFLL_REF>, 1318 <&tegra_car TEGRA210_CLK_I2C5>; 1319 clock-names = "soc", "ref", "i2c"; 1320 resets = <&tegra_car TEGRA210_RST_DFLL_DVCO>; 1321 reset-names = "dvco"; 1322 #clock-cells = <0>; 1323 clock-output-names = "dfllCPU_out"; 1324 status = "disabled"; 1325 }; 1326 1327 aconnect@702c0000 { 1328 compatible = "nvidia,tegra210-aconnect"; 1329 clocks = <&tegra_car TEGRA210_CLK_APE>, 1330 <&tegra_car TEGRA210_CLK_APB2APE>; 1331 clock-names = "ape", "apb2ape"; 1332 power-domains = <&pd_audio>; 1333 #address-cells = <1>; 1334 #size-cells = <1>; 1335 ranges = <0x702c0000 0x0 0x702c0000 0x00040000>; 1336 status = "disabled"; 1337 1338 adma: dma@702e2000 { 1339 compatible = "nvidia,tegra210-adma"; 1340 reg = <0x702e2000 0x2000>; 1341 interrupt-parent = <&agic>; 1342 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 1343 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 1344 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 1345 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 1346 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 1347 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 1348 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 1349 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 1350 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 1351 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 1352 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 1353 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 1354 <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, 1355 <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, 1356 <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, 1357 <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 1358 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 1359 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 1360 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 1361 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 1362 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 1363 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 1364 #dma-cells = <1>; 1365 clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>; 1366 clock-names = "d_audio"; 1367 status = "disabled"; 1368 }; 1369 1370 agic: interrupt-controller@702f9000 { 1371 compatible = "nvidia,tegra210-agic"; 1372 #interrupt-cells = <3>; 1373 interrupt-controller; 1374 reg = <0x702f9000 0x1000>, 1375 <0x702fa000 0x2000>; 1376 interrupts = <GIC_SPI 102 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 1377 clocks = <&tegra_car TEGRA210_CLK_APE>; 1378 clock-names = "clk"; 1379 status = "disabled"; 1380 }; 1381 }; 1382 1383 spi@70410000 { 1384 compatible = "nvidia,tegra210-qspi"; 1385 reg = <0x0 0x70410000 0x0 0x1000>; 1386 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 1387 #address-cells = <1>; 1388 #size-cells = <0>; 1389 clocks = <&tegra_car TEGRA210_CLK_QSPI>; 1390 clock-names = "qspi"; 1391 resets = <&tegra_car 211>; 1392 reset-names = "qspi"; 1393 dmas = <&apbdma 5>, <&apbdma 5>; 1394 dma-names = "rx", "tx"; 1395 status = "disabled"; 1396 }; 1397 1398 usb@7d000000 { 1399 compatible = "nvidia,tegra210-ehci", "nvidia,tegra30-ehci", "usb-ehci"; 1400 reg = <0x0 0x7d000000 0x0 0x4000>; 1401 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 1402 phy_type = "utmi"; 1403 clocks = <&tegra_car TEGRA210_CLK_USBD>; 1404 clock-names = "usb"; 1405 resets = <&tegra_car 22>; 1406 reset-names = "usb"; 1407 nvidia,phy = <&phy1>; 1408 status = "disabled"; 1409 }; 1410 1411 phy1: usb-phy@7d000000 { 1412 compatible = "nvidia,tegra210-usb-phy", "nvidia,tegra30-usb-phy"; 1413 reg = <0x0 0x7d000000 0x0 0x4000>, 1414 <0x0 0x7d000000 0x0 0x4000>; 1415 phy_type = "utmi"; 1416 clocks = <&tegra_car TEGRA210_CLK_USBD>, 1417 <&tegra_car TEGRA210_CLK_PLL_U>, 1418 <&tegra_car TEGRA210_CLK_USBD>; 1419 clock-names = "reg", "pll_u", "utmi-pads"; 1420 resets = <&tegra_car 22>, <&tegra_car 22>; 1421 reset-names = "usb", "utmi-pads"; 1422 nvidia,hssync-start-delay = <0>; 1423 nvidia,idle-wait-delay = <17>; 1424 nvidia,elastic-limit = <16>; 1425 nvidia,term-range-adj = <6>; 1426 nvidia,xcvr-setup = <9>; 1427 nvidia,xcvr-lsfslew = <0>; 1428 nvidia,xcvr-lsrslew = <3>; 1429 nvidia,hssquelch-level = <2>; 1430 nvidia,hsdiscon-level = <5>; 1431 nvidia,xcvr-hsslew = <12>; 1432 nvidia,has-utmi-pad-registers; 1433 status = "disabled"; 1434 }; 1435 1436 usb@7d004000 { 1437 compatible = "nvidia,tegra210-ehci", "nvidia,tegra30-ehci", "usb-ehci"; 1438 reg = <0x0 0x7d004000 0x0 0x4000>; 1439 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 1440 phy_type = "utmi"; 1441 clocks = <&tegra_car TEGRA210_CLK_USB2>; 1442 clock-names = "usb"; 1443 resets = <&tegra_car 58>; 1444 reset-names = "usb"; 1445 nvidia,phy = <&phy2>; 1446 status = "disabled"; 1447 }; 1448 1449 phy2: usb-phy@7d004000 { 1450 compatible = "nvidia,tegra210-usb-phy", "nvidia,tegra30-usb-phy"; 1451 reg = <0x0 0x7d004000 0x0 0x4000>, 1452 <0x0 0x7d000000 0x0 0x4000>; 1453 phy_type = "utmi"; 1454 clocks = <&tegra_car TEGRA210_CLK_USB2>, 1455 <&tegra_car TEGRA210_CLK_PLL_U>, 1456 <&tegra_car TEGRA210_CLK_USBD>; 1457 clock-names = "reg", "pll_u", "utmi-pads"; 1458 resets = <&tegra_car 58>, <&tegra_car 22>; 1459 reset-names = "usb", "utmi-pads"; 1460 nvidia,hssync-start-delay = <0>; 1461 nvidia,idle-wait-delay = <17>; 1462 nvidia,elastic-limit = <16>; 1463 nvidia,term-range-adj = <6>; 1464 nvidia,xcvr-setup = <9>; 1465 nvidia,xcvr-lsfslew = <0>; 1466 nvidia,xcvr-lsrslew = <3>; 1467 nvidia,hssquelch-level = <2>; 1468 nvidia,hsdiscon-level = <5>; 1469 nvidia,xcvr-hsslew = <12>; 1470 status = "disabled"; 1471 }; 1472 1473 cpus { 1474 #address-cells = <1>; 1475 #size-cells = <0>; 1476 1477 cpu@0 { 1478 device_type = "cpu"; 1479 compatible = "arm,cortex-a57"; 1480 reg = <0>; 1481 clocks = <&tegra_car TEGRA210_CLK_CCLK_G>, 1482 <&tegra_car TEGRA210_CLK_PLL_X>, 1483 <&tegra_car TEGRA210_CLK_PLL_P_OUT4>, 1484 <&dfll>; 1485 clock-names = "cpu_g", "pll_x", "pll_p", "dfll"; 1486 clock-latency = <300000>; 1487 cpu-idle-states = <&CPU_SLEEP>; 1488 next-level-cache = <&L2>; 1489 }; 1490 1491 cpu@1 { 1492 device_type = "cpu"; 1493 compatible = "arm,cortex-a57"; 1494 reg = <1>; 1495 cpu-idle-states = <&CPU_SLEEP>; 1496 next-level-cache = <&L2>; 1497 }; 1498 1499 cpu@2 { 1500 device_type = "cpu"; 1501 compatible = "arm,cortex-a57"; 1502 reg = <2>; 1503 cpu-idle-states = <&CPU_SLEEP>; 1504 next-level-cache = <&L2>; 1505 }; 1506 1507 cpu@3 { 1508 device_type = "cpu"; 1509 compatible = "arm,cortex-a57"; 1510 reg = <3>; 1511 cpu-idle-states = <&CPU_SLEEP>; 1512 next-level-cache = <&L2>; 1513 }; 1514 1515 idle-states { 1516 entry-method = "psci"; 1517 1518 CPU_SLEEP: cpu-sleep { 1519 compatible = "arm,idle-state"; 1520 arm,psci-suspend-param = <0x40000007>; 1521 entry-latency-us = <100>; 1522 exit-latency-us = <30>; 1523 min-residency-us = <1000>; 1524 wakeup-latency-us = <130>; 1525 idle-state-name = "cpu-sleep"; 1526 status = "disabled"; 1527 }; 1528 }; 1529 1530 L2: l2-cache { 1531 compatible = "cache"; 1532 }; 1533 }; 1534 1535 pmu { 1536 compatible = "arm,armv8-pmuv3"; 1537 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 1538 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 1539 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 1540 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; 1541 interrupt-affinity = <&{/cpus/cpu@0} &{/cpus/cpu@1} 1542 &{/cpus/cpu@2} &{/cpus/cpu@3}>; 1543 }; 1544 1545 timer { 1546 compatible = "arm,armv8-timer"; 1547 interrupts = <GIC_PPI 13 1548 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1549 <GIC_PPI 14 1550 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1551 <GIC_PPI 11 1552 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1553 <GIC_PPI 10 1554 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 1555 interrupt-parent = <&gic>; 1556 arm,no-tick-in-suspend; 1557 }; 1558 1559 soctherm: thermal-sensor@700e2000 { 1560 compatible = "nvidia,tegra210-soctherm"; 1561 reg = <0x0 0x700e2000 0x0 0x600>, /* SOC_THERM reg_base */ 1562 <0x0 0x60006000 0x0 0x400>; /* CAR reg_base */ 1563 reg-names = "soctherm-reg", "car-reg"; 1564 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, 1565 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 1566 interrupt-names = "thermal", "edp"; 1567 clocks = <&tegra_car TEGRA210_CLK_TSENSOR>, 1568 <&tegra_car TEGRA210_CLK_SOC_THERM>; 1569 clock-names = "tsensor", "soctherm"; 1570 resets = <&tegra_car 78>; 1571 reset-names = "soctherm"; 1572 #thermal-sensor-cells = <1>; 1573 1574 throttle-cfgs { 1575 throttle_heavy: heavy { 1576 nvidia,priority = <100>; 1577 nvidia,cpu-throt-percent = <85>; 1578 1579 #cooling-cells = <2>; 1580 }; 1581 }; 1582 }; 1583 1584 thermal-zones { 1585 cpu { 1586 polling-delay-passive = <1000>; 1587 polling-delay = <0>; 1588 1589 thermal-sensors = 1590 <&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>; 1591 1592 trips { 1593 cpu-shutdown-trip { 1594 temperature = <102500>; 1595 hysteresis = <0>; 1596 type = "critical"; 1597 }; 1598 1599 cpu_throttle_trip: throttle-trip { 1600 temperature = <98500>; 1601 hysteresis = <1000>; 1602 type = "hot"; 1603 }; 1604 }; 1605 1606 cooling-maps { 1607 map0 { 1608 trip = <&cpu_throttle_trip>; 1609 cooling-device = <&throttle_heavy 1 1>; 1610 }; 1611 }; 1612 }; 1613 1614 mem { 1615 polling-delay-passive = <0>; 1616 polling-delay = <0>; 1617 1618 thermal-sensors = 1619 <&soctherm TEGRA124_SOCTHERM_SENSOR_MEM>; 1620 1621 trips { 1622 dram_nominal: mem-nominal-trip { 1623 temperature = <50000>; 1624 hysteresis = <1000>; 1625 type = "passive"; 1626 }; 1627 1628 dram_throttle: mem-throttle-trip { 1629 temperature = <70000>; 1630 hysteresis = <1000>; 1631 type = "active"; 1632 }; 1633 1634 mem-shutdown-trip { 1635 temperature = <103000>; 1636 hysteresis = <0>; 1637 type = "critical"; 1638 }; 1639 }; 1640 1641 cooling-maps { 1642 dram-passive { 1643 cooling-device = <&emc 0 0>; 1644 trip = <&dram_nominal>; 1645 }; 1646 1647 dram-active { 1648 cooling-device = <&emc 1 1>; 1649 trip = <&dram_throttle>; 1650 }; 1651 }; 1652 }; 1653 1654 gpu { 1655 polling-delay-passive = <1000>; 1656 polling-delay = <0>; 1657 1658 thermal-sensors = 1659 <&soctherm TEGRA124_SOCTHERM_SENSOR_GPU>; 1660 1661 trips { 1662 gpu-shutdown-trip { 1663 temperature = <103000>; 1664 hysteresis = <0>; 1665 type = "critical"; 1666 }; 1667 1668 gpu_throttle_trip: throttle-trip { 1669 temperature = <100000>; 1670 hysteresis = <1000>; 1671 type = "hot"; 1672 }; 1673 }; 1674 1675 cooling-maps { 1676 map0 { 1677 trip = <&gpu_throttle_trip>; 1678 cooling-device = <&throttle_heavy 1 1>; 1679 }; 1680 }; 1681 }; 1682 1683 pllx { 1684 polling-delay-passive = <0>; 1685 polling-delay = <0>; 1686 1687 thermal-sensors = 1688 <&soctherm TEGRA124_SOCTHERM_SENSOR_PLLX>; 1689 1690 trips { 1691 pllx-shutdown-trip { 1692 temperature = <103000>; 1693 hysteresis = <0>; 1694 type = "critical"; 1695 }; 1696 }; 1697 1698 cooling-maps { 1699 /* 1700 * There are currently no cooling maps, 1701 * because there are no cooling devices. 1702 */ 1703 }; 1704 }; 1705 }; 1706}; 1707