1// SPDX-License-Identifier: GPL-2.0 2#include <dt-bindings/clock/tegra210-car.h> 3#include <dt-bindings/gpio/tegra-gpio.h> 4#include <dt-bindings/memory/tegra210-mc.h> 5#include <dt-bindings/pinctrl/pinctrl-tegra.h> 6#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 7#include <dt-bindings/reset/tegra210-car.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/thermal/tegra124-soctherm.h> 10#include <dt-bindings/soc/tegra-pmc.h> 11 12/ { 13 compatible = "nvidia,tegra210"; 14 interrupt-parent = <&lic>; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 18 pcie@1003000 { 19 compatible = "nvidia,tegra210-pcie"; 20 device_type = "pci"; 21 reg = <0x0 0x01003000 0x0 0x00000800>, /* PADS registers */ 22 <0x0 0x01003800 0x0 0x00000800>, /* AFI registers */ 23 <0x0 0x02000000 0x0 0x10000000>; /* configuration space */ 24 reg-names = "pads", "afi", "cs"; 25 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 26 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 27 interrupt-names = "intr", "msi"; 28 29 #interrupt-cells = <1>; 30 interrupt-map-mask = <0 0 0 0>; 31 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 32 33 bus-range = <0x00 0xff>; 34 #address-cells = <3>; 35 #size-cells = <2>; 36 37 ranges = <0x02000000 0 0x01000000 0x0 0x01000000 0 0x00001000>, /* port 0 configuration space */ 38 <0x02000000 0 0x01001000 0x0 0x01001000 0 0x00001000>, /* port 1 configuration space */ 39 <0x01000000 0 0x0 0x0 0x12000000 0 0x00010000>, /* downstream I/O (64 KiB) */ 40 <0x02000000 0 0x13000000 0x0 0x13000000 0 0x0d000000>, /* non-prefetchable memory (208 MiB) */ 41 <0x42000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */ 42 43 clocks = <&tegra_car TEGRA210_CLK_PCIE>, 44 <&tegra_car TEGRA210_CLK_AFI>, 45 <&tegra_car TEGRA210_CLK_PLL_E>, 46 <&tegra_car TEGRA210_CLK_CML0>; 47 clock-names = "pex", "afi", "pll_e", "cml"; 48 resets = <&tegra_car 70>, 49 <&tegra_car 72>, 50 <&tegra_car 74>; 51 reset-names = "pex", "afi", "pcie_x"; 52 53 pinctrl-names = "default", "idle"; 54 pinctrl-0 = <&pex_dpd_disable>; 55 pinctrl-1 = <&pex_dpd_enable>; 56 57 status = "disabled"; 58 59 pci@1,0 { 60 device_type = "pci"; 61 assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>; 62 reg = <0x000800 0 0 0 0>; 63 bus-range = <0x00 0xff>; 64 status = "disabled"; 65 66 #address-cells = <3>; 67 #size-cells = <2>; 68 ranges; 69 70 nvidia,num-lanes = <4>; 71 }; 72 73 pci@2,0 { 74 device_type = "pci"; 75 assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>; 76 reg = <0x001000 0 0 0 0>; 77 bus-range = <0x00 0xff>; 78 status = "disabled"; 79 80 #address-cells = <3>; 81 #size-cells = <2>; 82 ranges; 83 84 nvidia,num-lanes = <1>; 85 }; 86 }; 87 88 host1x@50000000 { 89 compatible = "nvidia,tegra210-host1x"; 90 reg = <0x0 0x50000000 0x0 0x00034000>; 91 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */ 92 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */ 93 interrupt-names = "syncpt", "host1x"; 94 clocks = <&tegra_car TEGRA210_CLK_HOST1X>; 95 clock-names = "host1x"; 96 resets = <&tegra_car 28>; 97 reset-names = "host1x"; 98 99 #address-cells = <2>; 100 #size-cells = <2>; 101 102 ranges = <0x0 0x54000000 0x0 0x54000000 0x0 0x01000000>; 103 104 iommus = <&mc TEGRA_SWGROUP_HC>; 105 106 dpaux1: dpaux@54040000 { 107 compatible = "nvidia,tegra210-dpaux"; 108 reg = <0x0 0x54040000 0x0 0x00040000>; 109 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 110 clocks = <&tegra_car TEGRA210_CLK_DPAUX1>, 111 <&tegra_car TEGRA210_CLK_PLL_DP>; 112 clock-names = "dpaux", "parent"; 113 resets = <&tegra_car 207>; 114 reset-names = "dpaux"; 115 power-domains = <&pd_sor>; 116 status = "disabled"; 117 118 state_dpaux1_aux: pinmux-aux { 119 groups = "dpaux-io"; 120 function = "aux"; 121 }; 122 123 state_dpaux1_i2c: pinmux-i2c { 124 groups = "dpaux-io"; 125 function = "i2c"; 126 }; 127 128 state_dpaux1_off: pinmux-off { 129 groups = "dpaux-io"; 130 function = "off"; 131 }; 132 133 i2c-bus { 134 #address-cells = <1>; 135 #size-cells = <0>; 136 }; 137 }; 138 139 vi@54080000 { 140 compatible = "nvidia,tegra210-vi"; 141 reg = <0x0 0x54080000 0x0 0x700>; 142 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 143 status = "disabled"; 144 assigned-clocks = <&tegra_car TEGRA210_CLK_VI>; 145 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; 146 147 clocks = <&tegra_car TEGRA210_CLK_VI>; 148 power-domains = <&pd_venc>; 149 150 #address-cells = <1>; 151 #size-cells = <1>; 152 153 ranges = <0x0 0x0 0x54080000 0x2000>; 154 155 csi@838 { 156 compatible = "nvidia,tegra210-csi"; 157 reg = <0x838 0x1300>; 158 status = "disabled"; 159 assigned-clocks = <&tegra_car TEGRA210_CLK_CILAB>, 160 <&tegra_car TEGRA210_CLK_CILCD>, 161 <&tegra_car TEGRA210_CLK_CILE>, 162 <&tegra_car TEGRA210_CLK_CSI_TPG>; 163 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_P>, 164 <&tegra_car TEGRA210_CLK_PLL_P>, 165 <&tegra_car TEGRA210_CLK_PLL_P>; 166 assigned-clock-rates = <102000000>, 167 <102000000>, 168 <102000000>, 169 <972000000>; 170 171 clocks = <&tegra_car TEGRA210_CLK_CSI>, 172 <&tegra_car TEGRA210_CLK_CILAB>, 173 <&tegra_car TEGRA210_CLK_CILCD>, 174 <&tegra_car TEGRA210_CLK_CILE>, 175 <&tegra_car TEGRA210_CLK_CSI_TPG>; 176 clock-names = "csi", "cilab", "cilcd", "cile", "csi_tpg"; 177 power-domains = <&pd_sor>; 178 }; 179 }; 180 181 tsec@54100000 { 182 compatible = "nvidia,tegra210-tsec"; 183 reg = <0x0 0x54100000 0x0 0x00040000>; 184 }; 185 186 dc@54200000 { 187 compatible = "nvidia,tegra210-dc"; 188 reg = <0x0 0x54200000 0x0 0x00040000>; 189 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 190 clocks = <&tegra_car TEGRA210_CLK_DISP1>; 191 clock-names = "dc"; 192 resets = <&tegra_car 27>; 193 reset-names = "dc"; 194 195 iommus = <&mc TEGRA_SWGROUP_DC>; 196 197 nvidia,head = <0>; 198 }; 199 200 dc@54240000 { 201 compatible = "nvidia,tegra210-dc"; 202 reg = <0x0 0x54240000 0x0 0x00040000>; 203 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 204 clocks = <&tegra_car TEGRA210_CLK_DISP2>; 205 clock-names = "dc"; 206 resets = <&tegra_car 26>; 207 reset-names = "dc"; 208 209 iommus = <&mc TEGRA_SWGROUP_DCB>; 210 211 nvidia,head = <1>; 212 }; 213 214 dsi@54300000 { 215 compatible = "nvidia,tegra210-dsi"; 216 reg = <0x0 0x54300000 0x0 0x00040000>; 217 clocks = <&tegra_car TEGRA210_CLK_DSIA>, 218 <&tegra_car TEGRA210_CLK_DSIALP>, 219 <&tegra_car TEGRA210_CLK_PLL_D_OUT0>; 220 clock-names = "dsi", "lp", "parent"; 221 resets = <&tegra_car 48>; 222 reset-names = "dsi"; 223 power-domains = <&pd_sor>; 224 nvidia,mipi-calibrate = <&mipi 0x0c0>; /* DSIA & DSIB pads */ 225 226 status = "disabled"; 227 228 #address-cells = <1>; 229 #size-cells = <0>; 230 }; 231 232 vic@54340000 { 233 compatible = "nvidia,tegra210-vic"; 234 reg = <0x0 0x54340000 0x0 0x00040000>; 235 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 236 clocks = <&tegra_car TEGRA210_CLK_VIC03>; 237 clock-names = "vic"; 238 resets = <&tegra_car 178>; 239 reset-names = "vic"; 240 241 iommus = <&mc TEGRA_SWGROUP_VIC>; 242 power-domains = <&pd_vic>; 243 }; 244 245 nvjpg@54380000 { 246 compatible = "nvidia,tegra210-nvjpg"; 247 reg = <0x0 0x54380000 0x0 0x00040000>; 248 status = "disabled"; 249 }; 250 251 dsi@54400000 { 252 compatible = "nvidia,tegra210-dsi"; 253 reg = <0x0 0x54400000 0x0 0x00040000>; 254 clocks = <&tegra_car TEGRA210_CLK_DSIB>, 255 <&tegra_car TEGRA210_CLK_DSIBLP>, 256 <&tegra_car TEGRA210_CLK_PLL_D_OUT0>; 257 clock-names = "dsi", "lp", "parent"; 258 resets = <&tegra_car 82>; 259 reset-names = "dsi"; 260 power-domains = <&pd_sor>; 261 nvidia,mipi-calibrate = <&mipi 0x300>; /* DSIC & DSID pads */ 262 263 status = "disabled"; 264 265 #address-cells = <1>; 266 #size-cells = <0>; 267 }; 268 269 nvdec@54480000 { 270 compatible = "nvidia,tegra210-nvdec"; 271 reg = <0x0 0x54480000 0x0 0x00040000>; 272 status = "disabled"; 273 }; 274 275 nvenc@544c0000 { 276 compatible = "nvidia,tegra210-nvenc"; 277 reg = <0x0 0x544c0000 0x0 0x00040000>; 278 status = "disabled"; 279 }; 280 281 tsec@54500000 { 282 compatible = "nvidia,tegra210-tsec"; 283 reg = <0x0 0x54500000 0x0 0x00040000>; 284 status = "disabled"; 285 }; 286 287 sor@54540000 { 288 compatible = "nvidia,tegra210-sor"; 289 reg = <0x0 0x54540000 0x0 0x00040000>; 290 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 291 clocks = <&tegra_car TEGRA210_CLK_SOR0>, 292 <&tegra_car TEGRA210_CLK_SOR0_OUT>, 293 <&tegra_car TEGRA210_CLK_PLL_D_OUT0>, 294 <&tegra_car TEGRA210_CLK_PLL_DP>, 295 <&tegra_car TEGRA210_CLK_SOR_SAFE>; 296 clock-names = "sor", "out", "parent", "dp", "safe"; 297 resets = <&tegra_car 182>; 298 reset-names = "sor"; 299 pinctrl-0 = <&state_dpaux_aux>; 300 pinctrl-1 = <&state_dpaux_i2c>; 301 pinctrl-2 = <&state_dpaux_off>; 302 pinctrl-names = "aux", "i2c", "off"; 303 power-domains = <&pd_sor>; 304 status = "disabled"; 305 }; 306 307 sor@54580000 { 308 compatible = "nvidia,tegra210-sor1"; 309 reg = <0x0 0x54580000 0x0 0x00040000>; 310 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 311 clocks = <&tegra_car TEGRA210_CLK_SOR1>, 312 <&tegra_car TEGRA210_CLK_SOR1_OUT>, 313 <&tegra_car TEGRA210_CLK_PLL_D2_OUT0>, 314 <&tegra_car TEGRA210_CLK_PLL_DP>, 315 <&tegra_car TEGRA210_CLK_SOR_SAFE>; 316 clock-names = "sor", "out", "parent", "dp", "safe"; 317 resets = <&tegra_car 183>; 318 reset-names = "sor"; 319 pinctrl-0 = <&state_dpaux1_aux>; 320 pinctrl-1 = <&state_dpaux1_i2c>; 321 pinctrl-2 = <&state_dpaux1_off>; 322 pinctrl-names = "aux", "i2c", "off"; 323 power-domains = <&pd_sor>; 324 status = "disabled"; 325 }; 326 327 dpaux: dpaux@545c0000 { 328 compatible = "nvidia,tegra210-dpaux"; 329 reg = <0x0 0x545c0000 0x0 0x00040000>; 330 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 331 clocks = <&tegra_car TEGRA210_CLK_DPAUX>, 332 <&tegra_car TEGRA210_CLK_PLL_DP>; 333 clock-names = "dpaux", "parent"; 334 resets = <&tegra_car 181>; 335 reset-names = "dpaux"; 336 power-domains = <&pd_sor>; 337 status = "disabled"; 338 339 state_dpaux_aux: pinmux-aux { 340 groups = "dpaux-io"; 341 function = "aux"; 342 }; 343 344 state_dpaux_i2c: pinmux-i2c { 345 groups = "dpaux-io"; 346 function = "i2c"; 347 }; 348 349 state_dpaux_off: pinmux-off { 350 groups = "dpaux-io"; 351 function = "off"; 352 }; 353 354 i2c-bus { 355 #address-cells = <1>; 356 #size-cells = <0>; 357 }; 358 }; 359 360 isp@54600000 { 361 compatible = "nvidia,tegra210-isp"; 362 reg = <0x0 0x54600000 0x0 0x00040000>; 363 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 364 status = "disabled"; 365 }; 366 367 isp@54680000 { 368 compatible = "nvidia,tegra210-isp"; 369 reg = <0x0 0x54680000 0x0 0x00040000>; 370 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 371 status = "disabled"; 372 }; 373 374 i2c@546c0000 { 375 compatible = "nvidia,tegra210-i2c-vi"; 376 reg = <0x0 0x546c0000 0x0 0x00040000>; 377 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 378 status = "disabled"; 379 }; 380 }; 381 382 gic: interrupt-controller@50041000 { 383 compatible = "arm,gic-400"; 384 #interrupt-cells = <3>; 385 interrupt-controller; 386 reg = <0x0 0x50041000 0x0 0x1000>, 387 <0x0 0x50042000 0x0 0x2000>, 388 <0x0 0x50044000 0x0 0x2000>, 389 <0x0 0x50046000 0x0 0x2000>; 390 interrupts = <GIC_PPI 9 391 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 392 interrupt-parent = <&gic>; 393 }; 394 395 gpu@57000000 { 396 compatible = "nvidia,gm20b"; 397 reg = <0x0 0x57000000 0x0 0x01000000>, 398 <0x0 0x58000000 0x0 0x01000000>; 399 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 400 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 401 interrupt-names = "stall", "nonstall"; 402 clocks = <&tegra_car TEGRA210_CLK_GPU>, 403 <&tegra_car TEGRA210_CLK_PLL_P_OUT5>, 404 <&tegra_car TEGRA210_CLK_PLL_G_REF>; 405 clock-names = "gpu", "pwr", "ref"; 406 resets = <&tegra_car 184>; 407 reset-names = "gpu"; 408 409 iommus = <&mc TEGRA_SWGROUP_GPU>; 410 411 status = "disabled"; 412 }; 413 414 lic: interrupt-controller@60004000 { 415 compatible = "nvidia,tegra210-ictlr"; 416 reg = <0x0 0x60004000 0x0 0x40>, /* primary controller */ 417 <0x0 0x60004100 0x0 0x40>, /* secondary controller */ 418 <0x0 0x60004200 0x0 0x40>, /* tertiary controller */ 419 <0x0 0x60004300 0x0 0x40>, /* quaternary controller */ 420 <0x0 0x60004400 0x0 0x40>, /* quinary controller */ 421 <0x0 0x60004500 0x0 0x40>; /* senary controller */ 422 interrupt-controller; 423 #interrupt-cells = <3>; 424 interrupt-parent = <&gic>; 425 }; 426 427 timer@60005000 { 428 compatible = "nvidia,tegra210-timer"; 429 reg = <0x0 0x60005000 0x0 0x400>; 430 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, 431 <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 432 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 433 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 434 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 435 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 436 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 437 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 438 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 439 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 440 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 441 <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>, 442 <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>, 443 <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; 444 clocks = <&tegra_car TEGRA210_CLK_TIMER>; 445 clock-names = "timer"; 446 }; 447 448 tegra_car: clock@60006000 { 449 compatible = "nvidia,tegra210-car"; 450 reg = <0x0 0x60006000 0x0 0x1000>; 451 #clock-cells = <1>; 452 #reset-cells = <1>; 453 }; 454 455 flow-controller@60007000 { 456 compatible = "nvidia,tegra210-flowctrl"; 457 reg = <0x0 0x60007000 0x0 0x1000>; 458 }; 459 460 gpio: gpio@6000d000 { 461 compatible = "nvidia,tegra210-gpio", "nvidia,tegra30-gpio"; 462 reg = <0x0 0x6000d000 0x0 0x1000>; 463 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 464 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 465 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 466 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 467 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 468 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 469 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 470 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 471 #gpio-cells = <2>; 472 gpio-controller; 473 #interrupt-cells = <2>; 474 interrupt-controller; 475 }; 476 477 apbdma: dma@60020000 { 478 compatible = "nvidia,tegra210-apbdma", "nvidia,tegra148-apbdma"; 479 reg = <0x0 0x60020000 0x0 0x1400>; 480 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 481 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 482 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 483 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 484 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 485 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 486 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 487 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 488 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 489 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 490 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 491 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 492 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 493 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 494 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 495 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 496 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 497 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 498 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 499 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 500 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 501 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 502 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 503 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 504 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 505 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 506 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 507 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 508 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 509 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 510 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 511 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 512 clocks = <&tegra_car TEGRA210_CLK_APBDMA>; 513 clock-names = "dma"; 514 resets = <&tegra_car 34>; 515 reset-names = "dma"; 516 #dma-cells = <1>; 517 }; 518 519 apbmisc@70000800 { 520 compatible = "nvidia,tegra210-apbmisc", "nvidia,tegra20-apbmisc"; 521 reg = <0x0 0x70000800 0x0 0x64>, /* Chip revision */ 522 <0x0 0x70000008 0x0 0x04>; /* Strapping options */ 523 }; 524 525 pinmux: pinmux@700008d4 { 526 compatible = "nvidia,tegra210-pinmux"; 527 reg = <0x0 0x700008d4 0x0 0x29c>, /* Pad control registers */ 528 <0x0 0x70003000 0x0 0x294>; /* Mux registers */ 529 sdmmc1_3v3_drv: sdmmc1-3v3-drv { 530 sdmmc1 { 531 nvidia,pins = "drive_sdmmc1"; 532 nvidia,pull-down-strength = <0x8>; 533 nvidia,pull-up-strength = <0x8>; 534 }; 535 }; 536 sdmmc1_1v8_drv: sdmmc1-1v8-drv { 537 sdmmc1 { 538 nvidia,pins = "drive_sdmmc1"; 539 nvidia,pull-down-strength = <0x4>; 540 nvidia,pull-up-strength = <0x3>; 541 }; 542 }; 543 sdmmc2_1v8_drv: sdmmc2-1v8-drv { 544 sdmmc2 { 545 nvidia,pins = "drive_sdmmc2"; 546 nvidia,pull-down-strength = <0x10>; 547 nvidia,pull-up-strength = <0x10>; 548 }; 549 }; 550 sdmmc3_3v3_drv: sdmmc3-3v3-drv { 551 sdmmc3 { 552 nvidia,pins = "drive_sdmmc3"; 553 nvidia,pull-down-strength = <0x8>; 554 nvidia,pull-up-strength = <0x8>; 555 }; 556 }; 557 sdmmc3_1v8_drv: sdmmc3-1v8-drv { 558 sdmmc3 { 559 nvidia,pins = "drive_sdmmc3"; 560 nvidia,pull-down-strength = <0x4>; 561 nvidia,pull-up-strength = <0x3>; 562 }; 563 }; 564 sdmmc4_1v8_drv: sdmmc4-1v8-drv { 565 sdmmc4 { 566 nvidia,pins = "drive_sdmmc4"; 567 nvidia,pull-down-strength = <0x10>; 568 nvidia,pull-up-strength = <0x10>; 569 }; 570 }; 571 }; 572 573 /* 574 * There are two serial driver i.e. 8250 based simple serial 575 * driver and APB DMA based serial driver for higher baudrate 576 * and performance. To enable the 8250 based driver, the compatible 577 * is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable 578 * the APB DMA based serial driver, the compatible is 579 * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart". 580 */ 581 uarta: serial@70006000 { 582 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; 583 reg = <0x0 0x70006000 0x0 0x40>; 584 reg-shift = <2>; 585 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 586 clocks = <&tegra_car TEGRA210_CLK_UARTA>; 587 clock-names = "serial"; 588 resets = <&tegra_car 6>; 589 reset-names = "serial"; 590 dmas = <&apbdma 8>, <&apbdma 8>; 591 dma-names = "rx", "tx"; 592 status = "disabled"; 593 }; 594 595 uartb: serial@70006040 { 596 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; 597 reg = <0x0 0x70006040 0x0 0x40>; 598 reg-shift = <2>; 599 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 600 clocks = <&tegra_car TEGRA210_CLK_UARTB>; 601 clock-names = "serial"; 602 resets = <&tegra_car 7>; 603 reset-names = "serial"; 604 dmas = <&apbdma 9>, <&apbdma 9>; 605 dma-names = "rx", "tx"; 606 status = "disabled"; 607 }; 608 609 uartc: serial@70006200 { 610 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; 611 reg = <0x0 0x70006200 0x0 0x40>; 612 reg-shift = <2>; 613 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 614 clocks = <&tegra_car TEGRA210_CLK_UARTC>; 615 clock-names = "serial"; 616 resets = <&tegra_car 55>; 617 reset-names = "serial"; 618 dmas = <&apbdma 10>, <&apbdma 10>; 619 dma-names = "rx", "tx"; 620 status = "disabled"; 621 }; 622 623 uartd: serial@70006300 { 624 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; 625 reg = <0x0 0x70006300 0x0 0x40>; 626 reg-shift = <2>; 627 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 628 clocks = <&tegra_car TEGRA210_CLK_UARTD>; 629 clock-names = "serial"; 630 resets = <&tegra_car 65>; 631 reset-names = "serial"; 632 dmas = <&apbdma 19>, <&apbdma 19>; 633 dma-names = "rx", "tx"; 634 status = "disabled"; 635 }; 636 637 pwm: pwm@7000a000 { 638 compatible = "nvidia,tegra210-pwm", "nvidia,tegra20-pwm"; 639 reg = <0x0 0x7000a000 0x0 0x100>; 640 #pwm-cells = <2>; 641 clocks = <&tegra_car TEGRA210_CLK_PWM>; 642 clock-names = "pwm"; 643 resets = <&tegra_car 17>; 644 reset-names = "pwm"; 645 status = "disabled"; 646 }; 647 648 i2c@7000c000 { 649 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; 650 reg = <0x0 0x7000c000 0x0 0x100>; 651 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 652 #address-cells = <1>; 653 #size-cells = <0>; 654 clocks = <&tegra_car TEGRA210_CLK_I2C1>; 655 clock-names = "div-clk"; 656 resets = <&tegra_car 12>; 657 reset-names = "i2c"; 658 dmas = <&apbdma 21>, <&apbdma 21>; 659 dma-names = "rx", "tx"; 660 status = "disabled"; 661 }; 662 663 i2c@7000c400 { 664 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; 665 reg = <0x0 0x7000c400 0x0 0x100>; 666 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 667 #address-cells = <1>; 668 #size-cells = <0>; 669 clocks = <&tegra_car TEGRA210_CLK_I2C2>; 670 clock-names = "div-clk"; 671 resets = <&tegra_car 54>; 672 reset-names = "i2c"; 673 dmas = <&apbdma 22>, <&apbdma 22>; 674 dma-names = "rx", "tx"; 675 status = "disabled"; 676 }; 677 678 i2c@7000c500 { 679 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; 680 reg = <0x0 0x7000c500 0x0 0x100>; 681 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 682 #address-cells = <1>; 683 #size-cells = <0>; 684 clocks = <&tegra_car TEGRA210_CLK_I2C3>; 685 clock-names = "div-clk"; 686 resets = <&tegra_car 67>; 687 reset-names = "i2c"; 688 dmas = <&apbdma 23>, <&apbdma 23>; 689 dma-names = "rx", "tx"; 690 status = "disabled"; 691 }; 692 693 i2c@7000c700 { 694 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; 695 reg = <0x0 0x7000c700 0x0 0x100>; 696 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 697 #address-cells = <1>; 698 #size-cells = <0>; 699 clocks = <&tegra_car TEGRA210_CLK_I2C4>; 700 clock-names = "div-clk"; 701 resets = <&tegra_car 103>; 702 reset-names = "i2c"; 703 dmas = <&apbdma 26>, <&apbdma 26>; 704 dma-names = "rx", "tx"; 705 pinctrl-0 = <&state_dpaux1_i2c>; 706 pinctrl-1 = <&state_dpaux1_off>; 707 pinctrl-names = "default", "idle"; 708 status = "disabled"; 709 }; 710 711 i2c@7000d000 { 712 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; 713 reg = <0x0 0x7000d000 0x0 0x100>; 714 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 715 #address-cells = <1>; 716 #size-cells = <0>; 717 clocks = <&tegra_car TEGRA210_CLK_I2C5>; 718 clock-names = "div-clk"; 719 resets = <&tegra_car 47>; 720 reset-names = "i2c"; 721 dmas = <&apbdma 24>, <&apbdma 24>; 722 dma-names = "rx", "tx"; 723 status = "disabled"; 724 }; 725 726 i2c@7000d100 { 727 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; 728 reg = <0x0 0x7000d100 0x0 0x100>; 729 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 730 #address-cells = <1>; 731 #size-cells = <0>; 732 clocks = <&tegra_car TEGRA210_CLK_I2C6>; 733 clock-names = "div-clk"; 734 resets = <&tegra_car 166>; 735 reset-names = "i2c"; 736 dmas = <&apbdma 30>, <&apbdma 30>; 737 dma-names = "rx", "tx"; 738 pinctrl-0 = <&state_dpaux_i2c>; 739 pinctrl-1 = <&state_dpaux_off>; 740 pinctrl-names = "default", "idle"; 741 status = "disabled"; 742 }; 743 744 spi@7000d400 { 745 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 746 reg = <0x0 0x7000d400 0x0 0x200>; 747 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 748 #address-cells = <1>; 749 #size-cells = <0>; 750 clocks = <&tegra_car TEGRA210_CLK_SBC1>; 751 clock-names = "spi"; 752 resets = <&tegra_car 41>; 753 reset-names = "spi"; 754 dmas = <&apbdma 15>, <&apbdma 15>; 755 dma-names = "rx", "tx"; 756 status = "disabled"; 757 }; 758 759 spi@7000d600 { 760 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 761 reg = <0x0 0x7000d600 0x0 0x200>; 762 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 763 #address-cells = <1>; 764 #size-cells = <0>; 765 clocks = <&tegra_car TEGRA210_CLK_SBC2>; 766 clock-names = "spi"; 767 resets = <&tegra_car 44>; 768 reset-names = "spi"; 769 dmas = <&apbdma 16>, <&apbdma 16>; 770 dma-names = "rx", "tx"; 771 status = "disabled"; 772 }; 773 774 spi@7000d800 { 775 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 776 reg = <0x0 0x7000d800 0x0 0x200>; 777 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 778 #address-cells = <1>; 779 #size-cells = <0>; 780 clocks = <&tegra_car TEGRA210_CLK_SBC3>; 781 clock-names = "spi"; 782 resets = <&tegra_car 46>; 783 reset-names = "spi"; 784 dmas = <&apbdma 17>, <&apbdma 17>; 785 dma-names = "rx", "tx"; 786 status = "disabled"; 787 }; 788 789 spi@7000da00 { 790 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 791 reg = <0x0 0x7000da00 0x0 0x200>; 792 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 793 #address-cells = <1>; 794 #size-cells = <0>; 795 clocks = <&tegra_car TEGRA210_CLK_SBC4>; 796 clock-names = "spi"; 797 resets = <&tegra_car 68>; 798 reset-names = "spi"; 799 dmas = <&apbdma 18>, <&apbdma 18>; 800 dma-names = "rx", "tx"; 801 status = "disabled"; 802 }; 803 804 rtc@7000e000 { 805 compatible = "nvidia,tegra210-rtc", "nvidia,tegra20-rtc"; 806 reg = <0x0 0x7000e000 0x0 0x100>; 807 interrupts = <16 IRQ_TYPE_LEVEL_HIGH>; 808 interrupt-parent = <&tegra_pmc>; 809 clocks = <&tegra_car TEGRA210_CLK_RTC>; 810 clock-names = "rtc"; 811 }; 812 813 tegra_pmc: pmc@7000e400 { 814 compatible = "nvidia,tegra210-pmc"; 815 reg = <0x0 0x7000e400 0x0 0x400>; 816 clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>; 817 clock-names = "pclk", "clk32k_in"; 818 #clock-cells = <1>; 819 #interrupt-cells = <2>; 820 interrupt-controller; 821 822 powergates { 823 pd_audio: aud { 824 clocks = <&tegra_car TEGRA210_CLK_APE>, 825 <&tegra_car TEGRA210_CLK_APB2APE>; 826 resets = <&tegra_car 198>; 827 #power-domain-cells = <0>; 828 }; 829 830 pd_sor: sor { 831 clocks = <&tegra_car TEGRA210_CLK_SOR0>, 832 <&tegra_car TEGRA210_CLK_SOR1>, 833 <&tegra_car TEGRA210_CLK_CILAB>, 834 <&tegra_car TEGRA210_CLK_CILCD>, 835 <&tegra_car TEGRA210_CLK_CILE>, 836 <&tegra_car TEGRA210_CLK_DSIA>, 837 <&tegra_car TEGRA210_CLK_DSIB>, 838 <&tegra_car TEGRA210_CLK_DPAUX>, 839 <&tegra_car TEGRA210_CLK_DPAUX1>, 840 <&tegra_car TEGRA210_CLK_MIPI_CAL>; 841 resets = <&tegra_car TEGRA210_CLK_SOR0>, 842 <&tegra_car TEGRA210_CLK_SOR1>, 843 <&tegra_car TEGRA210_CLK_DSIA>, 844 <&tegra_car TEGRA210_CLK_DSIB>, 845 <&tegra_car TEGRA210_CLK_DPAUX>, 846 <&tegra_car TEGRA210_CLK_DPAUX1>, 847 <&tegra_car TEGRA210_CLK_MIPI_CAL>; 848 #power-domain-cells = <0>; 849 }; 850 851 pd_xusbss: xusba { 852 clocks = <&tegra_car TEGRA210_CLK_XUSB_SS>; 853 resets = <&tegra_car TEGRA210_CLK_XUSB_SS>; 854 #power-domain-cells = <0>; 855 }; 856 857 pd_xusbdev: xusbb { 858 clocks = <&tegra_car TEGRA210_CLK_XUSB_DEV>; 859 resets = <&tegra_car 95>; 860 #power-domain-cells = <0>; 861 }; 862 863 pd_xusbhost: xusbc { 864 clocks = <&tegra_car TEGRA210_CLK_XUSB_HOST>; 865 resets = <&tegra_car TEGRA210_CLK_XUSB_HOST>; 866 #power-domain-cells = <0>; 867 }; 868 869 pd_vic: vic { 870 clocks = <&tegra_car TEGRA210_CLK_VIC03>; 871 clock-names = "vic"; 872 resets = <&tegra_car 178>; 873 reset-names = "vic"; 874 #power-domain-cells = <0>; 875 }; 876 877 pd_venc: venc { 878 clocks = <&tegra_car TEGRA210_CLK_VI>, 879 <&tegra_car TEGRA210_CLK_CSI>; 880 resets = <&mc TEGRA210_MC_RESET_VI>, 881 <&tegra_car 20>, 882 <&tegra_car 52>; 883 #power-domain-cells = <0>; 884 }; 885 }; 886 887 sdmmc1_3v3: sdmmc1-3v3 { 888 pins = "sdmmc1"; 889 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 890 }; 891 892 sdmmc1_1v8: sdmmc1-1v8 { 893 pins = "sdmmc1"; 894 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 895 }; 896 897 sdmmc3_3v3: sdmmc3-3v3 { 898 pins = "sdmmc3"; 899 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 900 }; 901 902 sdmmc3_1v8: sdmmc3-1v8 { 903 pins = "sdmmc3"; 904 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 905 }; 906 907 pex_dpd_disable: pex_en { 908 pex-dpd-disable { 909 pins = "pex-bias", "pex-clk1", "pex-clk2"; 910 low-power-disable; 911 }; 912 }; 913 914 pex_dpd_enable: pex_dis { 915 pex-dpd-enable { 916 pins = "pex-bias", "pex-clk1", "pex-clk2"; 917 low-power-enable; 918 }; 919 }; 920 }; 921 922 fuse@7000f800 { 923 compatible = "nvidia,tegra210-efuse"; 924 reg = <0x0 0x7000f800 0x0 0x400>; 925 clocks = <&tegra_car TEGRA210_CLK_FUSE>; 926 clock-names = "fuse"; 927 resets = <&tegra_car 39>; 928 reset-names = "fuse"; 929 }; 930 931 mc: memory-controller@70019000 { 932 compatible = "nvidia,tegra210-mc"; 933 reg = <0x0 0x70019000 0x0 0x1000>; 934 clocks = <&tegra_car TEGRA210_CLK_MC>; 935 clock-names = "mc"; 936 937 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 938 939 #iommu-cells = <1>; 940 #reset-cells = <1>; 941 }; 942 943 emc: external-memory-controller@7001b000 { 944 compatible = "nvidia,tegra210-emc"; 945 reg = <0x0 0x7001b000 0x0 0x1000>, 946 <0x0 0x7001e000 0x0 0x1000>, 947 <0x0 0x7001f000 0x0 0x1000>; 948 clocks = <&tegra_car TEGRA210_CLK_EMC>; 949 clock-names = "emc"; 950 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 951 nvidia,memory-controller = <&mc>; 952 #cooling-cells = <2>; 953 }; 954 955 sata@70020000 { 956 compatible = "nvidia,tegra210-ahci"; 957 reg = <0x0 0x70027000 0x0 0x2000>, /* AHCI */ 958 <0x0 0x70020000 0x0 0x7000>, /* SATA */ 959 <0x0 0x70001100 0x0 0x1000>; /* SATA AUX */ 960 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 961 clocks = <&tegra_car TEGRA210_CLK_SATA>, 962 <&tegra_car TEGRA210_CLK_SATA_OOB>; 963 clock-names = "sata", "sata-oob"; 964 resets = <&tegra_car 124>, 965 <&tegra_car 123>, 966 <&tegra_car 129>; 967 reset-names = "sata", "sata-oob", "sata-cold"; 968 status = "disabled"; 969 }; 970 971 hda@70030000 { 972 compatible = "nvidia,tegra210-hda", "nvidia,tegra30-hda"; 973 reg = <0x0 0x70030000 0x0 0x10000>; 974 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 975 clocks = <&tegra_car TEGRA210_CLK_HDA>, 976 <&tegra_car TEGRA210_CLK_HDA2HDMI>, 977 <&tegra_car TEGRA210_CLK_HDA2CODEC_2X>; 978 clock-names = "hda", "hda2hdmi", "hda2codec_2x"; 979 resets = <&tegra_car 125>, /* hda */ 980 <&tegra_car 128>, /* hda2hdmi */ 981 <&tegra_car 111>; /* hda2codec_2x */ 982 reset-names = "hda", "hda2hdmi", "hda2codec_2x"; 983 status = "disabled"; 984 }; 985 986 usb@70090000 { 987 compatible = "nvidia,tegra210-xusb"; 988 reg = <0x0 0x70090000 0x0 0x8000>, 989 <0x0 0x70098000 0x0 0x1000>, 990 <0x0 0x70099000 0x0 0x1000>; 991 reg-names = "hcd", "fpci", "ipfs"; 992 993 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 994 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 995 996 clocks = <&tegra_car TEGRA210_CLK_XUSB_HOST>, 997 <&tegra_car TEGRA210_CLK_XUSB_HOST_SRC>, 998 <&tegra_car TEGRA210_CLK_XUSB_FALCON_SRC>, 999 <&tegra_car TEGRA210_CLK_XUSB_SS>, 1000 <&tegra_car TEGRA210_CLK_XUSB_SS_SRC>, 1001 <&tegra_car TEGRA210_CLK_XUSB_SS_DIV2>, 1002 <&tegra_car TEGRA210_CLK_XUSB_HS_SRC>, 1003 <&tegra_car TEGRA210_CLK_XUSB_FS_SRC>, 1004 <&tegra_car TEGRA210_CLK_PLL_U_480M>, 1005 <&tegra_car TEGRA210_CLK_CLK_M>, 1006 <&tegra_car TEGRA210_CLK_PLL_E>; 1007 clock-names = "xusb_host", "xusb_host_src", 1008 "xusb_falcon_src", "xusb_ss", 1009 "xusb_ss_src", "xusb_ss_div2", 1010 "xusb_hs_src", "xusb_fs_src", 1011 "pll_u_480m", "clk_m", "pll_e"; 1012 resets = <&tegra_car 89>, <&tegra_car 156>, 1013 <&tegra_car 143>; 1014 reset-names = "xusb_host", "xusb_ss", "xusb_src"; 1015 power-domains = <&pd_xusbhost>, <&pd_xusbss>; 1016 power-domain-names = "xusb_host", "xusb_ss"; 1017 1018 nvidia,xusb-padctl = <&padctl>; 1019 1020 status = "disabled"; 1021 }; 1022 1023 padctl: padctl@7009f000 { 1024 compatible = "nvidia,tegra210-xusb-padctl"; 1025 reg = <0x0 0x7009f000 0x0 0x1000>; 1026 resets = <&tegra_car 142>; 1027 reset-names = "padctl"; 1028 1029 status = "disabled"; 1030 1031 pads { 1032 usb2 { 1033 clocks = <&tegra_car TEGRA210_CLK_USB2_TRK>; 1034 clock-names = "trk"; 1035 status = "disabled"; 1036 1037 lanes { 1038 usb2-0 { 1039 status = "disabled"; 1040 #phy-cells = <0>; 1041 }; 1042 1043 usb2-1 { 1044 status = "disabled"; 1045 #phy-cells = <0>; 1046 }; 1047 1048 usb2-2 { 1049 status = "disabled"; 1050 #phy-cells = <0>; 1051 }; 1052 1053 usb2-3 { 1054 status = "disabled"; 1055 #phy-cells = <0>; 1056 }; 1057 }; 1058 }; 1059 1060 hsic { 1061 clocks = <&tegra_car TEGRA210_CLK_HSIC_TRK>; 1062 clock-names = "trk"; 1063 status = "disabled"; 1064 1065 lanes { 1066 hsic-0 { 1067 status = "disabled"; 1068 #phy-cells = <0>; 1069 }; 1070 1071 hsic-1 { 1072 status = "disabled"; 1073 #phy-cells = <0>; 1074 }; 1075 }; 1076 }; 1077 1078 pcie { 1079 clocks = <&tegra_car TEGRA210_CLK_PLL_E>; 1080 clock-names = "pll"; 1081 resets = <&tegra_car 205>; 1082 reset-names = "phy"; 1083 status = "disabled"; 1084 1085 lanes { 1086 pcie-0 { 1087 status = "disabled"; 1088 #phy-cells = <0>; 1089 }; 1090 1091 pcie-1 { 1092 status = "disabled"; 1093 #phy-cells = <0>; 1094 }; 1095 1096 pcie-2 { 1097 status = "disabled"; 1098 #phy-cells = <0>; 1099 }; 1100 1101 pcie-3 { 1102 status = "disabled"; 1103 #phy-cells = <0>; 1104 }; 1105 1106 pcie-4 { 1107 status = "disabled"; 1108 #phy-cells = <0>; 1109 }; 1110 1111 pcie-5 { 1112 status = "disabled"; 1113 #phy-cells = <0>; 1114 }; 1115 1116 pcie-6 { 1117 status = "disabled"; 1118 #phy-cells = <0>; 1119 }; 1120 }; 1121 }; 1122 1123 sata { 1124 clocks = <&tegra_car TEGRA210_CLK_PLL_E>; 1125 clock-names = "pll"; 1126 resets = <&tegra_car 204>; 1127 reset-names = "phy"; 1128 status = "disabled"; 1129 1130 lanes { 1131 sata-0 { 1132 status = "disabled"; 1133 #phy-cells = <0>; 1134 }; 1135 }; 1136 }; 1137 }; 1138 1139 ports { 1140 usb2-0 { 1141 status = "disabled"; 1142 }; 1143 1144 usb2-1 { 1145 status = "disabled"; 1146 }; 1147 1148 usb2-2 { 1149 status = "disabled"; 1150 }; 1151 1152 usb2-3 { 1153 status = "disabled"; 1154 }; 1155 1156 hsic-0 { 1157 status = "disabled"; 1158 }; 1159 1160 usb3-0 { 1161 status = "disabled"; 1162 }; 1163 1164 usb3-1 { 1165 status = "disabled"; 1166 }; 1167 1168 usb3-2 { 1169 status = "disabled"; 1170 }; 1171 1172 usb3-3 { 1173 status = "disabled"; 1174 }; 1175 }; 1176 }; 1177 1178 mmc@700b0000 { 1179 compatible = "nvidia,tegra210-sdhci"; 1180 reg = <0x0 0x700b0000 0x0 0x200>; 1181 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1182 clocks = <&tegra_car TEGRA210_CLK_SDMMC1>; 1183 clock-names = "sdhci"; 1184 resets = <&tegra_car 14>; 1185 reset-names = "sdhci"; 1186 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8", 1187 "sdmmc-3v3-drv", "sdmmc-1v8-drv"; 1188 pinctrl-0 = <&sdmmc1_3v3>; 1189 pinctrl-1 = <&sdmmc1_1v8>; 1190 pinctrl-2 = <&sdmmc1_3v3_drv>; 1191 pinctrl-3 = <&sdmmc1_1v8_drv>; 1192 nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>; 1193 nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>; 1194 nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>; 1195 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7b>; 1196 nvidia,default-tap = <0x2>; 1197 nvidia,default-trim = <0x4>; 1198 assigned-clocks = <&tegra_car TEGRA210_CLK_SDMMC4>, 1199 <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>, 1200 <&tegra_car TEGRA210_CLK_PLL_C4>; 1201 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; 1202 assigned-clock-rates = <200000000>, <1000000000>, <1000000000>; 1203 status = "disabled"; 1204 }; 1205 1206 mmc@700b0200 { 1207 compatible = "nvidia,tegra210-sdhci"; 1208 reg = <0x0 0x700b0200 0x0 0x200>; 1209 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 1210 clocks = <&tegra_car TEGRA210_CLK_SDMMC2>; 1211 clock-names = "sdhci"; 1212 resets = <&tegra_car 9>; 1213 reset-names = "sdhci"; 1214 pinctrl-names = "sdmmc-1v8-drv"; 1215 pinctrl-0 = <&sdmmc2_1v8_drv>; 1216 nvidia,pad-autocal-pull-up-offset-1v8 = <0x05>; 1217 nvidia,pad-autocal-pull-down-offset-1v8 = <0x05>; 1218 nvidia,default-tap = <0x8>; 1219 nvidia,default-trim = <0x0>; 1220 status = "disabled"; 1221 }; 1222 1223 mmc@700b0400 { 1224 compatible = "nvidia,tegra210-sdhci"; 1225 reg = <0x0 0x700b0400 0x0 0x200>; 1226 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 1227 clocks = <&tegra_car TEGRA210_CLK_SDMMC3>; 1228 clock-names = "sdhci"; 1229 resets = <&tegra_car 69>; 1230 reset-names = "sdhci"; 1231 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8", 1232 "sdmmc-3v3-drv", "sdmmc-1v8-drv"; 1233 pinctrl-0 = <&sdmmc3_3v3>; 1234 pinctrl-1 = <&sdmmc3_1v8>; 1235 pinctrl-2 = <&sdmmc3_3v3_drv>; 1236 pinctrl-3 = <&sdmmc3_1v8_drv>; 1237 nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>; 1238 nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>; 1239 nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>; 1240 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7b>; 1241 nvidia,default-tap = <0x3>; 1242 nvidia,default-trim = <0x3>; 1243 status = "disabled"; 1244 }; 1245 1246 mmc@700b0600 { 1247 compatible = "nvidia,tegra210-sdhci"; 1248 reg = <0x0 0x700b0600 0x0 0x200>; 1249 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 1250 clocks = <&tegra_car TEGRA210_CLK_SDMMC4>; 1251 clock-names = "sdhci"; 1252 resets = <&tegra_car 15>; 1253 reset-names = "sdhci"; 1254 pinctrl-names = "sdmmc-3v3-drv", "sdmmc-1v8-drv"; 1255 pinctrl-0 = <&sdmmc4_1v8_drv>; 1256 pinctrl-1 = <&sdmmc4_1v8_drv>; 1257 nvidia,pad-autocal-pull-up-offset-1v8 = <0x05>; 1258 nvidia,pad-autocal-pull-down-offset-1v8 = <0x05>; 1259 nvidia,default-tap = <0x8>; 1260 nvidia,default-trim = <0x0>; 1261 assigned-clocks = <&tegra_car TEGRA210_CLK_SDMMC4>, 1262 <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; 1263 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; 1264 nvidia,dqs-trim = <40>; 1265 mmc-hs400-1_8v; 1266 status = "disabled"; 1267 }; 1268 1269 usb@700d0000 { 1270 compatible = "nvidia,tegra210-xudc"; 1271 reg = <0x0 0x700d0000 0x0 0x8000>, 1272 <0x0 0x700d8000 0x0 0x1000>, 1273 <0x0 0x700d9000 0x0 0x1000>; 1274 reg-names = "base", "fpci", "ipfs"; 1275 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 1276 clocks = <&tegra_car TEGRA210_CLK_XUSB_DEV>, 1277 <&tegra_car TEGRA210_CLK_XUSB_SS>, 1278 <&tegra_car TEGRA210_CLK_XUSB_SSP_SRC>, 1279 <&tegra_car TEGRA210_CLK_XUSB_FS_SRC>, 1280 <&tegra_car TEGRA210_CLK_XUSB_HS_SRC>; 1281 clock-names = "dev", "ss", "ss_src", "fs_src", "hs_src"; 1282 power-domains = <&pd_xusbdev>, <&pd_xusbss>; 1283 power-domain-names = "dev", "ss"; 1284 nvidia,xusb-padctl = <&padctl>; 1285 status = "disabled"; 1286 }; 1287 1288 mipi: mipi@700e3000 { 1289 compatible = "nvidia,tegra210-mipi"; 1290 reg = <0x0 0x700e3000 0x0 0x100>; 1291 clocks = <&tegra_car TEGRA210_CLK_MIPI_CAL>; 1292 clock-names = "mipi-cal"; 1293 power-domains = <&pd_sor>; 1294 #nvidia,mipi-calibrate-cells = <1>; 1295 }; 1296 1297 dfll: clock@70110000 { 1298 compatible = "nvidia,tegra210-dfll"; 1299 reg = <0 0x70110000 0 0x100>, /* DFLL control */ 1300 <0 0x70110000 0 0x100>, /* I2C output control */ 1301 <0 0x70110100 0 0x100>, /* Integrated I2C controller */ 1302 <0 0x70110200 0 0x100>; /* Look-up table RAM */ 1303 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 1304 clocks = <&tegra_car TEGRA210_CLK_DFLL_SOC>, 1305 <&tegra_car TEGRA210_CLK_DFLL_REF>, 1306 <&tegra_car TEGRA210_CLK_I2C5>; 1307 clock-names = "soc", "ref", "i2c"; 1308 resets = <&tegra_car TEGRA210_RST_DFLL_DVCO>; 1309 reset-names = "dvco"; 1310 #clock-cells = <0>; 1311 clock-output-names = "dfllCPU_out"; 1312 status = "disabled"; 1313 }; 1314 1315 aconnect@702c0000 { 1316 compatible = "nvidia,tegra210-aconnect"; 1317 clocks = <&tegra_car TEGRA210_CLK_APE>, 1318 <&tegra_car TEGRA210_CLK_APB2APE>; 1319 clock-names = "ape", "apb2ape"; 1320 power-domains = <&pd_audio>; 1321 #address-cells = <1>; 1322 #size-cells = <1>; 1323 ranges = <0x702c0000 0x0 0x702c0000 0x00040000>; 1324 status = "disabled"; 1325 1326 adma: dma@702e2000 { 1327 compatible = "nvidia,tegra210-adma"; 1328 reg = <0x702e2000 0x2000>; 1329 interrupt-parent = <&agic>; 1330 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 1331 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 1332 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 1333 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 1334 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 1335 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 1336 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 1337 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 1338 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 1339 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 1340 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 1341 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 1342 <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, 1343 <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, 1344 <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, 1345 <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 1346 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 1347 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 1348 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 1349 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 1350 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 1351 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 1352 #dma-cells = <1>; 1353 clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>; 1354 clock-names = "d_audio"; 1355 status = "disabled"; 1356 }; 1357 1358 agic: interrupt-controller@702f9000 { 1359 compatible = "nvidia,tegra210-agic"; 1360 #interrupt-cells = <3>; 1361 interrupt-controller; 1362 reg = <0x702f9000 0x1000>, 1363 <0x702fa000 0x2000>; 1364 interrupts = <GIC_SPI 102 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 1365 clocks = <&tegra_car TEGRA210_CLK_APE>; 1366 clock-names = "clk"; 1367 status = "disabled"; 1368 }; 1369 }; 1370 1371 spi@70410000 { 1372 compatible = "nvidia,tegra210-qspi"; 1373 reg = <0x0 0x70410000 0x0 0x1000>; 1374 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 1375 #address-cells = <1>; 1376 #size-cells = <0>; 1377 clocks = <&tegra_car TEGRA210_CLK_QSPI>; 1378 clock-names = "qspi"; 1379 resets = <&tegra_car 211>; 1380 reset-names = "qspi"; 1381 dmas = <&apbdma 5>, <&apbdma 5>; 1382 dma-names = "rx", "tx"; 1383 status = "disabled"; 1384 }; 1385 1386 usb@7d000000 { 1387 compatible = "nvidia,tegra210-ehci", "nvidia,tegra30-ehci", "usb-ehci"; 1388 reg = <0x0 0x7d000000 0x0 0x4000>; 1389 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 1390 phy_type = "utmi"; 1391 clocks = <&tegra_car TEGRA210_CLK_USBD>; 1392 clock-names = "usb"; 1393 resets = <&tegra_car 22>; 1394 reset-names = "usb"; 1395 nvidia,phy = <&phy1>; 1396 status = "disabled"; 1397 }; 1398 1399 phy1: usb-phy@7d000000 { 1400 compatible = "nvidia,tegra210-usb-phy", "nvidia,tegra30-usb-phy"; 1401 reg = <0x0 0x7d000000 0x0 0x4000>, 1402 <0x0 0x7d000000 0x0 0x4000>; 1403 phy_type = "utmi"; 1404 clocks = <&tegra_car TEGRA210_CLK_USBD>, 1405 <&tegra_car TEGRA210_CLK_PLL_U>, 1406 <&tegra_car TEGRA210_CLK_USBD>; 1407 clock-names = "reg", "pll_u", "utmi-pads"; 1408 resets = <&tegra_car 22>, <&tegra_car 22>; 1409 reset-names = "usb", "utmi-pads"; 1410 nvidia,hssync-start-delay = <0>; 1411 nvidia,idle-wait-delay = <17>; 1412 nvidia,elastic-limit = <16>; 1413 nvidia,term-range-adj = <6>; 1414 nvidia,xcvr-setup = <9>; 1415 nvidia,xcvr-lsfslew = <0>; 1416 nvidia,xcvr-lsrslew = <3>; 1417 nvidia,hssquelch-level = <2>; 1418 nvidia,hsdiscon-level = <5>; 1419 nvidia,xcvr-hsslew = <12>; 1420 nvidia,has-utmi-pad-registers; 1421 status = "disabled"; 1422 }; 1423 1424 usb@7d004000 { 1425 compatible = "nvidia,tegra210-ehci", "nvidia,tegra30-ehci", "usb-ehci"; 1426 reg = <0x0 0x7d004000 0x0 0x4000>; 1427 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 1428 phy_type = "utmi"; 1429 clocks = <&tegra_car TEGRA210_CLK_USB2>; 1430 clock-names = "usb"; 1431 resets = <&tegra_car 58>; 1432 reset-names = "usb"; 1433 nvidia,phy = <&phy2>; 1434 status = "disabled"; 1435 }; 1436 1437 phy2: usb-phy@7d004000 { 1438 compatible = "nvidia,tegra210-usb-phy", "nvidia,tegra30-usb-phy"; 1439 reg = <0x0 0x7d004000 0x0 0x4000>, 1440 <0x0 0x7d000000 0x0 0x4000>; 1441 phy_type = "utmi"; 1442 clocks = <&tegra_car TEGRA210_CLK_USB2>, 1443 <&tegra_car TEGRA210_CLK_PLL_U>, 1444 <&tegra_car TEGRA210_CLK_USBD>; 1445 clock-names = "reg", "pll_u", "utmi-pads"; 1446 resets = <&tegra_car 58>, <&tegra_car 22>; 1447 reset-names = "usb", "utmi-pads"; 1448 nvidia,hssync-start-delay = <0>; 1449 nvidia,idle-wait-delay = <17>; 1450 nvidia,elastic-limit = <16>; 1451 nvidia,term-range-adj = <6>; 1452 nvidia,xcvr-setup = <9>; 1453 nvidia,xcvr-lsfslew = <0>; 1454 nvidia,xcvr-lsrslew = <3>; 1455 nvidia,hssquelch-level = <2>; 1456 nvidia,hsdiscon-level = <5>; 1457 nvidia,xcvr-hsslew = <12>; 1458 status = "disabled"; 1459 }; 1460 1461 cpus { 1462 #address-cells = <1>; 1463 #size-cells = <0>; 1464 1465 cpu@0 { 1466 device_type = "cpu"; 1467 compatible = "arm,cortex-a57"; 1468 reg = <0>; 1469 clocks = <&tegra_car TEGRA210_CLK_CCLK_G>, 1470 <&tegra_car TEGRA210_CLK_PLL_X>, 1471 <&tegra_car TEGRA210_CLK_PLL_P_OUT4>, 1472 <&dfll>; 1473 clock-names = "cpu_g", "pll_x", "pll_p", "dfll"; 1474 clock-latency = <300000>; 1475 cpu-idle-states = <&CPU_SLEEP>; 1476 next-level-cache = <&L2>; 1477 }; 1478 1479 cpu@1 { 1480 device_type = "cpu"; 1481 compatible = "arm,cortex-a57"; 1482 reg = <1>; 1483 cpu-idle-states = <&CPU_SLEEP>; 1484 next-level-cache = <&L2>; 1485 }; 1486 1487 cpu@2 { 1488 device_type = "cpu"; 1489 compatible = "arm,cortex-a57"; 1490 reg = <2>; 1491 cpu-idle-states = <&CPU_SLEEP>; 1492 next-level-cache = <&L2>; 1493 }; 1494 1495 cpu@3 { 1496 device_type = "cpu"; 1497 compatible = "arm,cortex-a57"; 1498 reg = <3>; 1499 cpu-idle-states = <&CPU_SLEEP>; 1500 next-level-cache = <&L2>; 1501 }; 1502 1503 idle-states { 1504 entry-method = "psci"; 1505 1506 CPU_SLEEP: cpu-sleep { 1507 compatible = "arm,idle-state"; 1508 arm,psci-suspend-param = <0x40000007>; 1509 entry-latency-us = <100>; 1510 exit-latency-us = <30>; 1511 min-residency-us = <1000>; 1512 wakeup-latency-us = <130>; 1513 idle-state-name = "cpu-sleep"; 1514 status = "disabled"; 1515 }; 1516 }; 1517 1518 L2: l2-cache { 1519 compatible = "cache"; 1520 }; 1521 }; 1522 1523 pmu { 1524 compatible = "arm,armv8-pmuv3"; 1525 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 1526 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 1527 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 1528 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; 1529 interrupt-affinity = <&{/cpus/cpu@0} &{/cpus/cpu@1} 1530 &{/cpus/cpu@2} &{/cpus/cpu@3}>; 1531 }; 1532 1533 timer { 1534 compatible = "arm,armv8-timer"; 1535 interrupts = <GIC_PPI 13 1536 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1537 <GIC_PPI 14 1538 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1539 <GIC_PPI 11 1540 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1541 <GIC_PPI 10 1542 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 1543 interrupt-parent = <&gic>; 1544 arm,no-tick-in-suspend; 1545 }; 1546 1547 soctherm: thermal-sensor@700e2000 { 1548 compatible = "nvidia,tegra210-soctherm"; 1549 reg = <0x0 0x700e2000 0x0 0x600>, /* SOC_THERM reg_base */ 1550 <0x0 0x60006000 0x0 0x400>; /* CAR reg_base */ 1551 reg-names = "soctherm-reg", "car-reg"; 1552 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, 1553 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 1554 interrupt-names = "thermal", "edp"; 1555 clocks = <&tegra_car TEGRA210_CLK_TSENSOR>, 1556 <&tegra_car TEGRA210_CLK_SOC_THERM>; 1557 clock-names = "tsensor", "soctherm"; 1558 resets = <&tegra_car 78>; 1559 reset-names = "soctherm"; 1560 #thermal-sensor-cells = <1>; 1561 1562 throttle-cfgs { 1563 throttle_heavy: heavy { 1564 nvidia,priority = <100>; 1565 nvidia,cpu-throt-percent = <85>; 1566 1567 #cooling-cells = <2>; 1568 }; 1569 }; 1570 }; 1571 1572 thermal-zones { 1573 cpu { 1574 polling-delay-passive = <1000>; 1575 polling-delay = <0>; 1576 1577 thermal-sensors = 1578 <&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>; 1579 1580 trips { 1581 cpu-shutdown-trip { 1582 temperature = <102500>; 1583 hysteresis = <0>; 1584 type = "critical"; 1585 }; 1586 1587 cpu_throttle_trip: throttle-trip { 1588 temperature = <98500>; 1589 hysteresis = <1000>; 1590 type = "hot"; 1591 }; 1592 }; 1593 1594 cooling-maps { 1595 map0 { 1596 trip = <&cpu_throttle_trip>; 1597 cooling-device = <&throttle_heavy 1 1>; 1598 }; 1599 }; 1600 }; 1601 1602 mem { 1603 polling-delay-passive = <0>; 1604 polling-delay = <0>; 1605 1606 thermal-sensors = 1607 <&soctherm TEGRA124_SOCTHERM_SENSOR_MEM>; 1608 1609 trips { 1610 dram_nominal: mem-nominal-trip { 1611 temperature = <50000>; 1612 hysteresis = <1000>; 1613 type = "passive"; 1614 }; 1615 1616 dram_throttle: mem-throttle-trip { 1617 temperature = <70000>; 1618 hysteresis = <1000>; 1619 type = "active"; 1620 }; 1621 1622 mem-shutdown-trip { 1623 temperature = <103000>; 1624 hysteresis = <0>; 1625 type = "critical"; 1626 }; 1627 }; 1628 1629 cooling-maps { 1630 dram-passive { 1631 cooling-device = <&emc 0 0>; 1632 trip = <&dram_nominal>; 1633 }; 1634 1635 dram-active { 1636 cooling-device = <&emc 1 1>; 1637 trip = <&dram_throttle>; 1638 }; 1639 }; 1640 }; 1641 1642 gpu { 1643 polling-delay-passive = <1000>; 1644 polling-delay = <0>; 1645 1646 thermal-sensors = 1647 <&soctherm TEGRA124_SOCTHERM_SENSOR_GPU>; 1648 1649 trips { 1650 gpu-shutdown-trip { 1651 temperature = <103000>; 1652 hysteresis = <0>; 1653 type = "critical"; 1654 }; 1655 1656 gpu_throttle_trip: throttle-trip { 1657 temperature = <100000>; 1658 hysteresis = <1000>; 1659 type = "hot"; 1660 }; 1661 }; 1662 1663 cooling-maps { 1664 map0 { 1665 trip = <&gpu_throttle_trip>; 1666 cooling-device = <&throttle_heavy 1 1>; 1667 }; 1668 }; 1669 }; 1670 1671 pllx { 1672 polling-delay-passive = <0>; 1673 polling-delay = <0>; 1674 1675 thermal-sensors = 1676 <&soctherm TEGRA124_SOCTHERM_SENSOR_PLLX>; 1677 1678 trips { 1679 pllx-shutdown-trip { 1680 temperature = <103000>; 1681 hysteresis = <0>; 1682 type = "critical"; 1683 }; 1684 }; 1685 1686 cooling-maps { 1687 /* 1688 * There are currently no cooling maps, 1689 * because there are no cooling devices. 1690 */ 1691 }; 1692 }; 1693 }; 1694}; 1695