1// SPDX-License-Identifier: GPL-2.0 2#include <dt-bindings/clock/tegra210-car.h> 3#include <dt-bindings/gpio/tegra-gpio.h> 4#include <dt-bindings/memory/tegra210-mc.h> 5#include <dt-bindings/pinctrl/pinctrl-tegra.h> 6#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 7#include <dt-bindings/reset/tegra210-car.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/thermal/tegra124-soctherm.h> 10#include <dt-bindings/soc/tegra-pmc.h> 11 12/ { 13 compatible = "nvidia,tegra210"; 14 interrupt-parent = <&lic>; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 18 pcie@1003000 { 19 compatible = "nvidia,tegra210-pcie"; 20 device_type = "pci"; 21 reg = <0x0 0x01003000 0x0 0x00000800>, /* PADS registers */ 22 <0x0 0x01003800 0x0 0x00000800>, /* AFI registers */ 23 <0x0 0x02000000 0x0 0x10000000>; /* configuration space */ 24 reg-names = "pads", "afi", "cs"; 25 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 26 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 27 interrupt-names = "intr", "msi"; 28 29 #interrupt-cells = <1>; 30 interrupt-map-mask = <0 0 0 0>; 31 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 32 33 bus-range = <0x00 0xff>; 34 #address-cells = <3>; 35 #size-cells = <2>; 36 37 ranges = <0x02000000 0 0x01000000 0x0 0x01000000 0 0x00001000>, /* port 0 configuration space */ 38 <0x02000000 0 0x01001000 0x0 0x01001000 0 0x00001000>, /* port 1 configuration space */ 39 <0x01000000 0 0x0 0x0 0x12000000 0 0x00010000>, /* downstream I/O (64 KiB) */ 40 <0x02000000 0 0x13000000 0x0 0x13000000 0 0x0d000000>, /* non-prefetchable memory (208 MiB) */ 41 <0x42000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */ 42 43 clocks = <&tegra_car TEGRA210_CLK_PCIE>, 44 <&tegra_car TEGRA210_CLK_AFI>, 45 <&tegra_car TEGRA210_CLK_PLL_E>, 46 <&tegra_car TEGRA210_CLK_CML0>; 47 clock-names = "pex", "afi", "pll_e", "cml"; 48 resets = <&tegra_car 70>, 49 <&tegra_car 72>, 50 <&tegra_car 74>; 51 reset-names = "pex", "afi", "pcie_x"; 52 53 pinctrl-names = "default", "idle"; 54 pinctrl-0 = <&pex_dpd_disable>; 55 pinctrl-1 = <&pex_dpd_enable>; 56 57 status = "disabled"; 58 59 pci@1,0 { 60 device_type = "pci"; 61 assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>; 62 reg = <0x000800 0 0 0 0>; 63 bus-range = <0x00 0xff>; 64 status = "disabled"; 65 66 #address-cells = <3>; 67 #size-cells = <2>; 68 ranges; 69 70 nvidia,num-lanes = <4>; 71 }; 72 73 pci@2,0 { 74 device_type = "pci"; 75 assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>; 76 reg = <0x001000 0 0 0 0>; 77 bus-range = <0x00 0xff>; 78 status = "disabled"; 79 80 #address-cells = <3>; 81 #size-cells = <2>; 82 ranges; 83 84 nvidia,num-lanes = <1>; 85 }; 86 }; 87 88 host1x@50000000 { 89 compatible = "nvidia,tegra210-host1x"; 90 reg = <0x0 0x50000000 0x0 0x00034000>; 91 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */ 92 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */ 93 interrupt-names = "syncpt", "host1x"; 94 clocks = <&tegra_car TEGRA210_CLK_HOST1X>; 95 clock-names = "host1x"; 96 resets = <&tegra_car 28>; 97 reset-names = "host1x"; 98 99 #address-cells = <2>; 100 #size-cells = <2>; 101 102 ranges = <0x0 0x54000000 0x0 0x54000000 0x0 0x01000000>; 103 104 iommus = <&mc TEGRA_SWGROUP_HC>; 105 106 dpaux1: dpaux@54040000 { 107 compatible = "nvidia,tegra210-dpaux"; 108 reg = <0x0 0x54040000 0x0 0x00040000>; 109 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 110 clocks = <&tegra_car TEGRA210_CLK_DPAUX1>, 111 <&tegra_car TEGRA210_CLK_PLL_DP>; 112 clock-names = "dpaux", "parent"; 113 resets = <&tegra_car 207>; 114 reset-names = "dpaux"; 115 power-domains = <&pd_sor>; 116 status = "disabled"; 117 118 state_dpaux1_aux: pinmux-aux { 119 groups = "dpaux-io"; 120 function = "aux"; 121 }; 122 123 state_dpaux1_i2c: pinmux-i2c { 124 groups = "dpaux-io"; 125 function = "i2c"; 126 }; 127 128 state_dpaux1_off: pinmux-off { 129 groups = "dpaux-io"; 130 function = "off"; 131 }; 132 133 i2c-bus { 134 #address-cells = <1>; 135 #size-cells = <0>; 136 }; 137 }; 138 139 vi@54080000 { 140 compatible = "nvidia,tegra210-vi"; 141 reg = <0x0 0x54080000 0x0 0x700>; 142 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 143 status = "disabled"; 144 assigned-clocks = <&tegra_car TEGRA210_CLK_VI>; 145 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; 146 147 clocks = <&tegra_car TEGRA210_CLK_VI>; 148 power-domains = <&pd_venc>; 149 150 #address-cells = <1>; 151 #size-cells = <1>; 152 153 ranges = <0x0 0x0 0x54080000 0x2000>; 154 155 csi@838 { 156 compatible = "nvidia,tegra210-csi"; 157 reg = <0x838 0x1300>; 158 status = "disabled"; 159 assigned-clocks = <&tegra_car TEGRA210_CLK_CILAB>, 160 <&tegra_car TEGRA210_CLK_CILCD>, 161 <&tegra_car TEGRA210_CLK_CILE>, 162 <&tegra_car TEGRA210_CLK_CSI_TPG>; 163 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_P>, 164 <&tegra_car TEGRA210_CLK_PLL_P>, 165 <&tegra_car TEGRA210_CLK_PLL_P>; 166 assigned-clock-rates = <102000000>, 167 <102000000>, 168 <102000000>, 169 <972000000>; 170 171 clocks = <&tegra_car TEGRA210_CLK_CSI>, 172 <&tegra_car TEGRA210_CLK_CILAB>, 173 <&tegra_car TEGRA210_CLK_CILCD>, 174 <&tegra_car TEGRA210_CLK_CILE>, 175 <&tegra_car TEGRA210_CLK_CSI_TPG>; 176 clock-names = "csi", "cilab", "cilcd", "cile", "csi_tpg"; 177 power-domains = <&pd_sor>; 178 }; 179 }; 180 181 tsec@54100000 { 182 compatible = "nvidia,tegra210-tsec"; 183 reg = <0x0 0x54100000 0x0 0x00040000>; 184 }; 185 186 dc@54200000 { 187 compatible = "nvidia,tegra210-dc"; 188 reg = <0x0 0x54200000 0x0 0x00040000>; 189 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 190 clocks = <&tegra_car TEGRA210_CLK_DISP1>; 191 clock-names = "dc"; 192 resets = <&tegra_car 27>; 193 reset-names = "dc"; 194 195 iommus = <&mc TEGRA_SWGROUP_DC>; 196 197 nvidia,head = <0>; 198 }; 199 200 dc@54240000 { 201 compatible = "nvidia,tegra210-dc"; 202 reg = <0x0 0x54240000 0x0 0x00040000>; 203 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 204 clocks = <&tegra_car TEGRA210_CLK_DISP2>; 205 clock-names = "dc"; 206 resets = <&tegra_car 26>; 207 reset-names = "dc"; 208 209 iommus = <&mc TEGRA_SWGROUP_DCB>; 210 211 nvidia,head = <1>; 212 }; 213 214 dsi@54300000 { 215 compatible = "nvidia,tegra210-dsi"; 216 reg = <0x0 0x54300000 0x0 0x00040000>; 217 clocks = <&tegra_car TEGRA210_CLK_DSIA>, 218 <&tegra_car TEGRA210_CLK_DSIALP>, 219 <&tegra_car TEGRA210_CLK_PLL_D_OUT0>; 220 clock-names = "dsi", "lp", "parent"; 221 resets = <&tegra_car 48>; 222 reset-names = "dsi"; 223 power-domains = <&pd_sor>; 224 nvidia,mipi-calibrate = <&mipi 0x0c0>; /* DSIA & DSIB pads */ 225 226 status = "disabled"; 227 228 #address-cells = <1>; 229 #size-cells = <0>; 230 }; 231 232 vic@54340000 { 233 compatible = "nvidia,tegra210-vic"; 234 reg = <0x0 0x54340000 0x0 0x00040000>; 235 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 236 clocks = <&tegra_car TEGRA210_CLK_VIC03>; 237 clock-names = "vic"; 238 resets = <&tegra_car 178>; 239 reset-names = "vic"; 240 241 iommus = <&mc TEGRA_SWGROUP_VIC>; 242 power-domains = <&pd_vic>; 243 }; 244 245 nvjpg@54380000 { 246 compatible = "nvidia,tegra210-nvjpg"; 247 reg = <0x0 0x54380000 0x0 0x00040000>; 248 status = "disabled"; 249 }; 250 251 dsi@54400000 { 252 compatible = "nvidia,tegra210-dsi"; 253 reg = <0x0 0x54400000 0x0 0x00040000>; 254 clocks = <&tegra_car TEGRA210_CLK_DSIB>, 255 <&tegra_car TEGRA210_CLK_DSIBLP>, 256 <&tegra_car TEGRA210_CLK_PLL_D_OUT0>; 257 clock-names = "dsi", "lp", "parent"; 258 resets = <&tegra_car 82>; 259 reset-names = "dsi"; 260 power-domains = <&pd_sor>; 261 nvidia,mipi-calibrate = <&mipi 0x300>; /* DSIC & DSID pads */ 262 263 status = "disabled"; 264 265 #address-cells = <1>; 266 #size-cells = <0>; 267 }; 268 269 nvdec@54480000 { 270 compatible = "nvidia,tegra210-nvdec"; 271 reg = <0x0 0x54480000 0x0 0x00040000>; 272 status = "disabled"; 273 }; 274 275 nvenc@544c0000 { 276 compatible = "nvidia,tegra210-nvenc"; 277 reg = <0x0 0x544c0000 0x0 0x00040000>; 278 status = "disabled"; 279 }; 280 281 tsec@54500000 { 282 compatible = "nvidia,tegra210-tsec"; 283 reg = <0x0 0x54500000 0x0 0x00040000>; 284 status = "disabled"; 285 }; 286 287 sor@54540000 { 288 compatible = "nvidia,tegra210-sor"; 289 reg = <0x0 0x54540000 0x0 0x00040000>; 290 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 291 clocks = <&tegra_car TEGRA210_CLK_SOR0>, 292 <&tegra_car TEGRA210_CLK_SOR0_OUT>, 293 <&tegra_car TEGRA210_CLK_PLL_D_OUT0>, 294 <&tegra_car TEGRA210_CLK_PLL_DP>, 295 <&tegra_car TEGRA210_CLK_SOR_SAFE>; 296 clock-names = "sor", "out", "parent", "dp", "safe"; 297 resets = <&tegra_car 182>; 298 reset-names = "sor"; 299 pinctrl-0 = <&state_dpaux_aux>; 300 pinctrl-1 = <&state_dpaux_i2c>; 301 pinctrl-2 = <&state_dpaux_off>; 302 pinctrl-names = "aux", "i2c", "off"; 303 power-domains = <&pd_sor>; 304 status = "disabled"; 305 }; 306 307 sor@54580000 { 308 compatible = "nvidia,tegra210-sor1"; 309 reg = <0x0 0x54580000 0x0 0x00040000>; 310 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 311 clocks = <&tegra_car TEGRA210_CLK_SOR1>, 312 <&tegra_car TEGRA210_CLK_SOR1_OUT>, 313 <&tegra_car TEGRA210_CLK_PLL_D2_OUT0>, 314 <&tegra_car TEGRA210_CLK_PLL_DP>, 315 <&tegra_car TEGRA210_CLK_SOR_SAFE>; 316 clock-names = "sor", "out", "parent", "dp", "safe"; 317 resets = <&tegra_car 183>; 318 reset-names = "sor"; 319 pinctrl-0 = <&state_dpaux1_aux>; 320 pinctrl-1 = <&state_dpaux1_i2c>; 321 pinctrl-2 = <&state_dpaux1_off>; 322 pinctrl-names = "aux", "i2c", "off"; 323 power-domains = <&pd_sor>; 324 status = "disabled"; 325 }; 326 327 dpaux: dpaux@545c0000 { 328 compatible = "nvidia,tegra210-dpaux"; 329 reg = <0x0 0x545c0000 0x0 0x00040000>; 330 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 331 clocks = <&tegra_car TEGRA210_CLK_DPAUX>, 332 <&tegra_car TEGRA210_CLK_PLL_DP>; 333 clock-names = "dpaux", "parent"; 334 resets = <&tegra_car 181>; 335 reset-names = "dpaux"; 336 power-domains = <&pd_sor>; 337 status = "disabled"; 338 339 state_dpaux_aux: pinmux-aux { 340 groups = "dpaux-io"; 341 function = "aux"; 342 }; 343 344 state_dpaux_i2c: pinmux-i2c { 345 groups = "dpaux-io"; 346 function = "i2c"; 347 }; 348 349 state_dpaux_off: pinmux-off { 350 groups = "dpaux-io"; 351 function = "off"; 352 }; 353 354 i2c-bus { 355 #address-cells = <1>; 356 #size-cells = <0>; 357 }; 358 }; 359 360 isp@54600000 { 361 compatible = "nvidia,tegra210-isp"; 362 reg = <0x0 0x54600000 0x0 0x00040000>; 363 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 364 clocks = <&tegra_car TEGRA210_CLK_ISPA>; 365 resets = <&tegra_car 23>; 366 reset-names = "isp"; 367 status = "disabled"; 368 }; 369 370 isp@54680000 { 371 compatible = "nvidia,tegra210-isp"; 372 reg = <0x0 0x54680000 0x0 0x00040000>; 373 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 374 clocks = <&tegra_car TEGRA210_CLK_ISPB>; 375 resets = <&tegra_car 3>; 376 reset-names = "isp"; 377 status = "disabled"; 378 }; 379 380 i2c@546c0000 { 381 compatible = "nvidia,tegra210-i2c-vi"; 382 reg = <0x0 0x546c0000 0x0 0x00040000>; 383 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 384 status = "disabled"; 385 }; 386 }; 387 388 gic: interrupt-controller@50041000 { 389 compatible = "arm,gic-400"; 390 #interrupt-cells = <3>; 391 interrupt-controller; 392 reg = <0x0 0x50041000 0x0 0x1000>, 393 <0x0 0x50042000 0x0 0x2000>, 394 <0x0 0x50044000 0x0 0x2000>, 395 <0x0 0x50046000 0x0 0x2000>; 396 interrupts = <GIC_PPI 9 397 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 398 interrupt-parent = <&gic>; 399 }; 400 401 gpu@57000000 { 402 compatible = "nvidia,gm20b"; 403 reg = <0x0 0x57000000 0x0 0x01000000>, 404 <0x0 0x58000000 0x0 0x01000000>; 405 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 406 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 407 interrupt-names = "stall", "nonstall"; 408 clocks = <&tegra_car TEGRA210_CLK_GPU>, 409 <&tegra_car TEGRA210_CLK_PLL_P_OUT5>, 410 <&tegra_car TEGRA210_CLK_PLL_G_REF>; 411 clock-names = "gpu", "pwr", "ref"; 412 resets = <&tegra_car 184>; 413 reset-names = "gpu"; 414 415 iommus = <&mc TEGRA_SWGROUP_GPU>; 416 417 status = "disabled"; 418 }; 419 420 lic: interrupt-controller@60004000 { 421 compatible = "nvidia,tegra210-ictlr"; 422 reg = <0x0 0x60004000 0x0 0x40>, /* primary controller */ 423 <0x0 0x60004100 0x0 0x40>, /* secondary controller */ 424 <0x0 0x60004200 0x0 0x40>, /* tertiary controller */ 425 <0x0 0x60004300 0x0 0x40>, /* quaternary controller */ 426 <0x0 0x60004400 0x0 0x40>, /* quinary controller */ 427 <0x0 0x60004500 0x0 0x40>; /* senary controller */ 428 interrupt-controller; 429 #interrupt-cells = <3>; 430 interrupt-parent = <&gic>; 431 }; 432 433 timer@60005000 { 434 compatible = "nvidia,tegra210-timer"; 435 reg = <0x0 0x60005000 0x0 0x400>; 436 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, 437 <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 438 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 439 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 440 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 441 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 442 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 443 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 444 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 445 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 446 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 447 <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>, 448 <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>, 449 <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; 450 clocks = <&tegra_car TEGRA210_CLK_TIMER>; 451 clock-names = "timer"; 452 }; 453 454 tegra_car: clock@60006000 { 455 compatible = "nvidia,tegra210-car"; 456 reg = <0x0 0x60006000 0x0 0x1000>; 457 #clock-cells = <1>; 458 #reset-cells = <1>; 459 }; 460 461 flow-controller@60007000 { 462 compatible = "nvidia,tegra210-flowctrl"; 463 reg = <0x0 0x60007000 0x0 0x1000>; 464 }; 465 466 gpio: gpio@6000d000 { 467 compatible = "nvidia,tegra210-gpio", "nvidia,tegra30-gpio"; 468 reg = <0x0 0x6000d000 0x0 0x1000>; 469 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 470 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 471 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 472 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 473 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 474 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 475 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 476 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 477 #gpio-cells = <2>; 478 gpio-controller; 479 #interrupt-cells = <2>; 480 interrupt-controller; 481 }; 482 483 apbdma: dma@60020000 { 484 compatible = "nvidia,tegra210-apbdma", "nvidia,tegra148-apbdma"; 485 reg = <0x0 0x60020000 0x0 0x1400>; 486 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 487 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 488 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 489 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 490 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 491 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 492 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 493 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 494 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 495 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 496 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 497 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 498 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 499 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 500 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 501 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 502 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 503 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 504 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 505 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 506 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 507 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 508 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 509 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 510 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 511 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 512 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 513 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 514 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 515 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 516 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 517 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 518 clocks = <&tegra_car TEGRA210_CLK_APBDMA>; 519 clock-names = "dma"; 520 resets = <&tegra_car 34>; 521 reset-names = "dma"; 522 #dma-cells = <1>; 523 }; 524 525 apbmisc@70000800 { 526 compatible = "nvidia,tegra210-apbmisc", "nvidia,tegra20-apbmisc"; 527 reg = <0x0 0x70000800 0x0 0x64>, /* Chip revision */ 528 <0x0 0x70000008 0x0 0x04>; /* Strapping options */ 529 }; 530 531 pinmux: pinmux@700008d4 { 532 compatible = "nvidia,tegra210-pinmux"; 533 reg = <0x0 0x700008d4 0x0 0x29c>, /* Pad control registers */ 534 <0x0 0x70003000 0x0 0x294>; /* Mux registers */ 535 sdmmc1_3v3_drv: sdmmc1-3v3-drv { 536 sdmmc1 { 537 nvidia,pins = "drive_sdmmc1"; 538 nvidia,pull-down-strength = <0x8>; 539 nvidia,pull-up-strength = <0x8>; 540 }; 541 }; 542 sdmmc1_1v8_drv: sdmmc1-1v8-drv { 543 sdmmc1 { 544 nvidia,pins = "drive_sdmmc1"; 545 nvidia,pull-down-strength = <0x4>; 546 nvidia,pull-up-strength = <0x3>; 547 }; 548 }; 549 sdmmc2_1v8_drv: sdmmc2-1v8-drv { 550 sdmmc2 { 551 nvidia,pins = "drive_sdmmc2"; 552 nvidia,pull-down-strength = <0x10>; 553 nvidia,pull-up-strength = <0x10>; 554 }; 555 }; 556 sdmmc3_3v3_drv: sdmmc3-3v3-drv { 557 sdmmc3 { 558 nvidia,pins = "drive_sdmmc3"; 559 nvidia,pull-down-strength = <0x8>; 560 nvidia,pull-up-strength = <0x8>; 561 }; 562 }; 563 sdmmc3_1v8_drv: sdmmc3-1v8-drv { 564 sdmmc3 { 565 nvidia,pins = "drive_sdmmc3"; 566 nvidia,pull-down-strength = <0x4>; 567 nvidia,pull-up-strength = <0x3>; 568 }; 569 }; 570 sdmmc4_1v8_drv: sdmmc4-1v8-drv { 571 sdmmc4 { 572 nvidia,pins = "drive_sdmmc4"; 573 nvidia,pull-down-strength = <0x10>; 574 nvidia,pull-up-strength = <0x10>; 575 }; 576 }; 577 }; 578 579 /* 580 * There are two serial driver i.e. 8250 based simple serial 581 * driver and APB DMA based serial driver for higher baudrate 582 * and performance. To enable the 8250 based driver, the compatible 583 * is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable 584 * the APB DMA based serial driver, the compatible is 585 * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart". 586 */ 587 uarta: serial@70006000 { 588 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; 589 reg = <0x0 0x70006000 0x0 0x40>; 590 reg-shift = <2>; 591 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 592 clocks = <&tegra_car TEGRA210_CLK_UARTA>; 593 clock-names = "serial"; 594 resets = <&tegra_car 6>; 595 reset-names = "serial"; 596 dmas = <&apbdma 8>, <&apbdma 8>; 597 dma-names = "rx", "tx"; 598 status = "disabled"; 599 }; 600 601 uartb: serial@70006040 { 602 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; 603 reg = <0x0 0x70006040 0x0 0x40>; 604 reg-shift = <2>; 605 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 606 clocks = <&tegra_car TEGRA210_CLK_UARTB>; 607 clock-names = "serial"; 608 resets = <&tegra_car 7>; 609 reset-names = "serial"; 610 dmas = <&apbdma 9>, <&apbdma 9>; 611 dma-names = "rx", "tx"; 612 status = "disabled"; 613 }; 614 615 uartc: serial@70006200 { 616 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; 617 reg = <0x0 0x70006200 0x0 0x40>; 618 reg-shift = <2>; 619 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 620 clocks = <&tegra_car TEGRA210_CLK_UARTC>; 621 clock-names = "serial"; 622 resets = <&tegra_car 55>; 623 reset-names = "serial"; 624 dmas = <&apbdma 10>, <&apbdma 10>; 625 dma-names = "rx", "tx"; 626 status = "disabled"; 627 }; 628 629 uartd: serial@70006300 { 630 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; 631 reg = <0x0 0x70006300 0x0 0x40>; 632 reg-shift = <2>; 633 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 634 clocks = <&tegra_car TEGRA210_CLK_UARTD>; 635 clock-names = "serial"; 636 resets = <&tegra_car 65>; 637 reset-names = "serial"; 638 dmas = <&apbdma 19>, <&apbdma 19>; 639 dma-names = "rx", "tx"; 640 status = "disabled"; 641 }; 642 643 pwm: pwm@7000a000 { 644 compatible = "nvidia,tegra210-pwm", "nvidia,tegra20-pwm"; 645 reg = <0x0 0x7000a000 0x0 0x100>; 646 #pwm-cells = <2>; 647 clocks = <&tegra_car TEGRA210_CLK_PWM>; 648 clock-names = "pwm"; 649 resets = <&tegra_car 17>; 650 reset-names = "pwm"; 651 status = "disabled"; 652 }; 653 654 i2c@7000c000 { 655 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; 656 reg = <0x0 0x7000c000 0x0 0x100>; 657 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 658 #address-cells = <1>; 659 #size-cells = <0>; 660 clocks = <&tegra_car TEGRA210_CLK_I2C1>; 661 clock-names = "div-clk"; 662 resets = <&tegra_car 12>; 663 reset-names = "i2c"; 664 dmas = <&apbdma 21>, <&apbdma 21>; 665 dma-names = "rx", "tx"; 666 status = "disabled"; 667 }; 668 669 i2c@7000c400 { 670 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; 671 reg = <0x0 0x7000c400 0x0 0x100>; 672 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 673 #address-cells = <1>; 674 #size-cells = <0>; 675 clocks = <&tegra_car TEGRA210_CLK_I2C2>; 676 clock-names = "div-clk"; 677 resets = <&tegra_car 54>; 678 reset-names = "i2c"; 679 dmas = <&apbdma 22>, <&apbdma 22>; 680 dma-names = "rx", "tx"; 681 status = "disabled"; 682 }; 683 684 i2c@7000c500 { 685 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; 686 reg = <0x0 0x7000c500 0x0 0x100>; 687 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 688 #address-cells = <1>; 689 #size-cells = <0>; 690 clocks = <&tegra_car TEGRA210_CLK_I2C3>; 691 clock-names = "div-clk"; 692 resets = <&tegra_car 67>; 693 reset-names = "i2c"; 694 dmas = <&apbdma 23>, <&apbdma 23>; 695 dma-names = "rx", "tx"; 696 status = "disabled"; 697 }; 698 699 i2c@7000c700 { 700 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; 701 reg = <0x0 0x7000c700 0x0 0x100>; 702 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 703 #address-cells = <1>; 704 #size-cells = <0>; 705 clocks = <&tegra_car TEGRA210_CLK_I2C4>; 706 clock-names = "div-clk"; 707 resets = <&tegra_car 103>; 708 reset-names = "i2c"; 709 dmas = <&apbdma 26>, <&apbdma 26>; 710 dma-names = "rx", "tx"; 711 pinctrl-0 = <&state_dpaux1_i2c>; 712 pinctrl-1 = <&state_dpaux1_off>; 713 pinctrl-names = "default", "idle"; 714 status = "disabled"; 715 }; 716 717 i2c@7000d000 { 718 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; 719 reg = <0x0 0x7000d000 0x0 0x100>; 720 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 721 #address-cells = <1>; 722 #size-cells = <0>; 723 clocks = <&tegra_car TEGRA210_CLK_I2C5>; 724 clock-names = "div-clk"; 725 resets = <&tegra_car 47>; 726 reset-names = "i2c"; 727 dmas = <&apbdma 24>, <&apbdma 24>; 728 dma-names = "rx", "tx"; 729 status = "disabled"; 730 }; 731 732 i2c@7000d100 { 733 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; 734 reg = <0x0 0x7000d100 0x0 0x100>; 735 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 736 #address-cells = <1>; 737 #size-cells = <0>; 738 clocks = <&tegra_car TEGRA210_CLK_I2C6>; 739 clock-names = "div-clk"; 740 resets = <&tegra_car 166>; 741 reset-names = "i2c"; 742 dmas = <&apbdma 30>, <&apbdma 30>; 743 dma-names = "rx", "tx"; 744 pinctrl-0 = <&state_dpaux_i2c>; 745 pinctrl-1 = <&state_dpaux_off>; 746 pinctrl-names = "default", "idle"; 747 status = "disabled"; 748 }; 749 750 spi@7000d400 { 751 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 752 reg = <0x0 0x7000d400 0x0 0x200>; 753 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 754 #address-cells = <1>; 755 #size-cells = <0>; 756 clocks = <&tegra_car TEGRA210_CLK_SBC1>; 757 clock-names = "spi"; 758 resets = <&tegra_car 41>; 759 reset-names = "spi"; 760 dmas = <&apbdma 15>, <&apbdma 15>; 761 dma-names = "rx", "tx"; 762 status = "disabled"; 763 }; 764 765 spi@7000d600 { 766 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 767 reg = <0x0 0x7000d600 0x0 0x200>; 768 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 769 #address-cells = <1>; 770 #size-cells = <0>; 771 clocks = <&tegra_car TEGRA210_CLK_SBC2>; 772 clock-names = "spi"; 773 resets = <&tegra_car 44>; 774 reset-names = "spi"; 775 dmas = <&apbdma 16>, <&apbdma 16>; 776 dma-names = "rx", "tx"; 777 status = "disabled"; 778 }; 779 780 spi@7000d800 { 781 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 782 reg = <0x0 0x7000d800 0x0 0x200>; 783 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 784 #address-cells = <1>; 785 #size-cells = <0>; 786 clocks = <&tegra_car TEGRA210_CLK_SBC3>; 787 clock-names = "spi"; 788 resets = <&tegra_car 46>; 789 reset-names = "spi"; 790 dmas = <&apbdma 17>, <&apbdma 17>; 791 dma-names = "rx", "tx"; 792 status = "disabled"; 793 }; 794 795 spi@7000da00 { 796 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 797 reg = <0x0 0x7000da00 0x0 0x200>; 798 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 799 #address-cells = <1>; 800 #size-cells = <0>; 801 clocks = <&tegra_car TEGRA210_CLK_SBC4>; 802 clock-names = "spi"; 803 resets = <&tegra_car 68>; 804 reset-names = "spi"; 805 dmas = <&apbdma 18>, <&apbdma 18>; 806 dma-names = "rx", "tx"; 807 status = "disabled"; 808 }; 809 810 rtc@7000e000 { 811 compatible = "nvidia,tegra210-rtc", "nvidia,tegra20-rtc"; 812 reg = <0x0 0x7000e000 0x0 0x100>; 813 interrupts = <16 IRQ_TYPE_LEVEL_HIGH>; 814 interrupt-parent = <&tegra_pmc>; 815 clocks = <&tegra_car TEGRA210_CLK_RTC>; 816 clock-names = "rtc"; 817 }; 818 819 tegra_pmc: pmc@7000e400 { 820 compatible = "nvidia,tegra210-pmc"; 821 reg = <0x0 0x7000e400 0x0 0x400>; 822 clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>; 823 clock-names = "pclk", "clk32k_in"; 824 #clock-cells = <1>; 825 #interrupt-cells = <2>; 826 interrupt-controller; 827 828 powergates { 829 pd_audio: aud { 830 clocks = <&tegra_car TEGRA210_CLK_APE>, 831 <&tegra_car TEGRA210_CLK_APB2APE>; 832 resets = <&tegra_car 198>; 833 #power-domain-cells = <0>; 834 }; 835 836 pd_sor: sor { 837 clocks = <&tegra_car TEGRA210_CLK_SOR0>, 838 <&tegra_car TEGRA210_CLK_SOR1>, 839 <&tegra_car TEGRA210_CLK_CILAB>, 840 <&tegra_car TEGRA210_CLK_CILCD>, 841 <&tegra_car TEGRA210_CLK_CILE>, 842 <&tegra_car TEGRA210_CLK_DSIA>, 843 <&tegra_car TEGRA210_CLK_DSIB>, 844 <&tegra_car TEGRA210_CLK_DPAUX>, 845 <&tegra_car TEGRA210_CLK_DPAUX1>, 846 <&tegra_car TEGRA210_CLK_MIPI_CAL>; 847 resets = <&tegra_car TEGRA210_CLK_SOR0>, 848 <&tegra_car TEGRA210_CLK_SOR1>, 849 <&tegra_car TEGRA210_CLK_DSIA>, 850 <&tegra_car TEGRA210_CLK_DSIB>, 851 <&tegra_car TEGRA210_CLK_DPAUX>, 852 <&tegra_car TEGRA210_CLK_DPAUX1>, 853 <&tegra_car TEGRA210_CLK_MIPI_CAL>; 854 #power-domain-cells = <0>; 855 }; 856 857 pd_xusbss: xusba { 858 clocks = <&tegra_car TEGRA210_CLK_XUSB_SS>; 859 resets = <&tegra_car TEGRA210_CLK_XUSB_SS>; 860 #power-domain-cells = <0>; 861 }; 862 863 pd_xusbdev: xusbb { 864 clocks = <&tegra_car TEGRA210_CLK_XUSB_DEV>; 865 resets = <&tegra_car 95>; 866 #power-domain-cells = <0>; 867 }; 868 869 pd_xusbhost: xusbc { 870 clocks = <&tegra_car TEGRA210_CLK_XUSB_HOST>; 871 resets = <&tegra_car TEGRA210_CLK_XUSB_HOST>; 872 #power-domain-cells = <0>; 873 }; 874 875 pd_vic: vic { 876 clocks = <&tegra_car TEGRA210_CLK_VIC03>; 877 clock-names = "vic"; 878 resets = <&tegra_car 178>; 879 reset-names = "vic"; 880 #power-domain-cells = <0>; 881 }; 882 883 pd_venc: venc { 884 clocks = <&tegra_car TEGRA210_CLK_VI>, 885 <&tegra_car TEGRA210_CLK_CSI>; 886 resets = <&mc TEGRA210_MC_RESET_VI>, 887 <&tegra_car 20>, 888 <&tegra_car 52>; 889 #power-domain-cells = <0>; 890 }; 891 }; 892 893 sdmmc1_3v3: sdmmc1-3v3 { 894 pins = "sdmmc1"; 895 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 896 }; 897 898 sdmmc1_1v8: sdmmc1-1v8 { 899 pins = "sdmmc1"; 900 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 901 }; 902 903 sdmmc3_3v3: sdmmc3-3v3 { 904 pins = "sdmmc3"; 905 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 906 }; 907 908 sdmmc3_1v8: sdmmc3-1v8 { 909 pins = "sdmmc3"; 910 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 911 }; 912 913 pex_dpd_disable: pex_en { 914 pex-dpd-disable { 915 pins = "pex-bias", "pex-clk1", "pex-clk2"; 916 low-power-disable; 917 }; 918 }; 919 920 pex_dpd_enable: pex_dis { 921 pex-dpd-enable { 922 pins = "pex-bias", "pex-clk1", "pex-clk2"; 923 low-power-enable; 924 }; 925 }; 926 }; 927 928 fuse@7000f800 { 929 compatible = "nvidia,tegra210-efuse"; 930 reg = <0x0 0x7000f800 0x0 0x400>; 931 clocks = <&tegra_car TEGRA210_CLK_FUSE>; 932 clock-names = "fuse"; 933 resets = <&tegra_car 39>; 934 reset-names = "fuse"; 935 }; 936 937 mc: memory-controller@70019000 { 938 compatible = "nvidia,tegra210-mc"; 939 reg = <0x0 0x70019000 0x0 0x1000>; 940 clocks = <&tegra_car TEGRA210_CLK_MC>; 941 clock-names = "mc"; 942 943 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 944 945 #iommu-cells = <1>; 946 #reset-cells = <1>; 947 }; 948 949 emc: external-memory-controller@7001b000 { 950 compatible = "nvidia,tegra210-emc"; 951 reg = <0x0 0x7001b000 0x0 0x1000>, 952 <0x0 0x7001e000 0x0 0x1000>, 953 <0x0 0x7001f000 0x0 0x1000>; 954 clocks = <&tegra_car TEGRA210_CLK_EMC>; 955 clock-names = "emc"; 956 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 957 nvidia,memory-controller = <&mc>; 958 #cooling-cells = <2>; 959 }; 960 961 sata@70020000 { 962 compatible = "nvidia,tegra210-ahci"; 963 reg = <0x0 0x70027000 0x0 0x2000>, /* AHCI */ 964 <0x0 0x70020000 0x0 0x7000>, /* SATA */ 965 <0x0 0x70001100 0x0 0x1000>; /* SATA AUX */ 966 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 967 clocks = <&tegra_car TEGRA210_CLK_SATA>, 968 <&tegra_car TEGRA210_CLK_SATA_OOB>; 969 clock-names = "sata", "sata-oob"; 970 resets = <&tegra_car 124>, 971 <&tegra_car 123>, 972 <&tegra_car 129>; 973 reset-names = "sata", "sata-oob", "sata-cold"; 974 status = "disabled"; 975 }; 976 977 hda@70030000 { 978 compatible = "nvidia,tegra210-hda", "nvidia,tegra30-hda"; 979 reg = <0x0 0x70030000 0x0 0x10000>; 980 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 981 clocks = <&tegra_car TEGRA210_CLK_HDA>, 982 <&tegra_car TEGRA210_CLK_HDA2HDMI>, 983 <&tegra_car TEGRA210_CLK_HDA2CODEC_2X>; 984 clock-names = "hda", "hda2hdmi", "hda2codec_2x"; 985 resets = <&tegra_car 125>, /* hda */ 986 <&tegra_car 128>, /* hda2hdmi */ 987 <&tegra_car 111>; /* hda2codec_2x */ 988 reset-names = "hda", "hda2hdmi", "hda2codec_2x"; 989 status = "disabled"; 990 }; 991 992 usb@70090000 { 993 compatible = "nvidia,tegra210-xusb"; 994 reg = <0x0 0x70090000 0x0 0x8000>, 995 <0x0 0x70098000 0x0 0x1000>, 996 <0x0 0x70099000 0x0 0x1000>; 997 reg-names = "hcd", "fpci", "ipfs"; 998 999 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 1000 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 1001 1002 clocks = <&tegra_car TEGRA210_CLK_XUSB_HOST>, 1003 <&tegra_car TEGRA210_CLK_XUSB_HOST_SRC>, 1004 <&tegra_car TEGRA210_CLK_XUSB_FALCON_SRC>, 1005 <&tegra_car TEGRA210_CLK_XUSB_SS>, 1006 <&tegra_car TEGRA210_CLK_XUSB_SS_SRC>, 1007 <&tegra_car TEGRA210_CLK_XUSB_SS_DIV2>, 1008 <&tegra_car TEGRA210_CLK_XUSB_HS_SRC>, 1009 <&tegra_car TEGRA210_CLK_XUSB_FS_SRC>, 1010 <&tegra_car TEGRA210_CLK_PLL_U_480M>, 1011 <&tegra_car TEGRA210_CLK_CLK_M>, 1012 <&tegra_car TEGRA210_CLK_PLL_E>; 1013 clock-names = "xusb_host", "xusb_host_src", 1014 "xusb_falcon_src", "xusb_ss", 1015 "xusb_ss_src", "xusb_ss_div2", 1016 "xusb_hs_src", "xusb_fs_src", 1017 "pll_u_480m", "clk_m", "pll_e"; 1018 resets = <&tegra_car 89>, <&tegra_car 156>, 1019 <&tegra_car 143>; 1020 reset-names = "xusb_host", "xusb_ss", "xusb_src"; 1021 power-domains = <&pd_xusbhost>, <&pd_xusbss>; 1022 power-domain-names = "xusb_host", "xusb_ss"; 1023 1024 nvidia,xusb-padctl = <&padctl>; 1025 1026 status = "disabled"; 1027 }; 1028 1029 padctl: padctl@7009f000 { 1030 compatible = "nvidia,tegra210-xusb-padctl"; 1031 reg = <0x0 0x7009f000 0x0 0x1000>; 1032 resets = <&tegra_car 142>; 1033 reset-names = "padctl"; 1034 1035 status = "disabled"; 1036 1037 pads { 1038 usb2 { 1039 clocks = <&tegra_car TEGRA210_CLK_USB2_TRK>; 1040 clock-names = "trk"; 1041 status = "disabled"; 1042 1043 lanes { 1044 usb2-0 { 1045 status = "disabled"; 1046 #phy-cells = <0>; 1047 }; 1048 1049 usb2-1 { 1050 status = "disabled"; 1051 #phy-cells = <0>; 1052 }; 1053 1054 usb2-2 { 1055 status = "disabled"; 1056 #phy-cells = <0>; 1057 }; 1058 1059 usb2-3 { 1060 status = "disabled"; 1061 #phy-cells = <0>; 1062 }; 1063 }; 1064 }; 1065 1066 hsic { 1067 clocks = <&tegra_car TEGRA210_CLK_HSIC_TRK>; 1068 clock-names = "trk"; 1069 status = "disabled"; 1070 1071 lanes { 1072 hsic-0 { 1073 status = "disabled"; 1074 #phy-cells = <0>; 1075 }; 1076 1077 hsic-1 { 1078 status = "disabled"; 1079 #phy-cells = <0>; 1080 }; 1081 }; 1082 }; 1083 1084 pcie { 1085 clocks = <&tegra_car TEGRA210_CLK_PLL_E>; 1086 clock-names = "pll"; 1087 resets = <&tegra_car 205>; 1088 reset-names = "phy"; 1089 status = "disabled"; 1090 1091 lanes { 1092 pcie-0 { 1093 status = "disabled"; 1094 #phy-cells = <0>; 1095 }; 1096 1097 pcie-1 { 1098 status = "disabled"; 1099 #phy-cells = <0>; 1100 }; 1101 1102 pcie-2 { 1103 status = "disabled"; 1104 #phy-cells = <0>; 1105 }; 1106 1107 pcie-3 { 1108 status = "disabled"; 1109 #phy-cells = <0>; 1110 }; 1111 1112 pcie-4 { 1113 status = "disabled"; 1114 #phy-cells = <0>; 1115 }; 1116 1117 pcie-5 { 1118 status = "disabled"; 1119 #phy-cells = <0>; 1120 }; 1121 1122 pcie-6 { 1123 status = "disabled"; 1124 #phy-cells = <0>; 1125 }; 1126 }; 1127 }; 1128 1129 sata { 1130 clocks = <&tegra_car TEGRA210_CLK_PLL_E>; 1131 clock-names = "pll"; 1132 resets = <&tegra_car 204>; 1133 reset-names = "phy"; 1134 status = "disabled"; 1135 1136 lanes { 1137 sata-0 { 1138 status = "disabled"; 1139 #phy-cells = <0>; 1140 }; 1141 }; 1142 }; 1143 }; 1144 1145 ports { 1146 usb2-0 { 1147 status = "disabled"; 1148 }; 1149 1150 usb2-1 { 1151 status = "disabled"; 1152 }; 1153 1154 usb2-2 { 1155 status = "disabled"; 1156 }; 1157 1158 usb2-3 { 1159 status = "disabled"; 1160 }; 1161 1162 hsic-0 { 1163 status = "disabled"; 1164 }; 1165 1166 usb3-0 { 1167 status = "disabled"; 1168 }; 1169 1170 usb3-1 { 1171 status = "disabled"; 1172 }; 1173 1174 usb3-2 { 1175 status = "disabled"; 1176 }; 1177 1178 usb3-3 { 1179 status = "disabled"; 1180 }; 1181 }; 1182 }; 1183 1184 mmc@700b0000 { 1185 compatible = "nvidia,tegra210-sdhci"; 1186 reg = <0x0 0x700b0000 0x0 0x200>; 1187 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1188 clocks = <&tegra_car TEGRA210_CLK_SDMMC1>; 1189 clock-names = "sdhci"; 1190 resets = <&tegra_car 14>; 1191 reset-names = "sdhci"; 1192 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8", 1193 "sdmmc-3v3-drv", "sdmmc-1v8-drv"; 1194 pinctrl-0 = <&sdmmc1_3v3>; 1195 pinctrl-1 = <&sdmmc1_1v8>; 1196 pinctrl-2 = <&sdmmc1_3v3_drv>; 1197 pinctrl-3 = <&sdmmc1_1v8_drv>; 1198 nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>; 1199 nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>; 1200 nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>; 1201 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7b>; 1202 nvidia,default-tap = <0x2>; 1203 nvidia,default-trim = <0x4>; 1204 assigned-clocks = <&tegra_car TEGRA210_CLK_SDMMC4>, 1205 <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>, 1206 <&tegra_car TEGRA210_CLK_PLL_C4>; 1207 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; 1208 assigned-clock-rates = <200000000>, <1000000000>, <1000000000>; 1209 status = "disabled"; 1210 }; 1211 1212 mmc@700b0200 { 1213 compatible = "nvidia,tegra210-sdhci"; 1214 reg = <0x0 0x700b0200 0x0 0x200>; 1215 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 1216 clocks = <&tegra_car TEGRA210_CLK_SDMMC2>; 1217 clock-names = "sdhci"; 1218 resets = <&tegra_car 9>; 1219 reset-names = "sdhci"; 1220 pinctrl-names = "sdmmc-1v8-drv"; 1221 pinctrl-0 = <&sdmmc2_1v8_drv>; 1222 nvidia,pad-autocal-pull-up-offset-1v8 = <0x05>; 1223 nvidia,pad-autocal-pull-down-offset-1v8 = <0x05>; 1224 nvidia,default-tap = <0x8>; 1225 nvidia,default-trim = <0x0>; 1226 status = "disabled"; 1227 }; 1228 1229 mmc@700b0400 { 1230 compatible = "nvidia,tegra210-sdhci"; 1231 reg = <0x0 0x700b0400 0x0 0x200>; 1232 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 1233 clocks = <&tegra_car TEGRA210_CLK_SDMMC3>; 1234 clock-names = "sdhci"; 1235 resets = <&tegra_car 69>; 1236 reset-names = "sdhci"; 1237 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8", 1238 "sdmmc-3v3-drv", "sdmmc-1v8-drv"; 1239 pinctrl-0 = <&sdmmc3_3v3>; 1240 pinctrl-1 = <&sdmmc3_1v8>; 1241 pinctrl-2 = <&sdmmc3_3v3_drv>; 1242 pinctrl-3 = <&sdmmc3_1v8_drv>; 1243 nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>; 1244 nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>; 1245 nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>; 1246 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7b>; 1247 nvidia,default-tap = <0x3>; 1248 nvidia,default-trim = <0x3>; 1249 status = "disabled"; 1250 }; 1251 1252 mmc@700b0600 { 1253 compatible = "nvidia,tegra210-sdhci"; 1254 reg = <0x0 0x700b0600 0x0 0x200>; 1255 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 1256 clocks = <&tegra_car TEGRA210_CLK_SDMMC4>; 1257 clock-names = "sdhci"; 1258 resets = <&tegra_car 15>; 1259 reset-names = "sdhci"; 1260 pinctrl-names = "sdmmc-3v3-drv", "sdmmc-1v8-drv"; 1261 pinctrl-0 = <&sdmmc4_1v8_drv>; 1262 pinctrl-1 = <&sdmmc4_1v8_drv>; 1263 nvidia,pad-autocal-pull-up-offset-1v8 = <0x05>; 1264 nvidia,pad-autocal-pull-down-offset-1v8 = <0x05>; 1265 nvidia,default-tap = <0x8>; 1266 nvidia,default-trim = <0x0>; 1267 assigned-clocks = <&tegra_car TEGRA210_CLK_SDMMC4>, 1268 <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; 1269 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; 1270 nvidia,dqs-trim = <40>; 1271 mmc-hs400-1_8v; 1272 status = "disabled"; 1273 }; 1274 1275 usb@700d0000 { 1276 compatible = "nvidia,tegra210-xudc"; 1277 reg = <0x0 0x700d0000 0x0 0x8000>, 1278 <0x0 0x700d8000 0x0 0x1000>, 1279 <0x0 0x700d9000 0x0 0x1000>; 1280 reg-names = "base", "fpci", "ipfs"; 1281 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 1282 clocks = <&tegra_car TEGRA210_CLK_XUSB_DEV>, 1283 <&tegra_car TEGRA210_CLK_XUSB_SS>, 1284 <&tegra_car TEGRA210_CLK_XUSB_SSP_SRC>, 1285 <&tegra_car TEGRA210_CLK_XUSB_FS_SRC>, 1286 <&tegra_car TEGRA210_CLK_XUSB_HS_SRC>; 1287 clock-names = "dev", "ss", "ss_src", "fs_src", "hs_src"; 1288 power-domains = <&pd_xusbdev>, <&pd_xusbss>; 1289 power-domain-names = "dev", "ss"; 1290 nvidia,xusb-padctl = <&padctl>; 1291 status = "disabled"; 1292 }; 1293 1294 mipi: mipi@700e3000 { 1295 compatible = "nvidia,tegra210-mipi"; 1296 reg = <0x0 0x700e3000 0x0 0x100>; 1297 clocks = <&tegra_car TEGRA210_CLK_MIPI_CAL>; 1298 clock-names = "mipi-cal"; 1299 power-domains = <&pd_sor>; 1300 #nvidia,mipi-calibrate-cells = <1>; 1301 }; 1302 1303 dfll: clock@70110000 { 1304 compatible = "nvidia,tegra210-dfll"; 1305 reg = <0 0x70110000 0 0x100>, /* DFLL control */ 1306 <0 0x70110000 0 0x100>, /* I2C output control */ 1307 <0 0x70110100 0 0x100>, /* Integrated I2C controller */ 1308 <0 0x70110200 0 0x100>; /* Look-up table RAM */ 1309 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 1310 clocks = <&tegra_car TEGRA210_CLK_DFLL_SOC>, 1311 <&tegra_car TEGRA210_CLK_DFLL_REF>, 1312 <&tegra_car TEGRA210_CLK_I2C5>; 1313 clock-names = "soc", "ref", "i2c"; 1314 resets = <&tegra_car TEGRA210_RST_DFLL_DVCO>; 1315 reset-names = "dvco"; 1316 #clock-cells = <0>; 1317 clock-output-names = "dfllCPU_out"; 1318 status = "disabled"; 1319 }; 1320 1321 aconnect@702c0000 { 1322 compatible = "nvidia,tegra210-aconnect"; 1323 clocks = <&tegra_car TEGRA210_CLK_APE>, 1324 <&tegra_car TEGRA210_CLK_APB2APE>; 1325 clock-names = "ape", "apb2ape"; 1326 power-domains = <&pd_audio>; 1327 #address-cells = <1>; 1328 #size-cells = <1>; 1329 ranges = <0x702c0000 0x0 0x702c0000 0x00040000>; 1330 status = "disabled"; 1331 1332 adma: dma@702e2000 { 1333 compatible = "nvidia,tegra210-adma"; 1334 reg = <0x702e2000 0x2000>; 1335 interrupt-parent = <&agic>; 1336 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 1337 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 1338 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 1339 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 1340 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 1341 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 1342 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 1343 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 1344 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 1345 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 1346 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 1347 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 1348 <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, 1349 <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, 1350 <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, 1351 <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 1352 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 1353 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 1354 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 1355 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 1356 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 1357 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 1358 #dma-cells = <1>; 1359 clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>; 1360 clock-names = "d_audio"; 1361 status = "disabled"; 1362 }; 1363 1364 agic: interrupt-controller@702f9000 { 1365 compatible = "nvidia,tegra210-agic"; 1366 #interrupt-cells = <3>; 1367 interrupt-controller; 1368 reg = <0x702f9000 0x1000>, 1369 <0x702fa000 0x2000>; 1370 interrupts = <GIC_SPI 102 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 1371 clocks = <&tegra_car TEGRA210_CLK_APE>; 1372 clock-names = "clk"; 1373 status = "disabled"; 1374 }; 1375 }; 1376 1377 spi@70410000 { 1378 compatible = "nvidia,tegra210-qspi"; 1379 reg = <0x0 0x70410000 0x0 0x1000>; 1380 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 1381 #address-cells = <1>; 1382 #size-cells = <0>; 1383 clocks = <&tegra_car TEGRA210_CLK_QSPI>; 1384 clock-names = "qspi"; 1385 resets = <&tegra_car 211>; 1386 reset-names = "qspi"; 1387 dmas = <&apbdma 5>, <&apbdma 5>; 1388 dma-names = "rx", "tx"; 1389 status = "disabled"; 1390 }; 1391 1392 usb@7d000000 { 1393 compatible = "nvidia,tegra210-ehci", "nvidia,tegra30-ehci", "usb-ehci"; 1394 reg = <0x0 0x7d000000 0x0 0x4000>; 1395 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 1396 phy_type = "utmi"; 1397 clocks = <&tegra_car TEGRA210_CLK_USBD>; 1398 clock-names = "usb"; 1399 resets = <&tegra_car 22>; 1400 reset-names = "usb"; 1401 nvidia,phy = <&phy1>; 1402 status = "disabled"; 1403 }; 1404 1405 phy1: usb-phy@7d000000 { 1406 compatible = "nvidia,tegra210-usb-phy", "nvidia,tegra30-usb-phy"; 1407 reg = <0x0 0x7d000000 0x0 0x4000>, 1408 <0x0 0x7d000000 0x0 0x4000>; 1409 phy_type = "utmi"; 1410 clocks = <&tegra_car TEGRA210_CLK_USBD>, 1411 <&tegra_car TEGRA210_CLK_PLL_U>, 1412 <&tegra_car TEGRA210_CLK_USBD>; 1413 clock-names = "reg", "pll_u", "utmi-pads"; 1414 resets = <&tegra_car 22>, <&tegra_car 22>; 1415 reset-names = "usb", "utmi-pads"; 1416 nvidia,hssync-start-delay = <0>; 1417 nvidia,idle-wait-delay = <17>; 1418 nvidia,elastic-limit = <16>; 1419 nvidia,term-range-adj = <6>; 1420 nvidia,xcvr-setup = <9>; 1421 nvidia,xcvr-lsfslew = <0>; 1422 nvidia,xcvr-lsrslew = <3>; 1423 nvidia,hssquelch-level = <2>; 1424 nvidia,hsdiscon-level = <5>; 1425 nvidia,xcvr-hsslew = <12>; 1426 nvidia,has-utmi-pad-registers; 1427 status = "disabled"; 1428 }; 1429 1430 usb@7d004000 { 1431 compatible = "nvidia,tegra210-ehci", "nvidia,tegra30-ehci", "usb-ehci"; 1432 reg = <0x0 0x7d004000 0x0 0x4000>; 1433 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 1434 phy_type = "utmi"; 1435 clocks = <&tegra_car TEGRA210_CLK_USB2>; 1436 clock-names = "usb"; 1437 resets = <&tegra_car 58>; 1438 reset-names = "usb"; 1439 nvidia,phy = <&phy2>; 1440 status = "disabled"; 1441 }; 1442 1443 phy2: usb-phy@7d004000 { 1444 compatible = "nvidia,tegra210-usb-phy", "nvidia,tegra30-usb-phy"; 1445 reg = <0x0 0x7d004000 0x0 0x4000>, 1446 <0x0 0x7d000000 0x0 0x4000>; 1447 phy_type = "utmi"; 1448 clocks = <&tegra_car TEGRA210_CLK_USB2>, 1449 <&tegra_car TEGRA210_CLK_PLL_U>, 1450 <&tegra_car TEGRA210_CLK_USBD>; 1451 clock-names = "reg", "pll_u", "utmi-pads"; 1452 resets = <&tegra_car 58>, <&tegra_car 22>; 1453 reset-names = "usb", "utmi-pads"; 1454 nvidia,hssync-start-delay = <0>; 1455 nvidia,idle-wait-delay = <17>; 1456 nvidia,elastic-limit = <16>; 1457 nvidia,term-range-adj = <6>; 1458 nvidia,xcvr-setup = <9>; 1459 nvidia,xcvr-lsfslew = <0>; 1460 nvidia,xcvr-lsrslew = <3>; 1461 nvidia,hssquelch-level = <2>; 1462 nvidia,hsdiscon-level = <5>; 1463 nvidia,xcvr-hsslew = <12>; 1464 status = "disabled"; 1465 }; 1466 1467 cpus { 1468 #address-cells = <1>; 1469 #size-cells = <0>; 1470 1471 cpu@0 { 1472 device_type = "cpu"; 1473 compatible = "arm,cortex-a57"; 1474 reg = <0>; 1475 clocks = <&tegra_car TEGRA210_CLK_CCLK_G>, 1476 <&tegra_car TEGRA210_CLK_PLL_X>, 1477 <&tegra_car TEGRA210_CLK_PLL_P_OUT4>, 1478 <&dfll>; 1479 clock-names = "cpu_g", "pll_x", "pll_p", "dfll"; 1480 clock-latency = <300000>; 1481 cpu-idle-states = <&CPU_SLEEP>; 1482 next-level-cache = <&L2>; 1483 }; 1484 1485 cpu@1 { 1486 device_type = "cpu"; 1487 compatible = "arm,cortex-a57"; 1488 reg = <1>; 1489 cpu-idle-states = <&CPU_SLEEP>; 1490 next-level-cache = <&L2>; 1491 }; 1492 1493 cpu@2 { 1494 device_type = "cpu"; 1495 compatible = "arm,cortex-a57"; 1496 reg = <2>; 1497 cpu-idle-states = <&CPU_SLEEP>; 1498 next-level-cache = <&L2>; 1499 }; 1500 1501 cpu@3 { 1502 device_type = "cpu"; 1503 compatible = "arm,cortex-a57"; 1504 reg = <3>; 1505 cpu-idle-states = <&CPU_SLEEP>; 1506 next-level-cache = <&L2>; 1507 }; 1508 1509 idle-states { 1510 entry-method = "psci"; 1511 1512 CPU_SLEEP: cpu-sleep { 1513 compatible = "arm,idle-state"; 1514 arm,psci-suspend-param = <0x40000007>; 1515 entry-latency-us = <100>; 1516 exit-latency-us = <30>; 1517 min-residency-us = <1000>; 1518 wakeup-latency-us = <130>; 1519 idle-state-name = "cpu-sleep"; 1520 status = "disabled"; 1521 }; 1522 }; 1523 1524 L2: l2-cache { 1525 compatible = "cache"; 1526 }; 1527 }; 1528 1529 pmu { 1530 compatible = "arm,armv8-pmuv3"; 1531 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 1532 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 1533 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 1534 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; 1535 interrupt-affinity = <&{/cpus/cpu@0} &{/cpus/cpu@1} 1536 &{/cpus/cpu@2} &{/cpus/cpu@3}>; 1537 }; 1538 1539 timer { 1540 compatible = "arm,armv8-timer"; 1541 interrupts = <GIC_PPI 13 1542 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1543 <GIC_PPI 14 1544 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1545 <GIC_PPI 11 1546 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1547 <GIC_PPI 10 1548 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 1549 interrupt-parent = <&gic>; 1550 arm,no-tick-in-suspend; 1551 }; 1552 1553 soctherm: thermal-sensor@700e2000 { 1554 compatible = "nvidia,tegra210-soctherm"; 1555 reg = <0x0 0x700e2000 0x0 0x600>, /* SOC_THERM reg_base */ 1556 <0x0 0x60006000 0x0 0x400>; /* CAR reg_base */ 1557 reg-names = "soctherm-reg", "car-reg"; 1558 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, 1559 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 1560 interrupt-names = "thermal", "edp"; 1561 clocks = <&tegra_car TEGRA210_CLK_TSENSOR>, 1562 <&tegra_car TEGRA210_CLK_SOC_THERM>; 1563 clock-names = "tsensor", "soctherm"; 1564 resets = <&tegra_car 78>; 1565 reset-names = "soctherm"; 1566 #thermal-sensor-cells = <1>; 1567 1568 throttle-cfgs { 1569 throttle_heavy: heavy { 1570 nvidia,priority = <100>; 1571 nvidia,cpu-throt-percent = <85>; 1572 1573 #cooling-cells = <2>; 1574 }; 1575 }; 1576 }; 1577 1578 thermal-zones { 1579 cpu { 1580 polling-delay-passive = <1000>; 1581 polling-delay = <0>; 1582 1583 thermal-sensors = 1584 <&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>; 1585 1586 trips { 1587 cpu-shutdown-trip { 1588 temperature = <102500>; 1589 hysteresis = <0>; 1590 type = "critical"; 1591 }; 1592 1593 cpu_throttle_trip: throttle-trip { 1594 temperature = <98500>; 1595 hysteresis = <1000>; 1596 type = "hot"; 1597 }; 1598 }; 1599 1600 cooling-maps { 1601 map0 { 1602 trip = <&cpu_throttle_trip>; 1603 cooling-device = <&throttle_heavy 1 1>; 1604 }; 1605 }; 1606 }; 1607 1608 mem { 1609 polling-delay-passive = <0>; 1610 polling-delay = <0>; 1611 1612 thermal-sensors = 1613 <&soctherm TEGRA124_SOCTHERM_SENSOR_MEM>; 1614 1615 trips { 1616 dram_nominal: mem-nominal-trip { 1617 temperature = <50000>; 1618 hysteresis = <1000>; 1619 type = "passive"; 1620 }; 1621 1622 dram_throttle: mem-throttle-trip { 1623 temperature = <70000>; 1624 hysteresis = <1000>; 1625 type = "active"; 1626 }; 1627 1628 mem-shutdown-trip { 1629 temperature = <103000>; 1630 hysteresis = <0>; 1631 type = "critical"; 1632 }; 1633 }; 1634 1635 cooling-maps { 1636 dram-passive { 1637 cooling-device = <&emc 0 0>; 1638 trip = <&dram_nominal>; 1639 }; 1640 1641 dram-active { 1642 cooling-device = <&emc 1 1>; 1643 trip = <&dram_throttle>; 1644 }; 1645 }; 1646 }; 1647 1648 gpu { 1649 polling-delay-passive = <1000>; 1650 polling-delay = <0>; 1651 1652 thermal-sensors = 1653 <&soctherm TEGRA124_SOCTHERM_SENSOR_GPU>; 1654 1655 trips { 1656 gpu-shutdown-trip { 1657 temperature = <103000>; 1658 hysteresis = <0>; 1659 type = "critical"; 1660 }; 1661 1662 gpu_throttle_trip: throttle-trip { 1663 temperature = <100000>; 1664 hysteresis = <1000>; 1665 type = "hot"; 1666 }; 1667 }; 1668 1669 cooling-maps { 1670 map0 { 1671 trip = <&gpu_throttle_trip>; 1672 cooling-device = <&throttle_heavy 1 1>; 1673 }; 1674 }; 1675 }; 1676 1677 pllx { 1678 polling-delay-passive = <0>; 1679 polling-delay = <0>; 1680 1681 thermal-sensors = 1682 <&soctherm TEGRA124_SOCTHERM_SENSOR_PLLX>; 1683 1684 trips { 1685 pllx-shutdown-trip { 1686 temperature = <103000>; 1687 hysteresis = <0>; 1688 type = "critical"; 1689 }; 1690 }; 1691 1692 cooling-maps { 1693 /* 1694 * There are currently no cooling maps, 1695 * because there are no cooling devices. 1696 */ 1697 }; 1698 }; 1699 }; 1700}; 1701