arm64: tegra: Correct Tegra210 XUSB mailbox interrupt

The XUSB mailbox interrupt for Tegra210 is 40 and not 49 which is for
the XUSB pad controller. For some Tegra210 boards, this is cau

arm64: tegra: Correct Tegra210 XUSB mailbox interrupt

The XUSB mailbox interrupt for Tegra210 is 40 and not 49 which is for
the XUSB pad controller. For some Tegra210 boards, this is causing USB
connect and disconnect events to go undetected. Fix this by changing the
interrupt number for the XUSB mailbox to 40.

Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

show more ...

arm64: tegra: Add Tegra210 XUSB controller

Add a device tree node for the Tegra XUSB controller. It contains a
phandle to the XUSB pad controller for control of the PHYs assigned
to

arm64: tegra: Add Tegra210 XUSB controller

Add a device tree node for the Tegra XUSB controller. It contains a
phandle to the XUSB pad controller for control of the PHYs assigned
to the USB ports.

Signed-off-by: Thierry Reding <treding@nvidia.com>

show more ...

arm64: tegra: Add Tegra210 XUSB pad controller

Add a device tree node for the XUSB pad controller found on Tegra210.

Signed-off-by: Thierry Reding <treding@nvidia.com>

Merge tag 'tegra-for-4.7-gm20b' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/dt64

Merge "arm64: tegra: Enable GM20B GPU on Tegra210" from Thierry Reding:

C

Merge tag 'tegra-for-4.7-gm20b' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/dt64

Merge "arm64: tegra: Enable GM20B GPU on Tegra210" from Thierry Reding:

Complement the GM20B GPU device tree node on Tegra210 with missing
properties to make it usable.

* tag 'tegra-for-4.7-gm20b' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
arm64: tegra: Add IOMMU node to GM20B on Tegra210
arm64: tegra: Add reference clock to GM20B on Tegra210
dt-bindings: Add documentation for GM20B GPU
dt-bindings: gk20a: Document iommus property
dt-bindings: gk20a: Fix typo in compatible name

show more ...

arm64: tegra: Add IOMMU node to GM20B on Tegra210

The operating system driver can take advantage of the IOMMU to remove
the need for physically contiguous memory buffers.

Signed

arm64: tegra: Add IOMMU node to GM20B on Tegra210

The operating system driver can take advantage of the IOMMU to remove
the need for physically contiguous memory buffers.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

show more ...

arm64: tegra: Add reference clock to GM20B on Tegra210

This clock is required for the GPU to operate.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Thier

arm64: tegra: Add reference clock to GM20B on Tegra210

This clock is required for the GPU to operate.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

show more ...

arm64: tegra: Remove unused #power-domain-cells property

Remove the "#power-domain-cells" property which was incorrectly
included by commit e53095857166 ("arm64: tegra: Add Tegra210

arm64: tegra: Remove unused #power-domain-cells property

Remove the "#power-domain-cells" property which was incorrectly
included by commit e53095857166 ("arm64: tegra: Add Tegra210
support").

Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

show more ...

arm64: tegra: Fix copy/paste typo in several DTS includes

The comment about the 8250 vs. APB DMA-enabled UART devices that was
added for Tegra20 and Tegra30 in commit b6551bb933f9 ("ARM:

arm64: tegra: Fix copy/paste typo in several DTS includes

The comment about the 8250 vs. APB DMA-enabled UART devices that was
added for Tegra20 and Tegra30 in commit b6551bb933f9 ("ARM: tegra: dts:
add aliases and DMA requestor for serial controller") introduced a typo
that has since spread to various other DTS include files. Fix all
occurrences of this typo.

Suggested-by: Ralf Ramsauer <ralf@ramses-pyramidenbau.de>
Signed-off-by: Thierry Reding <treding@nvidia.com>

show more ...

arm64: tegra: Remove 0, prefix from unit-addresses

When Tegra124 support was first merged the unit-addresses of all devices
were listed with a "0," prefix to encode the reg property's se

arm64: tegra: Remove 0, prefix from unit-addresses

When Tegra124 support was first merged the unit-addresses of all devices
were listed with a "0," prefix to encode the reg property's second cell.
It turns out that this notation is not correct, and the "," separator is
only used to separate fields in the unit address (such as the device and
function number in PCI devices), not individual cells for addresses with
more than one cell.

Signed-off-by: Thierry Reding <treding@nvidia.com>

show more ...

arm64: Fix misspellings in comments.

Signed-off-by: Adam Buchbinder <adam.buchbinder@gmail.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

arm64: tegra: Add Tegra210 support

Also known as Tegra X1, the Tegra210 has four Cortex-A57 cores paired
with four Cortex-A53 cores in a switched configuration. It features a
GPU usi

arm64: tegra: Add Tegra210 support

Also known as Tegra X1, the Tegra210 has four Cortex-A57 cores paired
with four Cortex-A53 cores in a switched configuration. It features a
GPU using the Maxwell architecture with support for DX11, SM4, OpenGL
4.5, OpenGL ES 3.1 and providing 256 CUDA cores. It supports hardware
accelerated en- and decoding of various video standards including
H.265, H.264 and VP8 at 4K resolutions and up to 60 fps.

Besides the multimedia features it also comes with a variety of I/O
controllers such as GPIO, I2C, SPI, SDHCI, PCIe, SATA and XHCI, to
name only a few.

Add a SoC-level device tree file that describes most of the hardware
available on the SoC. This includes only hardware for which a device
tree binding already exists or which is trivial to describe.

Signed-off-by: Thierry Reding <treding@nvidia.com>

show more ...