1#include <dt-bindings/clock/tegra210-car.h> 2#include <dt-bindings/gpio/tegra-gpio.h> 3#include <dt-bindings/memory/tegra210-mc.h> 4#include <dt-bindings/pinctrl/pinctrl-tegra.h> 5#include <dt-bindings/interrupt-controller/arm-gic.h> 6 7/ { 8 compatible = "nvidia,tegra210"; 9 interrupt-parent = <&lic>; 10 #address-cells = <2>; 11 #size-cells = <2>; 12 13 host1x@50000000 { 14 compatible = "nvidia,tegra210-host1x", "simple-bus"; 15 reg = <0x0 0x50000000 0x0 0x00034000>; 16 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */ 17 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */ 18 clocks = <&tegra_car TEGRA210_CLK_HOST1X>; 19 clock-names = "host1x"; 20 resets = <&tegra_car 28>; 21 reset-names = "host1x"; 22 23 #address-cells = <2>; 24 #size-cells = <2>; 25 26 ranges = <0x0 0x54000000 0x0 0x54000000 0x0 0x01000000>; 27 28 dpaux1: dpaux@54040000 { 29 compatible = "nvidia,tegra210-dpaux"; 30 reg = <0x0 0x54040000 0x0 0x00040000>; 31 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 32 clocks = <&tegra_car TEGRA210_CLK_DPAUX1>, 33 <&tegra_car TEGRA210_CLK_PLL_DP>; 34 clock-names = "dpaux", "parent"; 35 resets = <&tegra_car 207>; 36 reset-names = "dpaux"; 37 status = "disabled"; 38 }; 39 40 vi@54080000 { 41 compatible = "nvidia,tegra210-vi"; 42 reg = <0x0 0x54080000 0x0 0x00040000>; 43 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 44 status = "disabled"; 45 }; 46 47 tsec@54100000 { 48 compatible = "nvidia,tegra210-tsec"; 49 reg = <0x0 0x54100000 0x0 0x00040000>; 50 }; 51 52 dc@54200000 { 53 compatible = "nvidia,tegra210-dc"; 54 reg = <0x0 0x54200000 0x0 0x00040000>; 55 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 56 clocks = <&tegra_car TEGRA210_CLK_DISP1>, 57 <&tegra_car TEGRA210_CLK_PLL_P>; 58 clock-names = "dc", "parent"; 59 resets = <&tegra_car 27>; 60 reset-names = "dc"; 61 62 iommus = <&mc TEGRA_SWGROUP_DC>; 63 64 nvidia,head = <0>; 65 }; 66 67 dc@54240000 { 68 compatible = "nvidia,tegra210-dc"; 69 reg = <0x0 0x54240000 0x0 0x00040000>; 70 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 71 clocks = <&tegra_car TEGRA210_CLK_DISP2>, 72 <&tegra_car TEGRA210_CLK_PLL_P>; 73 clock-names = "dc", "parent"; 74 resets = <&tegra_car 26>; 75 reset-names = "dc"; 76 77 iommus = <&mc TEGRA_SWGROUP_DCB>; 78 79 nvidia,head = <1>; 80 }; 81 82 dsi@54300000 { 83 compatible = "nvidia,tegra210-dsi"; 84 reg = <0x0 0x54300000 0x0 0x00040000>; 85 clocks = <&tegra_car TEGRA210_CLK_DSIA>, 86 <&tegra_car TEGRA210_CLK_DSIALP>, 87 <&tegra_car TEGRA210_CLK_PLL_D_OUT0>; 88 clock-names = "dsi", "lp", "parent"; 89 resets = <&tegra_car 48>; 90 reset-names = "dsi"; 91 nvidia,mipi-calibrate = <&mipi 0x0c0>; /* DSIA & DSIB pads */ 92 93 status = "disabled"; 94 95 #address-cells = <1>; 96 #size-cells = <0>; 97 }; 98 99 vic@54340000 { 100 compatible = "nvidia,tegra210-vic"; 101 reg = <0x0 0x54340000 0x0 0x00040000>; 102 status = "disabled"; 103 }; 104 105 nvjpg@54380000 { 106 compatible = "nvidia,tegra210-nvjpg"; 107 reg = <0x0 0x54380000 0x0 0x00040000>; 108 status = "disabled"; 109 }; 110 111 dsi@54400000 { 112 compatible = "nvidia,tegra210-dsi"; 113 reg = <0x0 0x54400000 0x0 0x00040000>; 114 clocks = <&tegra_car TEGRA210_CLK_DSIB>, 115 <&tegra_car TEGRA210_CLK_DSIBLP>, 116 <&tegra_car TEGRA210_CLK_PLL_D_OUT0>; 117 clock-names = "dsi", "lp", "parent"; 118 resets = <&tegra_car 82>; 119 reset-names = "dsi"; 120 nvidia,mipi-calibrate = <&mipi 0x300>; /* DSIC & DSID pads */ 121 122 status = "disabled"; 123 124 #address-cells = <1>; 125 #size-cells = <0>; 126 }; 127 128 nvdec@54480000 { 129 compatible = "nvidia,tegra210-nvdec"; 130 reg = <0x0 0x54480000 0x0 0x00040000>; 131 status = "disabled"; 132 }; 133 134 nvenc@544c0000 { 135 compatible = "nvidia,tegra210-nvenc"; 136 reg = <0x0 0x544c0000 0x0 0x00040000>; 137 status = "disabled"; 138 }; 139 140 tsec@54500000 { 141 compatible = "nvidia,tegra210-tsec"; 142 reg = <0x0 0x54500000 0x0 0x00040000>; 143 status = "disabled"; 144 }; 145 146 sor@54540000 { 147 compatible = "nvidia,tegra210-sor"; 148 reg = <0x0 0x54540000 0x0 0x00040000>; 149 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 150 clocks = <&tegra_car TEGRA210_CLK_SOR0>, 151 <&tegra_car TEGRA210_CLK_PLL_D_OUT0>, 152 <&tegra_car TEGRA210_CLK_PLL_DP>, 153 <&tegra_car TEGRA210_CLK_SOR_SAFE>; 154 clock-names = "sor", "parent", "dp", "safe"; 155 resets = <&tegra_car 182>; 156 reset-names = "sor"; 157 status = "disabled"; 158 }; 159 160 sor@54580000 { 161 compatible = "nvidia,tegra210-sor1"; 162 reg = <0x0 0x54580000 0x0 0x00040000>; 163 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 164 clocks = <&tegra_car TEGRA210_CLK_SOR1>, 165 <&tegra_car TEGRA210_CLK_PLL_D2_OUT0>, 166 <&tegra_car TEGRA210_CLK_PLL_DP>, 167 <&tegra_car TEGRA210_CLK_SOR_SAFE>; 168 clock-names = "sor", "parent", "dp", "safe"; 169 resets = <&tegra_car 183>; 170 reset-names = "sor"; 171 status = "disabled"; 172 }; 173 174 dpaux: dpaux@545c0000 { 175 compatible = "nvidia,tegra124-dpaux"; 176 reg = <0x0 0x545c0000 0x0 0x00040000>; 177 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 178 clocks = <&tegra_car TEGRA210_CLK_DPAUX>, 179 <&tegra_car TEGRA210_CLK_PLL_DP>; 180 clock-names = "dpaux", "parent"; 181 resets = <&tegra_car 181>; 182 reset-names = "dpaux"; 183 status = "disabled"; 184 }; 185 186 isp@54600000 { 187 compatible = "nvidia,tegra210-isp"; 188 reg = <0x0 0x54600000 0x0 0x00040000>; 189 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 190 status = "disabled"; 191 }; 192 193 isp@54680000 { 194 compatible = "nvidia,tegra210-isp"; 195 reg = <0x0 0x54680000 0x0 0x00040000>; 196 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 197 status = "disabled"; 198 }; 199 200 i2c@546c0000 { 201 compatible = "nvidia,tegra210-i2c-vi"; 202 reg = <0x0 0x546c0000 0x0 0x00040000>; 203 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 204 status = "disabled"; 205 }; 206 }; 207 208 gic: interrupt-controller@50041000 { 209 compatible = "arm,gic-400"; 210 #interrupt-cells = <3>; 211 interrupt-controller; 212 reg = <0x0 0x50041000 0x0 0x1000>, 213 <0x0 0x50042000 0x0 0x2000>, 214 <0x0 0x50044000 0x0 0x2000>, 215 <0x0 0x50046000 0x0 0x2000>; 216 interrupts = <GIC_PPI 9 217 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 218 interrupt-parent = <&gic>; 219 }; 220 221 gpu@57000000 { 222 compatible = "nvidia,gm20b"; 223 reg = <0x0 0x57000000 0x0 0x01000000>, 224 <0x0 0x58000000 0x0 0x01000000>; 225 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 226 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 227 interrupt-names = "stall", "nonstall"; 228 clocks = <&tegra_car TEGRA210_CLK_GPU>, 229 <&tegra_car TEGRA210_CLK_PLL_P_OUT5>, 230 <&tegra_car TEGRA210_CLK_PLL_G_REF>; 231 clock-names = "gpu", "pwr", "ref"; 232 resets = <&tegra_car 184>; 233 reset-names = "gpu"; 234 235 iommus = <&mc TEGRA_SWGROUP_GPU>; 236 237 status = "disabled"; 238 }; 239 240 lic: interrupt-controller@60004000 { 241 compatible = "nvidia,tegra210-ictlr"; 242 reg = <0x0 0x60004000 0x0 0x40>, /* primary controller */ 243 <0x0 0x60004100 0x0 0x40>, /* secondary controller */ 244 <0x0 0x60004200 0x0 0x40>, /* tertiary controller */ 245 <0x0 0x60004300 0x0 0x40>, /* quaternary controller */ 246 <0x0 0x60004400 0x0 0x40>, /* quinary controller */ 247 <0x0 0x60004500 0x0 0x40>; /* senary controller */ 248 interrupt-controller; 249 #interrupt-cells = <3>; 250 interrupt-parent = <&gic>; 251 }; 252 253 timer@60005000 { 254 compatible = "nvidia,tegra210-timer", "nvidia,tegra20-timer"; 255 reg = <0x0 0x60005000 0x0 0x400>; 256 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 257 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 258 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 259 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 260 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 261 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 262 clocks = <&tegra_car TEGRA210_CLK_TIMER>; 263 clock-names = "timer"; 264 }; 265 266 tegra_car: clock@60006000 { 267 compatible = "nvidia,tegra210-car"; 268 reg = <0x0 0x60006000 0x0 0x1000>; 269 #clock-cells = <1>; 270 #reset-cells = <1>; 271 }; 272 273 flow-controller@60007000 { 274 compatible = "nvidia,tegra210-flowctrl"; 275 reg = <0x0 0x60007000 0x0 0x1000>; 276 }; 277 278 gpio: gpio@6000d000 { 279 compatible = "nvidia,tegra210-gpio", "nvidia,tegra124-gpio", "nvidia,tegra30-gpio"; 280 reg = <0x0 0x6000d000 0x0 0x1000>; 281 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 282 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 283 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 284 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 285 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 286 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 287 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 288 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 289 #gpio-cells = <2>; 290 gpio-controller; 291 #interrupt-cells = <2>; 292 interrupt-controller; 293 }; 294 295 apbdma: dma@60020000 { 296 compatible = "nvidia,tegra210-apbdma", "nvidia,tegra148-apbdma"; 297 reg = <0x0 0x60020000 0x0 0x1400>; 298 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 299 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 300 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 301 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 302 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 303 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 304 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 305 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 306 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 307 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 308 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 309 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 310 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 311 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 312 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 313 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 314 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 315 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 316 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 317 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 318 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 319 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 320 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 321 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 322 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 323 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 324 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 325 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 326 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 327 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 328 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 329 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 330 clocks = <&tegra_car TEGRA210_CLK_APBDMA>; 331 clock-names = "dma"; 332 resets = <&tegra_car 34>; 333 reset-names = "dma"; 334 #dma-cells = <1>; 335 }; 336 337 apbmisc@70000800 { 338 compatible = "nvidia,tegra210-apbmisc", "nvidia,tegra20-apbmisc"; 339 reg = <0x0 0x70000800 0x0 0x64>, /* Chip revision */ 340 <0x0 0x7000e864 0x0 0x04>; /* Strapping options */ 341 }; 342 343 pinmux: pinmux@700008d4 { 344 compatible = "nvidia,tegra210-pinmux"; 345 reg = <0x0 0x700008d4 0x0 0x29c>, /* Pad control registers */ 346 <0x0 0x70003000 0x0 0x294>; /* Mux registers */ 347 }; 348 349 /* 350 * There are two serial driver i.e. 8250 based simple serial 351 * driver and APB DMA based serial driver for higher baudrate 352 * and performance. To enable the 8250 based driver, the compatible 353 * is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable 354 * the APB DMA based serial driver, the compatible is 355 * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart". 356 */ 357 uarta: serial@70006000 { 358 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; 359 reg = <0x0 0x70006000 0x0 0x40>; 360 reg-shift = <2>; 361 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 362 clocks = <&tegra_car TEGRA210_CLK_UARTA>; 363 clock-names = "serial"; 364 resets = <&tegra_car 6>; 365 reset-names = "serial"; 366 dmas = <&apbdma 8>, <&apbdma 8>; 367 dma-names = "rx", "tx"; 368 status = "disabled"; 369 }; 370 371 uartb: serial@70006040 { 372 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; 373 reg = <0x0 0x70006040 0x0 0x40>; 374 reg-shift = <2>; 375 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 376 clocks = <&tegra_car TEGRA210_CLK_UARTB>; 377 clock-names = "serial"; 378 resets = <&tegra_car 7>; 379 reset-names = "serial"; 380 dmas = <&apbdma 9>, <&apbdma 9>; 381 dma-names = "rx", "tx"; 382 status = "disabled"; 383 }; 384 385 uartc: serial@70006200 { 386 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; 387 reg = <0x0 0x70006200 0x0 0x40>; 388 reg-shift = <2>; 389 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 390 clocks = <&tegra_car TEGRA210_CLK_UARTC>; 391 clock-names = "serial"; 392 resets = <&tegra_car 55>; 393 reset-names = "serial"; 394 dmas = <&apbdma 10>, <&apbdma 10>; 395 dma-names = "rx", "tx"; 396 status = "disabled"; 397 }; 398 399 uartd: serial@70006300 { 400 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; 401 reg = <0x0 0x70006300 0x0 0x40>; 402 reg-shift = <2>; 403 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 404 clocks = <&tegra_car TEGRA210_CLK_UARTD>; 405 clock-names = "serial"; 406 resets = <&tegra_car 65>; 407 reset-names = "serial"; 408 dmas = <&apbdma 19>, <&apbdma 19>; 409 dma-names = "rx", "tx"; 410 status = "disabled"; 411 }; 412 413 pwm: pwm@7000a000 { 414 compatible = "nvidia,tegra210-pwm", "nvidia,tegra20-pwm"; 415 reg = <0x0 0x7000a000 0x0 0x100>; 416 #pwm-cells = <2>; 417 clocks = <&tegra_car TEGRA210_CLK_PWM>; 418 clock-names = "pwm"; 419 resets = <&tegra_car 17>; 420 reset-names = "pwm"; 421 status = "disabled"; 422 }; 423 424 i2c@7000c000 { 425 compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c"; 426 reg = <0x0 0x7000c000 0x0 0x100>; 427 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 428 #address-cells = <1>; 429 #size-cells = <0>; 430 clocks = <&tegra_car TEGRA210_CLK_I2C1>; 431 clock-names = "div-clk"; 432 resets = <&tegra_car 12>; 433 reset-names = "i2c"; 434 dmas = <&apbdma 21>, <&apbdma 21>; 435 dma-names = "rx", "tx"; 436 status = "disabled"; 437 }; 438 439 i2c@7000c400 { 440 compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c"; 441 reg = <0x0 0x7000c400 0x0 0x100>; 442 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 443 #address-cells = <1>; 444 #size-cells = <0>; 445 clocks = <&tegra_car TEGRA210_CLK_I2C2>; 446 clock-names = "div-clk"; 447 resets = <&tegra_car 54>; 448 reset-names = "i2c"; 449 dmas = <&apbdma 22>, <&apbdma 22>; 450 dma-names = "rx", "tx"; 451 status = "disabled"; 452 }; 453 454 i2c@7000c500 { 455 compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c"; 456 reg = <0x0 0x7000c500 0x0 0x100>; 457 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 458 #address-cells = <1>; 459 #size-cells = <0>; 460 clocks = <&tegra_car TEGRA210_CLK_I2C3>; 461 clock-names = "div-clk"; 462 resets = <&tegra_car 67>; 463 reset-names = "i2c"; 464 dmas = <&apbdma 23>, <&apbdma 23>; 465 dma-names = "rx", "tx"; 466 status = "disabled"; 467 }; 468 469 i2c@7000c700 { 470 compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c"; 471 reg = <0x0 0x7000c700 0x0 0x100>; 472 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 473 #address-cells = <1>; 474 #size-cells = <0>; 475 clocks = <&tegra_car TEGRA210_CLK_I2C4>; 476 clock-names = "div-clk"; 477 resets = <&tegra_car 103>; 478 reset-names = "i2c"; 479 dmas = <&apbdma 26>, <&apbdma 26>; 480 dma-names = "rx", "tx"; 481 status = "disabled"; 482 }; 483 484 i2c@7000d000 { 485 compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c"; 486 reg = <0x0 0x7000d000 0x0 0x100>; 487 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 488 #address-cells = <1>; 489 #size-cells = <0>; 490 clocks = <&tegra_car TEGRA210_CLK_I2C5>; 491 clock-names = "div-clk"; 492 resets = <&tegra_car 47>; 493 reset-names = "i2c"; 494 dmas = <&apbdma 24>, <&apbdma 24>; 495 dma-names = "rx", "tx"; 496 status = "disabled"; 497 }; 498 499 i2c@7000d100 { 500 compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c"; 501 reg = <0x0 0x7000d100 0x0 0x100>; 502 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 503 #address-cells = <1>; 504 #size-cells = <0>; 505 clocks = <&tegra_car TEGRA210_CLK_I2C6>; 506 clock-names = "div-clk"; 507 resets = <&tegra_car 166>; 508 reset-names = "i2c"; 509 dmas = <&apbdma 30>, <&apbdma 30>; 510 dma-names = "rx", "tx"; 511 status = "disabled"; 512 }; 513 514 spi@7000d400 { 515 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 516 reg = <0x0 0x7000d400 0x0 0x200>; 517 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 518 #address-cells = <1>; 519 #size-cells = <0>; 520 clocks = <&tegra_car TEGRA210_CLK_SBC1>; 521 clock-names = "spi"; 522 resets = <&tegra_car 41>; 523 reset-names = "spi"; 524 dmas = <&apbdma 15>, <&apbdma 15>; 525 dma-names = "rx", "tx"; 526 status = "disabled"; 527 }; 528 529 spi@7000d600 { 530 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 531 reg = <0x0 0x7000d600 0x0 0x200>; 532 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 533 #address-cells = <1>; 534 #size-cells = <0>; 535 clocks = <&tegra_car TEGRA210_CLK_SBC2>; 536 clock-names = "spi"; 537 resets = <&tegra_car 44>; 538 reset-names = "spi"; 539 dmas = <&apbdma 16>, <&apbdma 16>; 540 dma-names = "rx", "tx"; 541 status = "disabled"; 542 }; 543 544 spi@7000d800 { 545 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 546 reg = <0x0 0x7000d800 0x0 0x200>; 547 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 548 #address-cells = <1>; 549 #size-cells = <0>; 550 clocks = <&tegra_car TEGRA210_CLK_SBC3>; 551 clock-names = "spi"; 552 resets = <&tegra_car 46>; 553 reset-names = "spi"; 554 dmas = <&apbdma 17>, <&apbdma 17>; 555 dma-names = "rx", "tx"; 556 status = "disabled"; 557 }; 558 559 spi@7000da00 { 560 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 561 reg = <0x0 0x7000da00 0x0 0x200>; 562 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 563 #address-cells = <1>; 564 #size-cells = <0>; 565 clocks = <&tegra_car TEGRA210_CLK_SBC4>; 566 clock-names = "spi"; 567 resets = <&tegra_car 68>; 568 reset-names = "spi"; 569 dmas = <&apbdma 18>, <&apbdma 18>; 570 dma-names = "rx", "tx"; 571 status = "disabled"; 572 }; 573 574 rtc@7000e000 { 575 compatible = "nvidia,tegra210-rtc", "nvidia,tegra20-rtc"; 576 reg = <0x0 0x7000e000 0x0 0x100>; 577 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 578 clocks = <&tegra_car TEGRA210_CLK_RTC>; 579 clock-names = "rtc"; 580 }; 581 582 pmc: pmc@7000e400 { 583 compatible = "nvidia,tegra210-pmc"; 584 reg = <0x0 0x7000e400 0x0 0x400>; 585 clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>; 586 clock-names = "pclk", "clk32k_in"; 587 }; 588 589 fuse@7000f800 { 590 compatible = "nvidia,tegra210-efuse"; 591 reg = <0x0 0x7000f800 0x0 0x400>; 592 clocks = <&tegra_car TEGRA210_CLK_FUSE>; 593 clock-names = "fuse"; 594 resets = <&tegra_car 39>; 595 reset-names = "fuse"; 596 }; 597 598 mc: memory-controller@70019000 { 599 compatible = "nvidia,tegra210-mc"; 600 reg = <0x0 0x70019000 0x0 0x1000>; 601 clocks = <&tegra_car TEGRA210_CLK_MC>; 602 clock-names = "mc"; 603 604 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 605 606 #iommu-cells = <1>; 607 }; 608 609 hda@70030000 { 610 compatible = "nvidia,tegra210-hda", "nvidia,tegra30-hda"; 611 reg = <0x0 0x70030000 0x0 0x10000>; 612 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 613 clocks = <&tegra_car TEGRA210_CLK_HDA>, 614 <&tegra_car TEGRA210_CLK_HDA2HDMI>, 615 <&tegra_car TEGRA210_CLK_HDA2CODEC_2X>; 616 clock-names = "hda", "hda2hdmi", "hda2codec_2x"; 617 resets = <&tegra_car 125>, /* hda */ 618 <&tegra_car 128>, /* hda2hdmi */ 619 <&tegra_car 111>; /* hda2codec_2x */ 620 reset-names = "hda", "hda2hdmi", "hda2codec_2x"; 621 status = "disabled"; 622 }; 623 624 usb@70090000 { 625 compatible = "nvidia,tegra210-xusb"; 626 reg = <0x0 0x70090000 0x0 0x8000>, 627 <0x0 0x70098000 0x0 0x1000>, 628 <0x0 0x70099000 0x0 0x1000>; 629 reg-names = "hcd", "fpci", "ipfs"; 630 631 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 632 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 633 634 clocks = <&tegra_car TEGRA210_CLK_XUSB_HOST>, 635 <&tegra_car TEGRA210_CLK_XUSB_HOST_SRC>, 636 <&tegra_car TEGRA210_CLK_XUSB_FALCON_SRC>, 637 <&tegra_car TEGRA210_CLK_XUSB_SS>, 638 <&tegra_car TEGRA210_CLK_XUSB_SS_DIV2>, 639 <&tegra_car TEGRA210_CLK_XUSB_SS_SRC>, 640 <&tegra_car TEGRA210_CLK_XUSB_HS_SRC>, 641 <&tegra_car TEGRA210_CLK_XUSB_FS_SRC>, 642 <&tegra_car TEGRA210_CLK_PLL_U_480M>, 643 <&tegra_car TEGRA210_CLK_CLK_M>, 644 <&tegra_car TEGRA210_CLK_PLL_E>; 645 clock-names = "xusb_host", "xusb_host_src", 646 "xusb_falcon_src", "xusb_ss", 647 "xusb_ss_div2", "xusb_ss_src", 648 "xusb_hs_src", "xusb_fs_src", 649 "pll_u_480m", "clk_m", "pll_e"; 650 resets = <&tegra_car 89>, <&tegra_car 156>, 651 <&tegra_car 143>; 652 reset-names = "xusb_host", "xusb_ss", "xusb_src"; 653 654 nvidia,xusb-padctl = <&padctl>; 655 656 status = "disabled"; 657 }; 658 659 padctl: padctl@7009f000 { 660 compatible = "nvidia,tegra210-xusb-padctl"; 661 reg = <0x0 0x7009f000 0x0 0x1000>; 662 resets = <&tegra_car 142>; 663 reset-names = "padctl"; 664 665 status = "disabled"; 666 667 pads { 668 usb2 { 669 clocks = <&tegra_car TEGRA210_CLK_USB2_TRK>; 670 clock-names = "trk"; 671 status = "disabled"; 672 673 lanes { 674 usb2-0 { 675 status = "disabled"; 676 #phy-cells = <0>; 677 }; 678 679 usb2-1 { 680 status = "disabled"; 681 #phy-cells = <0>; 682 }; 683 684 usb2-2 { 685 status = "disabled"; 686 #phy-cells = <0>; 687 }; 688 689 usb2-3 { 690 status = "disabled"; 691 #phy-cells = <0>; 692 }; 693 }; 694 }; 695 696 hsic { 697 clocks = <&tegra_car TEGRA210_CLK_HSIC_TRK>; 698 clock-names = "trk"; 699 status = "disabled"; 700 701 lanes { 702 hsic-0 { 703 status = "disabled"; 704 #phy-cells = <0>; 705 }; 706 707 hsic-1 { 708 status = "disabled"; 709 #phy-cells = <0>; 710 }; 711 }; 712 }; 713 714 pcie { 715 clocks = <&tegra_car TEGRA210_CLK_PLL_E>; 716 clock-names = "pll"; 717 resets = <&tegra_car 205>; 718 reset-names = "phy"; 719 status = "disabled"; 720 721 lanes { 722 pcie-0 { 723 status = "disabled"; 724 #phy-cells = <0>; 725 }; 726 727 pcie-1 { 728 status = "disabled"; 729 #phy-cells = <0>; 730 }; 731 732 pcie-2 { 733 status = "disabled"; 734 #phy-cells = <0>; 735 }; 736 737 pcie-3 { 738 status = "disabled"; 739 #phy-cells = <0>; 740 }; 741 742 pcie-4 { 743 status = "disabled"; 744 #phy-cells = <0>; 745 }; 746 747 pcie-5 { 748 status = "disabled"; 749 #phy-cells = <0>; 750 }; 751 752 pcie-6 { 753 status = "disabled"; 754 #phy-cells = <0>; 755 }; 756 }; 757 }; 758 759 sata { 760 clocks = <&tegra_car TEGRA210_CLK_PLL_E>; 761 clock-names = "pll"; 762 resets = <&tegra_car 204>; 763 reset-names = "phy"; 764 status = "disabled"; 765 766 lanes { 767 sata-0 { 768 status = "disabled"; 769 #phy-cells = <0>; 770 }; 771 }; 772 }; 773 }; 774 775 ports { 776 usb2-0 { 777 status = "disabled"; 778 }; 779 780 usb2-1 { 781 status = "disabled"; 782 }; 783 784 usb2-2 { 785 status = "disabled"; 786 }; 787 788 usb2-3 { 789 status = "disabled"; 790 }; 791 792 hsic-0 { 793 status = "disabled"; 794 }; 795 796 usb3-0 { 797 status = "disabled"; 798 }; 799 800 usb3-1 { 801 status = "disabled"; 802 }; 803 804 usb3-2 { 805 status = "disabled"; 806 }; 807 808 usb3-3 { 809 status = "disabled"; 810 }; 811 }; 812 }; 813 814 sdhci@700b0000 { 815 compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci"; 816 reg = <0x0 0x700b0000 0x0 0x200>; 817 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 818 clocks = <&tegra_car TEGRA210_CLK_SDMMC1>; 819 clock-names = "sdhci"; 820 resets = <&tegra_car 14>; 821 reset-names = "sdhci"; 822 status = "disabled"; 823 }; 824 825 sdhci@700b0200 { 826 compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci"; 827 reg = <0x0 0x700b0200 0x0 0x200>; 828 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 829 clocks = <&tegra_car TEGRA210_CLK_SDMMC2>; 830 clock-names = "sdhci"; 831 resets = <&tegra_car 9>; 832 reset-names = "sdhci"; 833 status = "disabled"; 834 }; 835 836 sdhci@700b0400 { 837 compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci"; 838 reg = <0x0 0x700b0400 0x0 0x200>; 839 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 840 clocks = <&tegra_car TEGRA210_CLK_SDMMC3>; 841 clock-names = "sdhci"; 842 resets = <&tegra_car 69>; 843 reset-names = "sdhci"; 844 status = "disabled"; 845 }; 846 847 sdhci@700b0600 { 848 compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci"; 849 reg = <0x0 0x700b0600 0x0 0x200>; 850 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 851 clocks = <&tegra_car TEGRA210_CLK_SDMMC4>; 852 clock-names = "sdhci"; 853 resets = <&tegra_car 15>; 854 reset-names = "sdhci"; 855 status = "disabled"; 856 }; 857 858 mipi: mipi@700e3000 { 859 compatible = "nvidia,tegra210-mipi"; 860 reg = <0x0 0x700e3000 0x0 0x100>; 861 clocks = <&tegra_car TEGRA210_CLK_MIPI_CAL>; 862 clock-names = "mipi-cal"; 863 #nvidia,mipi-calibrate-cells = <1>; 864 }; 865 866 spi@70410000 { 867 compatible = "nvidia,tegra210-qspi"; 868 reg = <0x0 0x70410000 0x0 0x1000>; 869 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 870 #address-cells = <1>; 871 #size-cells = <0>; 872 clocks = <&tegra_car TEGRA210_CLK_QSPI>; 873 clock-names = "qspi"; 874 resets = <&tegra_car 211>; 875 reset-names = "qspi"; 876 dmas = <&apbdma 5>, <&apbdma 5>; 877 dma-names = "rx", "tx"; 878 status = "disabled"; 879 }; 880 881 usb@7d000000 { 882 compatible = "nvidia,tegra210-ehci", "nvidia,tegra30-ehci", "usb-ehci"; 883 reg = <0x0 0x7d000000 0x0 0x4000>; 884 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 885 phy_type = "utmi"; 886 clocks = <&tegra_car TEGRA210_CLK_USBD>; 887 clock-names = "usb"; 888 resets = <&tegra_car 22>; 889 reset-names = "usb"; 890 nvidia,phy = <&phy1>; 891 status = "disabled"; 892 }; 893 894 phy1: usb-phy@7d000000 { 895 compatible = "nvidia,tegra210-usb-phy", "nvidia,tegra30-usb-phy"; 896 reg = <0x0 0x7d000000 0x0 0x4000>, 897 <0x0 0x7d000000 0x0 0x4000>; 898 phy_type = "utmi"; 899 clocks = <&tegra_car TEGRA210_CLK_USBD>, 900 <&tegra_car TEGRA210_CLK_PLL_U>, 901 <&tegra_car TEGRA210_CLK_USBD>; 902 clock-names = "reg", "pll_u", "utmi-pads"; 903 resets = <&tegra_car 22>, <&tegra_car 22>; 904 reset-names = "usb", "utmi-pads"; 905 nvidia,hssync-start-delay = <0>; 906 nvidia,idle-wait-delay = <17>; 907 nvidia,elastic-limit = <16>; 908 nvidia,term-range-adj = <6>; 909 nvidia,xcvr-setup = <9>; 910 nvidia,xcvr-lsfslew = <0>; 911 nvidia,xcvr-lsrslew = <3>; 912 nvidia,hssquelch-level = <2>; 913 nvidia,hsdiscon-level = <5>; 914 nvidia,xcvr-hsslew = <12>; 915 nvidia,has-utmi-pad-registers; 916 status = "disabled"; 917 }; 918 919 usb@7d004000 { 920 compatible = "nvidia,tegra210-ehci", "nvidia,tegra30-ehci", "usb-ehci"; 921 reg = <0x0 0x7d004000 0x0 0x4000>; 922 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 923 phy_type = "utmi"; 924 clocks = <&tegra_car TEGRA210_CLK_USB2>; 925 clock-names = "usb"; 926 resets = <&tegra_car 58>; 927 reset-names = "usb"; 928 nvidia,phy = <&phy2>; 929 status = "disabled"; 930 }; 931 932 phy2: usb-phy@7d004000 { 933 compatible = "nvidia,tegra210-usb-phy", "nvidia,tegra30-usb-phy"; 934 reg = <0x0 0x7d004000 0x0 0x4000>, 935 <0x0 0x7d000000 0x0 0x4000>; 936 phy_type = "utmi"; 937 clocks = <&tegra_car TEGRA210_CLK_USB2>, 938 <&tegra_car TEGRA210_CLK_PLL_U>, 939 <&tegra_car TEGRA210_CLK_USBD>; 940 clock-names = "reg", "pll_u", "utmi-pads"; 941 resets = <&tegra_car 58>, <&tegra_car 22>; 942 reset-names = "usb", "utmi-pads"; 943 nvidia,hssync-start-delay = <0>; 944 nvidia,idle-wait-delay = <17>; 945 nvidia,elastic-limit = <16>; 946 nvidia,term-range-adj = <6>; 947 nvidia,xcvr-setup = <9>; 948 nvidia,xcvr-lsfslew = <0>; 949 nvidia,xcvr-lsrslew = <3>; 950 nvidia,hssquelch-level = <2>; 951 nvidia,hsdiscon-level = <5>; 952 nvidia,xcvr-hsslew = <12>; 953 status = "disabled"; 954 }; 955 956 cpus { 957 #address-cells = <1>; 958 #size-cells = <0>; 959 960 cpu@0 { 961 device_type = "cpu"; 962 compatible = "arm,cortex-a57"; 963 reg = <0>; 964 }; 965 966 cpu@1 { 967 device_type = "cpu"; 968 compatible = "arm,cortex-a57"; 969 reg = <1>; 970 }; 971 972 cpu@2 { 973 device_type = "cpu"; 974 compatible = "arm,cortex-a57"; 975 reg = <2>; 976 }; 977 978 cpu@3 { 979 device_type = "cpu"; 980 compatible = "arm,cortex-a57"; 981 reg = <3>; 982 }; 983 }; 984 985 timer { 986 compatible = "arm,armv8-timer"; 987 interrupts = <GIC_PPI 13 988 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 989 <GIC_PPI 14 990 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 991 <GIC_PPI 11 992 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 993 <GIC_PPI 10 994 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 995 interrupt-parent = <&gic>; 996 }; 997}; 998