1#include <dt-bindings/clock/tegra210-car.h> 2#include <dt-bindings/gpio/tegra-gpio.h> 3#include <dt-bindings/memory/tegra210-mc.h> 4#include <dt-bindings/pinctrl/pinctrl-tegra.h> 5#include <dt-bindings/interrupt-controller/arm-gic.h> 6 7/ { 8 compatible = "nvidia,tegra210"; 9 interrupt-parent = <&lic>; 10 #address-cells = <2>; 11 #size-cells = <2>; 12 13 host1x@50000000 { 14 compatible = "nvidia,tegra210-host1x", "simple-bus"; 15 reg = <0x0 0x50000000 0x0 0x00034000>; 16 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */ 17 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */ 18 clocks = <&tegra_car TEGRA210_CLK_HOST1X>; 19 clock-names = "host1x"; 20 resets = <&tegra_car 28>; 21 reset-names = "host1x"; 22 23 #address-cells = <2>; 24 #size-cells = <2>; 25 26 ranges = <0x0 0x54000000 0x0 0x54000000 0x0 0x01000000>; 27 28 dpaux1: dpaux@54040000 { 29 compatible = "nvidia,tegra210-dpaux"; 30 reg = <0x0 0x54040000 0x0 0x00040000>; 31 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 32 clocks = <&tegra_car TEGRA210_CLK_DPAUX1>, 33 <&tegra_car TEGRA210_CLK_PLL_DP>; 34 clock-names = "dpaux", "parent"; 35 resets = <&tegra_car 207>; 36 reset-names = "dpaux"; 37 status = "disabled"; 38 }; 39 40 vi@54080000 { 41 compatible = "nvidia,tegra210-vi"; 42 reg = <0x0 0x54080000 0x0 0x00040000>; 43 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 44 status = "disabled"; 45 }; 46 47 tsec@54100000 { 48 compatible = "nvidia,tegra210-tsec"; 49 reg = <0x0 0x54100000 0x0 0x00040000>; 50 }; 51 52 dc@54200000 { 53 compatible = "nvidia,tegra210-dc"; 54 reg = <0x0 0x54200000 0x0 0x00040000>; 55 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 56 clocks = <&tegra_car TEGRA210_CLK_DISP1>, 57 <&tegra_car TEGRA210_CLK_PLL_P>; 58 clock-names = "dc", "parent"; 59 resets = <&tegra_car 27>; 60 reset-names = "dc"; 61 62 iommus = <&mc TEGRA_SWGROUP_DC>; 63 64 nvidia,head = <0>; 65 }; 66 67 dc@54240000 { 68 compatible = "nvidia,tegra210-dc"; 69 reg = <0x0 0x54240000 0x0 0x00040000>; 70 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 71 clocks = <&tegra_car TEGRA210_CLK_DISP2>, 72 <&tegra_car TEGRA210_CLK_PLL_P>; 73 clock-names = "dc", "parent"; 74 resets = <&tegra_car 26>; 75 reset-names = "dc"; 76 77 iommus = <&mc TEGRA_SWGROUP_DCB>; 78 79 nvidia,head = <1>; 80 }; 81 82 dsi@54300000 { 83 compatible = "nvidia,tegra210-dsi"; 84 reg = <0x0 0x54300000 0x0 0x00040000>; 85 clocks = <&tegra_car TEGRA210_CLK_DSIA>, 86 <&tegra_car TEGRA210_CLK_DSIALP>, 87 <&tegra_car TEGRA210_CLK_PLL_D_OUT0>; 88 clock-names = "dsi", "lp", "parent"; 89 resets = <&tegra_car 48>; 90 reset-names = "dsi"; 91 nvidia,mipi-calibrate = <&mipi 0x0c0>; /* DSIA & DSIB pads */ 92 93 status = "disabled"; 94 95 #address-cells = <1>; 96 #size-cells = <0>; 97 }; 98 99 vic@54340000 { 100 compatible = "nvidia,tegra210-vic"; 101 reg = <0x0 0x54340000 0x0 0x00040000>; 102 status = "disabled"; 103 }; 104 105 nvjpg@54380000 { 106 compatible = "nvidia,tegra210-nvjpg"; 107 reg = <0x0 0x54380000 0x0 0x00040000>; 108 status = "disabled"; 109 }; 110 111 dsi@54400000 { 112 compatible = "nvidia,tegra210-dsi"; 113 reg = <0x0 0x54400000 0x0 0x00040000>; 114 clocks = <&tegra_car TEGRA210_CLK_DSIB>, 115 <&tegra_car TEGRA210_CLK_DSIBLP>, 116 <&tegra_car TEGRA210_CLK_PLL_D_OUT0>; 117 clock-names = "dsi", "lp", "parent"; 118 resets = <&tegra_car 82>; 119 reset-names = "dsi"; 120 nvidia,mipi-calibrate = <&mipi 0x300>; /* DSIC & DSID pads */ 121 122 status = "disabled"; 123 124 #address-cells = <1>; 125 #size-cells = <0>; 126 }; 127 128 nvdec@54480000 { 129 compatible = "nvidia,tegra210-nvdec"; 130 reg = <0x0 0x54480000 0x0 0x00040000>; 131 status = "disabled"; 132 }; 133 134 nvenc@544c0000 { 135 compatible = "nvidia,tegra210-nvenc"; 136 reg = <0x0 0x544c0000 0x0 0x00040000>; 137 status = "disabled"; 138 }; 139 140 tsec@54500000 { 141 compatible = "nvidia,tegra210-tsec"; 142 reg = <0x0 0x54500000 0x0 0x00040000>; 143 status = "disabled"; 144 }; 145 146 sor@54540000 { 147 compatible = "nvidia,tegra210-sor"; 148 reg = <0x0 0x54540000 0x0 0x00040000>; 149 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 150 clocks = <&tegra_car TEGRA210_CLK_SOR0>, 151 <&tegra_car TEGRA210_CLK_PLL_D_OUT0>, 152 <&tegra_car TEGRA210_CLK_PLL_DP>, 153 <&tegra_car TEGRA210_CLK_SOR_SAFE>; 154 clock-names = "sor", "parent", "dp", "safe"; 155 resets = <&tegra_car 182>; 156 reset-names = "sor"; 157 status = "disabled"; 158 }; 159 160 sor@54580000 { 161 compatible = "nvidia,tegra210-sor1"; 162 reg = <0x0 0x54580000 0x0 0x00040000>; 163 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 164 clocks = <&tegra_car TEGRA210_CLK_SOR1>, 165 <&tegra_car TEGRA210_CLK_PLL_D2_OUT0>, 166 <&tegra_car TEGRA210_CLK_PLL_DP>, 167 <&tegra_car TEGRA210_CLK_SOR_SAFE>; 168 clock-names = "sor", "parent", "dp", "safe"; 169 resets = <&tegra_car 183>; 170 reset-names = "sor"; 171 status = "disabled"; 172 }; 173 174 dpaux: dpaux@545c0000 { 175 compatible = "nvidia,tegra124-dpaux"; 176 reg = <0x0 0x545c0000 0x0 0x00040000>; 177 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 178 clocks = <&tegra_car TEGRA210_CLK_DPAUX>, 179 <&tegra_car TEGRA210_CLK_PLL_DP>; 180 clock-names = "dpaux", "parent"; 181 resets = <&tegra_car 181>; 182 reset-names = "dpaux"; 183 status = "disabled"; 184 }; 185 186 isp@54600000 { 187 compatible = "nvidia,tegra210-isp"; 188 reg = <0x0 0x54600000 0x0 0x00040000>; 189 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 190 status = "disabled"; 191 }; 192 193 isp@54680000 { 194 compatible = "nvidia,tegra210-isp"; 195 reg = <0x0 0x54680000 0x0 0x00040000>; 196 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 197 status = "disabled"; 198 }; 199 200 i2c@546c0000 { 201 compatible = "nvidia,tegra210-i2c-vi"; 202 reg = <0x0 0x546c0000 0x0 0x00040000>; 203 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 204 status = "disabled"; 205 }; 206 }; 207 208 gic: interrupt-controller@50041000 { 209 compatible = "arm,gic-400"; 210 #interrupt-cells = <3>; 211 interrupt-controller; 212 reg = <0x0 0x50041000 0x0 0x1000>, 213 <0x0 0x50042000 0x0 0x2000>, 214 <0x0 0x50044000 0x0 0x2000>, 215 <0x0 0x50046000 0x0 0x2000>; 216 interrupts = <GIC_PPI 9 217 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 218 interrupt-parent = <&gic>; 219 }; 220 221 gpu@57000000 { 222 compatible = "nvidia,gm20b"; 223 reg = <0x0 0x57000000 0x0 0x01000000>, 224 <0x0 0x58000000 0x0 0x01000000>; 225 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 226 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 227 interrupt-names = "stall", "nonstall"; 228 clocks = <&tegra_car TEGRA210_CLK_GPU>, 229 <&tegra_car TEGRA210_CLK_PLL_P_OUT5>; 230 clock-names = "gpu", "pwr"; 231 resets = <&tegra_car 184>; 232 reset-names = "gpu"; 233 status = "disabled"; 234 }; 235 236 lic: interrupt-controller@60004000 { 237 compatible = "nvidia,tegra210-ictlr"; 238 reg = <0x0 0x60004000 0x0 0x40>, /* primary controller */ 239 <0x0 0x60004100 0x0 0x40>, /* secondary controller */ 240 <0x0 0x60004200 0x0 0x40>, /* tertiary controller */ 241 <0x0 0x60004300 0x0 0x40>, /* quaternary controller */ 242 <0x0 0x60004400 0x0 0x40>, /* quinary controller */ 243 <0x0 0x60004500 0x0 0x40>; /* senary controller */ 244 interrupt-controller; 245 #interrupt-cells = <3>; 246 interrupt-parent = <&gic>; 247 }; 248 249 timer@60005000 { 250 compatible = "nvidia,tegra210-timer", "nvidia,tegra20-timer"; 251 reg = <0x0 0x60005000 0x0 0x400>; 252 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 253 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 254 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 255 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 256 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 257 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 258 clocks = <&tegra_car TEGRA210_CLK_TIMER>; 259 clock-names = "timer"; 260 }; 261 262 tegra_car: clock@60006000 { 263 compatible = "nvidia,tegra210-car"; 264 reg = <0x0 0x60006000 0x0 0x1000>; 265 #clock-cells = <1>; 266 #reset-cells = <1>; 267 }; 268 269 flow-controller@60007000 { 270 compatible = "nvidia,tegra210-flowctrl"; 271 reg = <0x0 0x60007000 0x0 0x1000>; 272 }; 273 274 gpio: gpio@6000d000 { 275 compatible = "nvidia,tegra210-gpio", "nvidia,tegra124-gpio", "nvidia,tegra30-gpio"; 276 reg = <0x0 0x6000d000 0x0 0x1000>; 277 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 278 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 279 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 280 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 281 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 282 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 283 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 284 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 285 #gpio-cells = <2>; 286 gpio-controller; 287 #interrupt-cells = <2>; 288 interrupt-controller; 289 }; 290 291 apbdma: dma@60020000 { 292 compatible = "nvidia,tegra210-apbdma", "nvidia,tegra148-apbdma"; 293 reg = <0x0 0x60020000 0x0 0x1400>; 294 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 295 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 296 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 297 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 298 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 299 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 300 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 301 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 302 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 303 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 304 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 305 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 306 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 307 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 308 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 309 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 310 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 311 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 312 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 313 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 314 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 315 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 316 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 317 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 318 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 319 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 320 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 321 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 322 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 323 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 324 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 325 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 326 clocks = <&tegra_car TEGRA210_CLK_APBDMA>; 327 clock-names = "dma"; 328 resets = <&tegra_car 34>; 329 reset-names = "dma"; 330 #dma-cells = <1>; 331 }; 332 333 apbmisc@70000800 { 334 compatible = "nvidia,tegra210-apbmisc", "nvidia,tegra20-apbmisc"; 335 reg = <0x0 0x70000800 0x0 0x64>, /* Chip revision */ 336 <0x0 0x7000e864 0x0 0x04>; /* Strapping options */ 337 }; 338 339 pinmux: pinmux@700008d4 { 340 compatible = "nvidia,tegra210-pinmux"; 341 reg = <0x0 0x700008d4 0x0 0x29c>, /* Pad control registers */ 342 <0x0 0x70003000 0x0 0x294>; /* Mux registers */ 343 }; 344 345 /* 346 * There are two serial driver i.e. 8250 based simple serial 347 * driver and APB DMA based serial driver for higher baudrate 348 * and performance. To enable the 8250 based driver, the compatible 349 * is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable 350 * the APB DMA based serial driver, the compatible is 351 * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart". 352 */ 353 uarta: serial@70006000 { 354 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; 355 reg = <0x0 0x70006000 0x0 0x40>; 356 reg-shift = <2>; 357 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 358 clocks = <&tegra_car TEGRA210_CLK_UARTA>; 359 clock-names = "serial"; 360 resets = <&tegra_car 6>; 361 reset-names = "serial"; 362 dmas = <&apbdma 8>, <&apbdma 8>; 363 dma-names = "rx", "tx"; 364 status = "disabled"; 365 }; 366 367 uartb: serial@70006040 { 368 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; 369 reg = <0x0 0x70006040 0x0 0x40>; 370 reg-shift = <2>; 371 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 372 clocks = <&tegra_car TEGRA210_CLK_UARTB>; 373 clock-names = "serial"; 374 resets = <&tegra_car 7>; 375 reset-names = "serial"; 376 dmas = <&apbdma 9>, <&apbdma 9>; 377 dma-names = "rx", "tx"; 378 status = "disabled"; 379 }; 380 381 uartc: serial@70006200 { 382 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; 383 reg = <0x0 0x70006200 0x0 0x40>; 384 reg-shift = <2>; 385 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 386 clocks = <&tegra_car TEGRA210_CLK_UARTC>; 387 clock-names = "serial"; 388 resets = <&tegra_car 55>; 389 reset-names = "serial"; 390 dmas = <&apbdma 10>, <&apbdma 10>; 391 dma-names = "rx", "tx"; 392 status = "disabled"; 393 }; 394 395 uartd: serial@70006300 { 396 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; 397 reg = <0x0 0x70006300 0x0 0x40>; 398 reg-shift = <2>; 399 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 400 clocks = <&tegra_car TEGRA210_CLK_UARTD>; 401 clock-names = "serial"; 402 resets = <&tegra_car 65>; 403 reset-names = "serial"; 404 dmas = <&apbdma 19>, <&apbdma 19>; 405 dma-names = "rx", "tx"; 406 status = "disabled"; 407 }; 408 409 pwm: pwm@7000a000 { 410 compatible = "nvidia,tegra210-pwm", "nvidia,tegra20-pwm"; 411 reg = <0x0 0x7000a000 0x0 0x100>; 412 #pwm-cells = <2>; 413 clocks = <&tegra_car TEGRA210_CLK_PWM>; 414 clock-names = "pwm"; 415 resets = <&tegra_car 17>; 416 reset-names = "pwm"; 417 status = "disabled"; 418 }; 419 420 i2c@7000c000 { 421 compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c"; 422 reg = <0x0 0x7000c000 0x0 0x100>; 423 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 424 #address-cells = <1>; 425 #size-cells = <0>; 426 clocks = <&tegra_car TEGRA210_CLK_I2C1>; 427 clock-names = "div-clk"; 428 resets = <&tegra_car 12>; 429 reset-names = "i2c"; 430 dmas = <&apbdma 21>, <&apbdma 21>; 431 dma-names = "rx", "tx"; 432 status = "disabled"; 433 }; 434 435 i2c@7000c400 { 436 compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c"; 437 reg = <0x0 0x7000c400 0x0 0x100>; 438 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 439 #address-cells = <1>; 440 #size-cells = <0>; 441 clocks = <&tegra_car TEGRA210_CLK_I2C2>; 442 clock-names = "div-clk"; 443 resets = <&tegra_car 54>; 444 reset-names = "i2c"; 445 dmas = <&apbdma 22>, <&apbdma 22>; 446 dma-names = "rx", "tx"; 447 status = "disabled"; 448 }; 449 450 i2c@7000c500 { 451 compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c"; 452 reg = <0x0 0x7000c500 0x0 0x100>; 453 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 454 #address-cells = <1>; 455 #size-cells = <0>; 456 clocks = <&tegra_car TEGRA210_CLK_I2C3>; 457 clock-names = "div-clk"; 458 resets = <&tegra_car 67>; 459 reset-names = "i2c"; 460 dmas = <&apbdma 23>, <&apbdma 23>; 461 dma-names = "rx", "tx"; 462 status = "disabled"; 463 }; 464 465 i2c@7000c700 { 466 compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c"; 467 reg = <0x0 0x7000c700 0x0 0x100>; 468 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 469 #address-cells = <1>; 470 #size-cells = <0>; 471 clocks = <&tegra_car TEGRA210_CLK_I2C4>; 472 clock-names = "div-clk"; 473 resets = <&tegra_car 103>; 474 reset-names = "i2c"; 475 dmas = <&apbdma 26>, <&apbdma 26>; 476 dma-names = "rx", "tx"; 477 status = "disabled"; 478 }; 479 480 i2c@7000d000 { 481 compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c"; 482 reg = <0x0 0x7000d000 0x0 0x100>; 483 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 484 #address-cells = <1>; 485 #size-cells = <0>; 486 clocks = <&tegra_car TEGRA210_CLK_I2C5>; 487 clock-names = "div-clk"; 488 resets = <&tegra_car 47>; 489 reset-names = "i2c"; 490 dmas = <&apbdma 24>, <&apbdma 24>; 491 dma-names = "rx", "tx"; 492 status = "disabled"; 493 }; 494 495 i2c@7000d100 { 496 compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c"; 497 reg = <0x0 0x7000d100 0x0 0x100>; 498 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 499 #address-cells = <1>; 500 #size-cells = <0>; 501 clocks = <&tegra_car TEGRA210_CLK_I2C6>; 502 clock-names = "div-clk"; 503 resets = <&tegra_car 166>; 504 reset-names = "i2c"; 505 dmas = <&apbdma 30>, <&apbdma 30>; 506 dma-names = "rx", "tx"; 507 status = "disabled"; 508 }; 509 510 spi@7000d400 { 511 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 512 reg = <0x0 0x7000d400 0x0 0x200>; 513 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 514 #address-cells = <1>; 515 #size-cells = <0>; 516 clocks = <&tegra_car TEGRA210_CLK_SBC1>; 517 clock-names = "spi"; 518 resets = <&tegra_car 41>; 519 reset-names = "spi"; 520 dmas = <&apbdma 15>, <&apbdma 15>; 521 dma-names = "rx", "tx"; 522 status = "disabled"; 523 }; 524 525 spi@7000d600 { 526 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 527 reg = <0x0 0x7000d600 0x0 0x200>; 528 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 529 #address-cells = <1>; 530 #size-cells = <0>; 531 clocks = <&tegra_car TEGRA210_CLK_SBC2>; 532 clock-names = "spi"; 533 resets = <&tegra_car 44>; 534 reset-names = "spi"; 535 dmas = <&apbdma 16>, <&apbdma 16>; 536 dma-names = "rx", "tx"; 537 status = "disabled"; 538 }; 539 540 spi@7000d800 { 541 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 542 reg = <0x0 0x7000d800 0x0 0x200>; 543 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 544 #address-cells = <1>; 545 #size-cells = <0>; 546 clocks = <&tegra_car TEGRA210_CLK_SBC3>; 547 clock-names = "spi"; 548 resets = <&tegra_car 46>; 549 reset-names = "spi"; 550 dmas = <&apbdma 17>, <&apbdma 17>; 551 dma-names = "rx", "tx"; 552 status = "disabled"; 553 }; 554 555 spi@7000da00 { 556 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 557 reg = <0x0 0x7000da00 0x0 0x200>; 558 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 559 #address-cells = <1>; 560 #size-cells = <0>; 561 clocks = <&tegra_car TEGRA210_CLK_SBC4>; 562 clock-names = "spi"; 563 resets = <&tegra_car 68>; 564 reset-names = "spi"; 565 dmas = <&apbdma 18>, <&apbdma 18>; 566 dma-names = "rx", "tx"; 567 status = "disabled"; 568 }; 569 570 rtc@7000e000 { 571 compatible = "nvidia,tegra210-rtc", "nvidia,tegra20-rtc"; 572 reg = <0x0 0x7000e000 0x0 0x100>; 573 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 574 clocks = <&tegra_car TEGRA210_CLK_RTC>; 575 clock-names = "rtc"; 576 }; 577 578 pmc: pmc@7000e400 { 579 compatible = "nvidia,tegra210-pmc"; 580 reg = <0x0 0x7000e400 0x0 0x400>; 581 clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>; 582 clock-names = "pclk", "clk32k_in"; 583 }; 584 585 fuse@7000f800 { 586 compatible = "nvidia,tegra210-efuse"; 587 reg = <0x0 0x7000f800 0x0 0x400>; 588 clocks = <&tegra_car TEGRA210_CLK_FUSE>; 589 clock-names = "fuse"; 590 resets = <&tegra_car 39>; 591 reset-names = "fuse"; 592 }; 593 594 mc: memory-controller@70019000 { 595 compatible = "nvidia,tegra210-mc"; 596 reg = <0x0 0x70019000 0x0 0x1000>; 597 clocks = <&tegra_car TEGRA210_CLK_MC>; 598 clock-names = "mc"; 599 600 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 601 602 #iommu-cells = <1>; 603 }; 604 605 hda@70030000 { 606 compatible = "nvidia,tegra210-hda", "nvidia,tegra30-hda"; 607 reg = <0x0 0x70030000 0x0 0x10000>; 608 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 609 clocks = <&tegra_car TEGRA210_CLK_HDA>, 610 <&tegra_car TEGRA210_CLK_HDA2HDMI>, 611 <&tegra_car TEGRA210_CLK_HDA2CODEC_2X>; 612 clock-names = "hda", "hda2hdmi", "hda2codec_2x"; 613 resets = <&tegra_car 125>, /* hda */ 614 <&tegra_car 128>, /* hda2hdmi */ 615 <&tegra_car 111>; /* hda2codec_2x */ 616 reset-names = "hda", "hda2hdmi", "hda2codec_2x"; 617 status = "disabled"; 618 }; 619 620 sdhci@700b0000 { 621 compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci"; 622 reg = <0x0 0x700b0000 0x0 0x200>; 623 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 624 clocks = <&tegra_car TEGRA210_CLK_SDMMC1>; 625 clock-names = "sdhci"; 626 resets = <&tegra_car 14>; 627 reset-names = "sdhci"; 628 status = "disabled"; 629 }; 630 631 sdhci@700b0200 { 632 compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci"; 633 reg = <0x0 0x700b0200 0x0 0x200>; 634 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 635 clocks = <&tegra_car TEGRA210_CLK_SDMMC2>; 636 clock-names = "sdhci"; 637 resets = <&tegra_car 9>; 638 reset-names = "sdhci"; 639 status = "disabled"; 640 }; 641 642 sdhci@700b0400 { 643 compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci"; 644 reg = <0x0 0x700b0400 0x0 0x200>; 645 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 646 clocks = <&tegra_car TEGRA210_CLK_SDMMC3>; 647 clock-names = "sdhci"; 648 resets = <&tegra_car 69>; 649 reset-names = "sdhci"; 650 status = "disabled"; 651 }; 652 653 sdhci@700b0600 { 654 compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci"; 655 reg = <0x0 0x700b0600 0x0 0x200>; 656 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 657 clocks = <&tegra_car TEGRA210_CLK_SDMMC4>; 658 clock-names = "sdhci"; 659 resets = <&tegra_car 15>; 660 reset-names = "sdhci"; 661 status = "disabled"; 662 }; 663 664 mipi: mipi@700e3000 { 665 compatible = "nvidia,tegra210-mipi"; 666 reg = <0x0 0x700e3000 0x0 0x100>; 667 clocks = <&tegra_car TEGRA210_CLK_MIPI_CAL>; 668 clock-names = "mipi-cal"; 669 #nvidia,mipi-calibrate-cells = <1>; 670 }; 671 672 spi@70410000 { 673 compatible = "nvidia,tegra210-qspi"; 674 reg = <0x0 0x70410000 0x0 0x1000>; 675 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 676 #address-cells = <1>; 677 #size-cells = <0>; 678 clocks = <&tegra_car TEGRA210_CLK_QSPI>; 679 clock-names = "qspi"; 680 resets = <&tegra_car 211>; 681 reset-names = "qspi"; 682 dmas = <&apbdma 5>, <&apbdma 5>; 683 dma-names = "rx", "tx"; 684 status = "disabled"; 685 }; 686 687 usb@7d000000 { 688 compatible = "nvidia,tegra210-ehci", "nvidia,tegra30-ehci", "usb-ehci"; 689 reg = <0x0 0x7d000000 0x0 0x4000>; 690 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 691 phy_type = "utmi"; 692 clocks = <&tegra_car TEGRA210_CLK_USBD>; 693 clock-names = "usb"; 694 resets = <&tegra_car 22>; 695 reset-names = "usb"; 696 nvidia,phy = <&phy1>; 697 status = "disabled"; 698 }; 699 700 phy1: usb-phy@7d000000 { 701 compatible = "nvidia,tegra210-usb-phy", "nvidia,tegra30-usb-phy"; 702 reg = <0x0 0x7d000000 0x0 0x4000>, 703 <0x0 0x7d000000 0x0 0x4000>; 704 phy_type = "utmi"; 705 clocks = <&tegra_car TEGRA210_CLK_USBD>, 706 <&tegra_car TEGRA210_CLK_PLL_U>, 707 <&tegra_car TEGRA210_CLK_USBD>; 708 clock-names = "reg", "pll_u", "utmi-pads"; 709 resets = <&tegra_car 22>, <&tegra_car 22>; 710 reset-names = "usb", "utmi-pads"; 711 nvidia,hssync-start-delay = <0>; 712 nvidia,idle-wait-delay = <17>; 713 nvidia,elastic-limit = <16>; 714 nvidia,term-range-adj = <6>; 715 nvidia,xcvr-setup = <9>; 716 nvidia,xcvr-lsfslew = <0>; 717 nvidia,xcvr-lsrslew = <3>; 718 nvidia,hssquelch-level = <2>; 719 nvidia,hsdiscon-level = <5>; 720 nvidia,xcvr-hsslew = <12>; 721 nvidia,has-utmi-pad-registers; 722 status = "disabled"; 723 }; 724 725 usb@7d004000 { 726 compatible = "nvidia,tegra210-ehci", "nvidia,tegra30-ehci", "usb-ehci"; 727 reg = <0x0 0x7d004000 0x0 0x4000>; 728 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 729 phy_type = "utmi"; 730 clocks = <&tegra_car TEGRA210_CLK_USB2>; 731 clock-names = "usb"; 732 resets = <&tegra_car 58>; 733 reset-names = "usb"; 734 nvidia,phy = <&phy2>; 735 status = "disabled"; 736 }; 737 738 phy2: usb-phy@7d004000 { 739 compatible = "nvidia,tegra210-usb-phy", "nvidia,tegra30-usb-phy"; 740 reg = <0x0 0x7d004000 0x0 0x4000>, 741 <0x0 0x7d000000 0x0 0x4000>; 742 phy_type = "utmi"; 743 clocks = <&tegra_car TEGRA210_CLK_USB2>, 744 <&tegra_car TEGRA210_CLK_PLL_U>, 745 <&tegra_car TEGRA210_CLK_USBD>; 746 clock-names = "reg", "pll_u", "utmi-pads"; 747 resets = <&tegra_car 58>, <&tegra_car 22>; 748 reset-names = "usb", "utmi-pads"; 749 nvidia,hssync-start-delay = <0>; 750 nvidia,idle-wait-delay = <17>; 751 nvidia,elastic-limit = <16>; 752 nvidia,term-range-adj = <6>; 753 nvidia,xcvr-setup = <9>; 754 nvidia,xcvr-lsfslew = <0>; 755 nvidia,xcvr-lsrslew = <3>; 756 nvidia,hssquelch-level = <2>; 757 nvidia,hsdiscon-level = <5>; 758 nvidia,xcvr-hsslew = <12>; 759 status = "disabled"; 760 }; 761 762 cpus { 763 #address-cells = <1>; 764 #size-cells = <0>; 765 766 cpu@0 { 767 device_type = "cpu"; 768 compatible = "arm,cortex-a57"; 769 reg = <0>; 770 }; 771 772 cpu@1 { 773 device_type = "cpu"; 774 compatible = "arm,cortex-a57"; 775 reg = <1>; 776 }; 777 778 cpu@2 { 779 device_type = "cpu"; 780 compatible = "arm,cortex-a57"; 781 reg = <2>; 782 }; 783 784 cpu@3 { 785 device_type = "cpu"; 786 compatible = "arm,cortex-a57"; 787 reg = <3>; 788 }; 789 }; 790 791 timer { 792 compatible = "arm,armv8-timer"; 793 interrupts = <GIC_PPI 13 794 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 795 <GIC_PPI 14 796 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 797 <GIC_PPI 11 798 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 799 <GIC_PPI 10 800 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 801 interrupt-parent = <&gic>; 802 }; 803}; 804