1#include <dt-bindings/clock/tegra210-car.h> 2#include <dt-bindings/gpio/tegra-gpio.h> 3#include <dt-bindings/memory/tegra210-mc.h> 4#include <dt-bindings/pinctrl/pinctrl-tegra.h> 5#include <dt-bindings/interrupt-controller/arm-gic.h> 6 7/ { 8 compatible = "nvidia,tegra210"; 9 interrupt-parent = <&lic>; 10 #address-cells = <2>; 11 #size-cells = <2>; 12 13 host1x@0,50000000 { 14 compatible = "nvidia,tegra210-host1x", "simple-bus"; 15 reg = <0x0 0x50000000 0x0 0x00034000>; 16 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */ 17 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */ 18 clocks = <&tegra_car TEGRA210_CLK_HOST1X>; 19 clock-names = "host1x"; 20 resets = <&tegra_car 28>; 21 reset-names = "host1x"; 22 23 #address-cells = <2>; 24 #size-cells = <2>; 25 26 ranges = <0x0 0x54000000 0x0 0x54000000 0x0 0x01000000>; 27 28 dpaux1: dpaux@0,54040000 { 29 compatible = "nvidia,tegra210-dpaux"; 30 reg = <0x0 0x54040000 0x0 0x00040000>; 31 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 32 clocks = <&tegra_car TEGRA210_CLK_DPAUX1>, 33 <&tegra_car TEGRA210_CLK_PLL_DP>; 34 clock-names = "dpaux", "parent"; 35 resets = <&tegra_car 207>; 36 reset-names = "dpaux"; 37 status = "disabled"; 38 }; 39 40 vi@0,54080000 { 41 compatible = "nvidia,tegra210-vi"; 42 reg = <0x0 0x54080000 0x0 0x00040000>; 43 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 44 status = "disabled"; 45 }; 46 47 tsec@0,54100000 { 48 compatible = "nvidia,tegra210-tsec"; 49 reg = <0x0 0x54100000 0x0 0x00040000>; 50 }; 51 52 dc@0,54200000 { 53 compatible = "nvidia,tegra210-dc"; 54 reg = <0x0 0x54200000 0x0 0x00040000>; 55 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 56 clocks = <&tegra_car TEGRA210_CLK_DISP1>, 57 <&tegra_car TEGRA210_CLK_PLL_P>; 58 clock-names = "dc", "parent"; 59 resets = <&tegra_car 27>; 60 reset-names = "dc"; 61 62 iommus = <&mc TEGRA_SWGROUP_DC>; 63 64 nvidia,head = <0>; 65 }; 66 67 dc@0,54240000 { 68 compatible = "nvidia,tegra210-dc"; 69 reg = <0x0 0x54240000 0x0 0x00040000>; 70 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 71 clocks = <&tegra_car TEGRA210_CLK_DISP2>, 72 <&tegra_car TEGRA210_CLK_PLL_P>; 73 clock-names = "dc", "parent"; 74 resets = <&tegra_car 26>; 75 reset-names = "dc"; 76 77 iommus = <&mc TEGRA_SWGROUP_DCB>; 78 79 nvidia,head = <1>; 80 }; 81 82 dsi@0,54300000 { 83 compatible = "nvidia,tegra210-dsi"; 84 reg = <0x0 0x54300000 0x0 0x00040000>; 85 clocks = <&tegra_car TEGRA210_CLK_DSIA>, 86 <&tegra_car TEGRA210_CLK_DSIALP>, 87 <&tegra_car TEGRA210_CLK_PLL_D_OUT0>; 88 clock-names = "dsi", "lp", "parent"; 89 resets = <&tegra_car 48>; 90 reset-names = "dsi"; 91 nvidia,mipi-calibrate = <&mipi 0x0c0>; /* DSIA & DSIB pads */ 92 93 status = "disabled"; 94 95 #address-cells = <1>; 96 #size-cells = <0>; 97 }; 98 99 vic@0,54340000 { 100 compatible = "nvidia,tegra210-vic"; 101 reg = <0x0 0x54340000 0x0 0x00040000>; 102 status = "disabled"; 103 }; 104 105 nvjpg@0,54380000 { 106 compatible = "nvidia,tegra210-nvjpg"; 107 reg = <0x0 0x54380000 0x0 0x00040000>; 108 status = "disabled"; 109 }; 110 111 dsi@0,54400000 { 112 compatible = "nvidia,tegra210-dsi"; 113 reg = <0x0 0x54400000 0x0 0x00040000>; 114 clocks = <&tegra_car TEGRA210_CLK_DSIB>, 115 <&tegra_car TEGRA210_CLK_DSIBLP>, 116 <&tegra_car TEGRA210_CLK_PLL_D_OUT0>; 117 clock-names = "dsi", "lp", "parent"; 118 resets = <&tegra_car 82>; 119 reset-names = "dsi"; 120 nvidia,mipi-calibrate = <&mipi 0x300>; /* DSIC & DSID pads */ 121 122 status = "disabled"; 123 124 #address-cells = <1>; 125 #size-cells = <0>; 126 }; 127 128 nvdec@0,54480000 { 129 compatible = "nvidia,tegra210-nvdec"; 130 reg = <0x0 0x54480000 0x0 0x00040000>; 131 status = "disabled"; 132 }; 133 134 nvenc@0,544c0000 { 135 compatible = "nvidia,tegra210-nvenc"; 136 reg = <0x0 0x544c0000 0x0 0x00040000>; 137 status = "disabled"; 138 }; 139 140 tsec@0,54500000 { 141 compatible = "nvidia,tegra210-tsec"; 142 reg = <0x0 0x54500000 0x0 0x00040000>; 143 status = "disabled"; 144 }; 145 146 sor@0,54540000 { 147 compatible = "nvidia,tegra210-sor"; 148 reg = <0x0 0x54540000 0x0 0x00040000>; 149 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 150 clocks = <&tegra_car TEGRA210_CLK_SOR0>, 151 <&tegra_car TEGRA210_CLK_PLL_D_OUT0>, 152 <&tegra_car TEGRA210_CLK_PLL_DP>, 153 <&tegra_car TEGRA210_CLK_SOR_SAFE>; 154 clock-names = "sor", "parent", "dp", "safe"; 155 resets = <&tegra_car 182>; 156 reset-names = "sor"; 157 status = "disabled"; 158 }; 159 160 sor@0,54580000 { 161 compatible = "nvidia,tegra210-sor1"; 162 reg = <0x0 0x54580000 0x0 0x00040000>; 163 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 164 clocks = <&tegra_car TEGRA210_CLK_SOR1>, 165 <&tegra_car TEGRA210_CLK_PLL_D2_OUT0>, 166 <&tegra_car TEGRA210_CLK_PLL_DP>, 167 <&tegra_car TEGRA210_CLK_SOR_SAFE>; 168 clock-names = "sor", "parent", "dp", "safe"; 169 resets = <&tegra_car 183>; 170 reset-names = "sor"; 171 status = "disabled"; 172 }; 173 174 dpaux: dpaux@0,545c0000 { 175 compatible = "nvidia,tegra124-dpaux"; 176 reg = <0x0 0x545c0000 0x0 0x00040000>; 177 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 178 clocks = <&tegra_car TEGRA210_CLK_DPAUX>, 179 <&tegra_car TEGRA210_CLK_PLL_DP>; 180 clock-names = "dpaux", "parent"; 181 resets = <&tegra_car 181>; 182 reset-names = "dpaux"; 183 status = "disabled"; 184 }; 185 186 isp@0,54600000 { 187 compatible = "nvidia,tegra210-isp"; 188 reg = <0x0 0x54600000 0x0 0x00040000>; 189 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 190 status = "disabled"; 191 }; 192 193 isp@0,54680000 { 194 compatible = "nvidia,tegra210-isp"; 195 reg = <0x0 0x54680000 0x0 0x00040000>; 196 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 197 status = "disabled"; 198 }; 199 200 i2c@0,546c0000 { 201 compatible = "nvidia,tegra210-i2c-vi"; 202 reg = <0x0 0x546c0000 0x0 0x00040000>; 203 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 204 status = "disabled"; 205 }; 206 }; 207 208 gic: interrupt-controller@0,50041000 { 209 compatible = "arm,gic-400"; 210 #interrupt-cells = <3>; 211 interrupt-controller; 212 reg = <0x0 0x50041000 0x0 0x1000>, 213 <0x0 0x50042000 0x0 0x2000>, 214 <0x0 0x50044000 0x0 0x2000>, 215 <0x0 0x50046000 0x0 0x2000>; 216 interrupts = <GIC_PPI 9 217 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 218 interrupt-parent = <&gic>; 219 }; 220 221 gpu@0,57000000 { 222 compatible = "nvidia,gm20b"; 223 reg = <0x0 0x57000000 0x0 0x01000000>, 224 <0x0 0x58000000 0x0 0x01000000>; 225 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 226 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 227 interrupt-names = "stall", "nonstall"; 228 clocks = <&tegra_car TEGRA210_CLK_GPU>, 229 <&tegra_car TEGRA210_CLK_PLL_P_OUT5>, 230 <&tegra_car TEGRA210_CLK_PLL_G_REF>; 231 clock-names = "gpu", "pwr", "ref"; 232 resets = <&tegra_car 184>; 233 reset-names = "gpu"; 234 status = "disabled"; 235 }; 236 237 lic: interrupt-controller@0,60004000 { 238 compatible = "nvidia,tegra210-ictlr"; 239 reg = <0x0 0x60004000 0x0 0x40>, /* primary controller */ 240 <0x0 0x60004100 0x0 0x40>, /* secondary controller */ 241 <0x0 0x60004200 0x0 0x40>, /* tertiary controller */ 242 <0x0 0x60004300 0x0 0x40>, /* quaternary controller */ 243 <0x0 0x60004400 0x0 0x40>, /* quinary controller */ 244 <0x0 0x60004500 0x0 0x40>; /* senary controller */ 245 interrupt-controller; 246 #interrupt-cells = <3>; 247 interrupt-parent = <&gic>; 248 }; 249 250 timer@0,60005000 { 251 compatible = "nvidia,tegra210-timer", "nvidia,tegra20-timer"; 252 reg = <0x0 0x60005000 0x0 0x400>; 253 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 254 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 255 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 256 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 257 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 258 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 259 clocks = <&tegra_car TEGRA210_CLK_TIMER>; 260 clock-names = "timer"; 261 }; 262 263 tegra_car: clock@0,60006000 { 264 compatible = "nvidia,tegra210-car"; 265 reg = <0x0 0x60006000 0x0 0x1000>; 266 #clock-cells = <1>; 267 #reset-cells = <1>; 268 }; 269 270 flow-controller@0,60007000 { 271 compatible = "nvidia,tegra210-flowctrl"; 272 reg = <0x0 0x60007000 0x0 0x1000>; 273 }; 274 275 gpio: gpio@0,6000d000 { 276 compatible = "nvidia,tegra210-gpio", "nvidia,tegra124-gpio", "nvidia,tegra30-gpio"; 277 reg = <0x0 0x6000d000 0x0 0x1000>; 278 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 279 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 280 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 281 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 282 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 283 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 284 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 285 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 286 #gpio-cells = <2>; 287 gpio-controller; 288 #interrupt-cells = <2>; 289 interrupt-controller; 290 }; 291 292 apbdma: dma@0,60020000 { 293 compatible = "nvidia,tegra210-apbdma", "nvidia,tegra148-apbdma"; 294 reg = <0x0 0x60020000 0x0 0x1400>; 295 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 296 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 297 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 298 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 299 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 300 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 301 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 302 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 303 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 304 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 305 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 306 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 307 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 308 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 309 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 310 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 311 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 312 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 313 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 314 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 315 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 316 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 317 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 318 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 319 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 320 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 321 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 322 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 323 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 324 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 325 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 326 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 327 clocks = <&tegra_car TEGRA210_CLK_APBDMA>; 328 clock-names = "dma"; 329 resets = <&tegra_car 34>; 330 reset-names = "dma"; 331 #dma-cells = <1>; 332 }; 333 334 apbmisc@0,70000800 { 335 compatible = "nvidia,tegra210-apbmisc", "nvidia,tegra20-apbmisc"; 336 reg = <0x0 0x70000800 0x0 0x64>, /* Chip revision */ 337 <0x0 0x7000e864 0x0 0x04>; /* Strapping options */ 338 }; 339 340 pinmux: pinmux@0,700008d4 { 341 compatible = "nvidia,tegra210-pinmux"; 342 reg = <0x0 0x700008d4 0x0 0x29c>, /* Pad control registers */ 343 <0x0 0x70003000 0x0 0x294>; /* Mux registers */ 344 }; 345 346 /* 347 * There are two serial driver i.e. 8250 based simple serial 348 * driver and APB DMA based serial driver for higher baudrate 349 * and performance. To enable the 8250 based driver, the compatible 350 * is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable 351 * the APB DMA based serial driver, the comptible is 352 * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart". 353 */ 354 uarta: serial@0,70006000 { 355 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; 356 reg = <0x0 0x70006000 0x0 0x40>; 357 reg-shift = <2>; 358 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 359 clocks = <&tegra_car TEGRA210_CLK_UARTA>; 360 clock-names = "serial"; 361 resets = <&tegra_car 6>; 362 reset-names = "serial"; 363 dmas = <&apbdma 8>, <&apbdma 8>; 364 dma-names = "rx", "tx"; 365 status = "disabled"; 366 }; 367 368 uartb: serial@0,70006040 { 369 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; 370 reg = <0x0 0x70006040 0x0 0x40>; 371 reg-shift = <2>; 372 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 373 clocks = <&tegra_car TEGRA210_CLK_UARTB>; 374 clock-names = "serial"; 375 resets = <&tegra_car 7>; 376 reset-names = "serial"; 377 dmas = <&apbdma 9>, <&apbdma 9>; 378 dma-names = "rx", "tx"; 379 status = "disabled"; 380 }; 381 382 uartc: serial@0,70006200 { 383 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; 384 reg = <0x0 0x70006200 0x0 0x40>; 385 reg-shift = <2>; 386 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 387 clocks = <&tegra_car TEGRA210_CLK_UARTC>; 388 clock-names = "serial"; 389 resets = <&tegra_car 55>; 390 reset-names = "serial"; 391 dmas = <&apbdma 10>, <&apbdma 10>; 392 dma-names = "rx", "tx"; 393 status = "disabled"; 394 }; 395 396 uartd: serial@0,70006300 { 397 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; 398 reg = <0x0 0x70006300 0x0 0x40>; 399 reg-shift = <2>; 400 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 401 clocks = <&tegra_car TEGRA210_CLK_UARTD>; 402 clock-names = "serial"; 403 resets = <&tegra_car 65>; 404 reset-names = "serial"; 405 dmas = <&apbdma 19>, <&apbdma 19>; 406 dma-names = "rx", "tx"; 407 status = "disabled"; 408 }; 409 410 pwm: pwm@0,7000a000 { 411 compatible = "nvidia,tegra210-pwm", "nvidia,tegra20-pwm"; 412 reg = <0x0 0x7000a000 0x0 0x100>; 413 #pwm-cells = <2>; 414 clocks = <&tegra_car TEGRA210_CLK_PWM>; 415 clock-names = "pwm"; 416 resets = <&tegra_car 17>; 417 reset-names = "pwm"; 418 status = "disabled"; 419 }; 420 421 i2c@0,7000c000 { 422 compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c"; 423 reg = <0x0 0x7000c000 0x0 0x100>; 424 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 425 #address-cells = <1>; 426 #size-cells = <0>; 427 clocks = <&tegra_car TEGRA210_CLK_I2C1>; 428 clock-names = "div-clk"; 429 resets = <&tegra_car 12>; 430 reset-names = "i2c"; 431 dmas = <&apbdma 21>, <&apbdma 21>; 432 dma-names = "rx", "tx"; 433 status = "disabled"; 434 }; 435 436 i2c@0,7000c400 { 437 compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c"; 438 reg = <0x0 0x7000c400 0x0 0x100>; 439 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 440 #address-cells = <1>; 441 #size-cells = <0>; 442 clocks = <&tegra_car TEGRA210_CLK_I2C2>; 443 clock-names = "div-clk"; 444 resets = <&tegra_car 54>; 445 reset-names = "i2c"; 446 dmas = <&apbdma 22>, <&apbdma 22>; 447 dma-names = "rx", "tx"; 448 status = "disabled"; 449 }; 450 451 i2c@0,7000c500 { 452 compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c"; 453 reg = <0x0 0x7000c500 0x0 0x100>; 454 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 455 #address-cells = <1>; 456 #size-cells = <0>; 457 clocks = <&tegra_car TEGRA210_CLK_I2C3>; 458 clock-names = "div-clk"; 459 resets = <&tegra_car 67>; 460 reset-names = "i2c"; 461 dmas = <&apbdma 23>, <&apbdma 23>; 462 dma-names = "rx", "tx"; 463 status = "disabled"; 464 }; 465 466 i2c@0,7000c700 { 467 compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c"; 468 reg = <0x0 0x7000c700 0x0 0x100>; 469 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 470 #address-cells = <1>; 471 #size-cells = <0>; 472 clocks = <&tegra_car TEGRA210_CLK_I2C4>; 473 clock-names = "div-clk"; 474 resets = <&tegra_car 103>; 475 reset-names = "i2c"; 476 dmas = <&apbdma 26>, <&apbdma 26>; 477 dma-names = "rx", "tx"; 478 status = "disabled"; 479 }; 480 481 i2c@0,7000d000 { 482 compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c"; 483 reg = <0x0 0x7000d000 0x0 0x100>; 484 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 485 #address-cells = <1>; 486 #size-cells = <0>; 487 clocks = <&tegra_car TEGRA210_CLK_I2C5>; 488 clock-names = "div-clk"; 489 resets = <&tegra_car 47>; 490 reset-names = "i2c"; 491 dmas = <&apbdma 24>, <&apbdma 24>; 492 dma-names = "rx", "tx"; 493 status = "disabled"; 494 }; 495 496 i2c@0,7000d100 { 497 compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c"; 498 reg = <0x0 0x7000d100 0x0 0x100>; 499 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 500 #address-cells = <1>; 501 #size-cells = <0>; 502 clocks = <&tegra_car TEGRA210_CLK_I2C6>; 503 clock-names = "div-clk"; 504 resets = <&tegra_car 166>; 505 reset-names = "i2c"; 506 dmas = <&apbdma 30>, <&apbdma 30>; 507 dma-names = "rx", "tx"; 508 status = "disabled"; 509 }; 510 511 spi@0,7000d400 { 512 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 513 reg = <0x0 0x7000d400 0x0 0x200>; 514 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 515 #address-cells = <1>; 516 #size-cells = <0>; 517 clocks = <&tegra_car TEGRA210_CLK_SBC1>; 518 clock-names = "spi"; 519 resets = <&tegra_car 41>; 520 reset-names = "spi"; 521 dmas = <&apbdma 15>, <&apbdma 15>; 522 dma-names = "rx", "tx"; 523 status = "disabled"; 524 }; 525 526 spi@0,7000d600 { 527 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 528 reg = <0x0 0x7000d600 0x0 0x200>; 529 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 530 #address-cells = <1>; 531 #size-cells = <0>; 532 clocks = <&tegra_car TEGRA210_CLK_SBC2>; 533 clock-names = "spi"; 534 resets = <&tegra_car 44>; 535 reset-names = "spi"; 536 dmas = <&apbdma 16>, <&apbdma 16>; 537 dma-names = "rx", "tx"; 538 status = "disabled"; 539 }; 540 541 spi@0,7000d800 { 542 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 543 reg = <0x0 0x7000d800 0x0 0x200>; 544 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 545 #address-cells = <1>; 546 #size-cells = <0>; 547 clocks = <&tegra_car TEGRA210_CLK_SBC3>; 548 clock-names = "spi"; 549 resets = <&tegra_car 46>; 550 reset-names = "spi"; 551 dmas = <&apbdma 17>, <&apbdma 17>; 552 dma-names = "rx", "tx"; 553 status = "disabled"; 554 }; 555 556 spi@0,7000da00 { 557 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 558 reg = <0x0 0x7000da00 0x0 0x200>; 559 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 560 #address-cells = <1>; 561 #size-cells = <0>; 562 clocks = <&tegra_car TEGRA210_CLK_SBC4>; 563 clock-names = "spi"; 564 resets = <&tegra_car 68>; 565 reset-names = "spi"; 566 dmas = <&apbdma 18>, <&apbdma 18>; 567 dma-names = "rx", "tx"; 568 status = "disabled"; 569 }; 570 571 rtc@0,7000e000 { 572 compatible = "nvidia,tegra210-rtc", "nvidia,tegra20-rtc"; 573 reg = <0x0 0x7000e000 0x0 0x100>; 574 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 575 clocks = <&tegra_car TEGRA210_CLK_RTC>; 576 clock-names = "rtc"; 577 }; 578 579 pmc: pmc@0,7000e400 { 580 compatible = "nvidia,tegra210-pmc"; 581 reg = <0x0 0x7000e400 0x0 0x400>; 582 clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>; 583 clock-names = "pclk", "clk32k_in"; 584 585 #power-domain-cells = <1>; 586 }; 587 588 fuse@0,7000f800 { 589 compatible = "nvidia,tegra210-efuse"; 590 reg = <0x0 0x7000f800 0x0 0x400>; 591 clocks = <&tegra_car TEGRA210_CLK_FUSE>; 592 clock-names = "fuse"; 593 resets = <&tegra_car 39>; 594 reset-names = "fuse"; 595 }; 596 597 mc: memory-controller@0,70019000 { 598 compatible = "nvidia,tegra210-mc"; 599 reg = <0x0 0x70019000 0x0 0x1000>; 600 clocks = <&tegra_car TEGRA210_CLK_MC>; 601 clock-names = "mc"; 602 603 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 604 605 #iommu-cells = <1>; 606 }; 607 608 hda@0,70030000 { 609 compatible = "nvidia,tegra210-hda", "nvidia,tegra30-hda"; 610 reg = <0x0 0x70030000 0x0 0x10000>; 611 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 612 clocks = <&tegra_car TEGRA210_CLK_HDA>, 613 <&tegra_car TEGRA210_CLK_HDA2HDMI>, 614 <&tegra_car TEGRA210_CLK_HDA2CODEC_2X>; 615 clock-names = "hda", "hda2hdmi", "hda2codec_2x"; 616 resets = <&tegra_car 125>, /* hda */ 617 <&tegra_car 128>, /* hda2hdmi */ 618 <&tegra_car 111>; /* hda2codec_2x */ 619 reset-names = "hda", "hda2hdmi", "hda2codec_2x"; 620 status = "disabled"; 621 }; 622 623 sdhci@0,700b0000 { 624 compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci"; 625 reg = <0x0 0x700b0000 0x0 0x200>; 626 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 627 clocks = <&tegra_car TEGRA210_CLK_SDMMC1>; 628 clock-names = "sdhci"; 629 resets = <&tegra_car 14>; 630 reset-names = "sdhci"; 631 status = "disabled"; 632 }; 633 634 sdhci@0,700b0200 { 635 compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci"; 636 reg = <0x0 0x700b0200 0x0 0x200>; 637 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 638 clocks = <&tegra_car TEGRA210_CLK_SDMMC2>; 639 clock-names = "sdhci"; 640 resets = <&tegra_car 9>; 641 reset-names = "sdhci"; 642 status = "disabled"; 643 }; 644 645 sdhci@0,700b0400 { 646 compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci"; 647 reg = <0x0 0x700b0400 0x0 0x200>; 648 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 649 clocks = <&tegra_car TEGRA210_CLK_SDMMC3>; 650 clock-names = "sdhci"; 651 resets = <&tegra_car 69>; 652 reset-names = "sdhci"; 653 status = "disabled"; 654 }; 655 656 sdhci@0,700b0600 { 657 compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci"; 658 reg = <0x0 0x700b0600 0x0 0x200>; 659 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 660 clocks = <&tegra_car TEGRA210_CLK_SDMMC4>; 661 clock-names = "sdhci"; 662 resets = <&tegra_car 15>; 663 reset-names = "sdhci"; 664 status = "disabled"; 665 }; 666 667 mipi: mipi@0,700e3000 { 668 compatible = "nvidia,tegra210-mipi"; 669 reg = <0x0 0x700e3000 0x0 0x100>; 670 clocks = <&tegra_car TEGRA210_CLK_MIPI_CAL>; 671 clock-names = "mipi-cal"; 672 #nvidia,mipi-calibrate-cells = <1>; 673 }; 674 675 spi@0,70410000 { 676 compatible = "nvidia,tegra210-qspi"; 677 reg = <0x0 0x70410000 0x0 0x1000>; 678 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 679 #address-cells = <1>; 680 #size-cells = <0>; 681 clocks = <&tegra_car TEGRA210_CLK_QSPI>; 682 clock-names = "qspi"; 683 resets = <&tegra_car 211>; 684 reset-names = "qspi"; 685 dmas = <&apbdma 5>, <&apbdma 5>; 686 dma-names = "rx", "tx"; 687 status = "disabled"; 688 }; 689 690 usb@0,7d000000 { 691 compatible = "nvidia,tegra210-ehci", "nvidia,tegra30-ehci", "usb-ehci"; 692 reg = <0x0 0x7d000000 0x0 0x4000>; 693 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 694 phy_type = "utmi"; 695 clocks = <&tegra_car TEGRA210_CLK_USBD>; 696 clock-names = "usb"; 697 resets = <&tegra_car 22>; 698 reset-names = "usb"; 699 nvidia,phy = <&phy1>; 700 status = "disabled"; 701 }; 702 703 phy1: usb-phy@0,7d000000 { 704 compatible = "nvidia,tegra210-usb-phy", "nvidia,tegra30-usb-phy"; 705 reg = <0x0 0x7d000000 0x0 0x4000>, 706 <0x0 0x7d000000 0x0 0x4000>; 707 phy_type = "utmi"; 708 clocks = <&tegra_car TEGRA210_CLK_USBD>, 709 <&tegra_car TEGRA210_CLK_PLL_U>, 710 <&tegra_car TEGRA210_CLK_USBD>; 711 clock-names = "reg", "pll_u", "utmi-pads"; 712 resets = <&tegra_car 22>, <&tegra_car 22>; 713 reset-names = "usb", "utmi-pads"; 714 nvidia,hssync-start-delay = <0>; 715 nvidia,idle-wait-delay = <17>; 716 nvidia,elastic-limit = <16>; 717 nvidia,term-range-adj = <6>; 718 nvidia,xcvr-setup = <9>; 719 nvidia,xcvr-lsfslew = <0>; 720 nvidia,xcvr-lsrslew = <3>; 721 nvidia,hssquelch-level = <2>; 722 nvidia,hsdiscon-level = <5>; 723 nvidia,xcvr-hsslew = <12>; 724 nvidia,has-utmi-pad-registers; 725 status = "disabled"; 726 }; 727 728 usb@0,7d004000 { 729 compatible = "nvidia,tegra210-ehci", "nvidia,tegra30-ehci", "usb-ehci"; 730 reg = <0x0 0x7d004000 0x0 0x4000>; 731 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 732 phy_type = "utmi"; 733 clocks = <&tegra_car TEGRA210_CLK_USB2>; 734 clock-names = "usb"; 735 resets = <&tegra_car 58>; 736 reset-names = "usb"; 737 nvidia,phy = <&phy2>; 738 status = "disabled"; 739 }; 740 741 phy2: usb-phy@0,7d004000 { 742 compatible = "nvidia,tegra210-usb-phy", "nvidia,tegra30-usb-phy"; 743 reg = <0x0 0x7d004000 0x0 0x4000>, 744 <0x0 0x7d000000 0x0 0x4000>; 745 phy_type = "utmi"; 746 clocks = <&tegra_car TEGRA210_CLK_USB2>, 747 <&tegra_car TEGRA210_CLK_PLL_U>, 748 <&tegra_car TEGRA210_CLK_USBD>; 749 clock-names = "reg", "pll_u", "utmi-pads"; 750 resets = <&tegra_car 58>, <&tegra_car 22>; 751 reset-names = "usb", "utmi-pads"; 752 nvidia,hssync-start-delay = <0>; 753 nvidia,idle-wait-delay = <17>; 754 nvidia,elastic-limit = <16>; 755 nvidia,term-range-adj = <6>; 756 nvidia,xcvr-setup = <9>; 757 nvidia,xcvr-lsfslew = <0>; 758 nvidia,xcvr-lsrslew = <3>; 759 nvidia,hssquelch-level = <2>; 760 nvidia,hsdiscon-level = <5>; 761 nvidia,xcvr-hsslew = <12>; 762 status = "disabled"; 763 }; 764 765 cpus { 766 #address-cells = <1>; 767 #size-cells = <0>; 768 769 cpu@0 { 770 device_type = "cpu"; 771 compatible = "arm,cortex-a57"; 772 reg = <0>; 773 }; 774 775 cpu@1 { 776 device_type = "cpu"; 777 compatible = "arm,cortex-a57"; 778 reg = <1>; 779 }; 780 781 cpu@2 { 782 device_type = "cpu"; 783 compatible = "arm,cortex-a57"; 784 reg = <2>; 785 }; 786 787 cpu@3 { 788 device_type = "cpu"; 789 compatible = "arm,cortex-a57"; 790 reg = <3>; 791 }; 792 }; 793 794 timer { 795 compatible = "arm,armv8-timer"; 796 interrupts = <GIC_PPI 13 797 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 798 <GIC_PPI 14 799 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 800 <GIC_PPI 11 801 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 802 <GIC_PPI 10 803 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 804 interrupt-parent = <&gic>; 805 }; 806}; 807