arm64: tegra: Add reset-cells to memory controller

Tegra210 device tree is missing reset-cells property for the memory
controller node. This patch adds it.

Signed-off-by: Sowjan

arm64: tegra: Add reset-cells to memory controller

Tegra210 device tree is missing reset-cells property for the memory
controller node. This patch adds it.

Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Fix SOR powergate clocks and reset

Tegra210 device tree lists CSI clock and reset under SOR powergate
node.

But Tegra210 has CSICIL in SOR partition and CSI in VEN

arm64: tegra: Fix SOR powergate clocks and reset

Tegra210 device tree lists CSI clock and reset under SOR powergate
node.

But Tegra210 has CSICIL in SOR partition and CSI in VENC partition.

So, this patch includes fix for SOR powergate node.

Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Hook up EMC cooling device

The external memory controller can be used as a cooling device for the
LPDDR chips. Hook it up to the "mem" thermal zone of the SOCTHERM block

arm64: tegra: Hook up EMC cooling device

The external memory controller can be used as a cooling device for the
LPDDR chips. Hook it up to the "mem" thermal zone of the SOCTHERM block
so that temperature polling can be enabled on the EMC when a given
temperature is exceeded.

Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Add external memory controller node for Tegra210

Add external memory controller (EMC) node for Tegra210

Signed-off-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by

arm64: tegra: Add external memory controller node for Tegra210

Add external memory controller (EMC) node for Tegra210

Signed-off-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Add clock-cells property to Tegra PMC node

Tegra132 and Tegra210 PMC blocks have clk_out_1, clk_out_2, clk_out_3,
and a blink clock as a part of the PMC.

These clo

arm64: tegra: Add clock-cells property to Tegra PMC node

Tegra132 and Tegra210 PMC blocks have clk_out_1, clk_out_2, clk_out_3,
and a blink clock as a part of the PMC.

These clocks were erroneously provided by the clock and reset controller
and are now provided by the PMC instead because that's where the primary
controls are.

Clock IDs for these clocks are defined in the PMC dt-bindings.

This patch updates the device tree to include the PMC dt-bindings header
and adds the #clock-cells property with one clock specifier to the PMC
node.

Reviewed-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Add XUDC node for Tegra210

Tegra210 has one XUSB device mode controller, which can be operated in
HS and SS modes. Add DT entry for XUSB device mode controller.

Si

arm64: tegra: Add XUDC node for Tegra210

Tegra210 has one XUSB device mode controller, which can be operated in
HS and SS modes. Add DT entry for XUSB device mode controller.

Signed-off-by: Nagarjuna Kristam <nkristam@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Enable wake from deep sleep on RTC alarm

This patch updates device tree for RTC and PMC to allow system wake
from deep sleep on RTC alarm.

Signed-off-by: Sowjanya

arm64: tegra: Enable wake from deep sleep on RTC alarm

This patch updates device tree for RTC and PMC to allow system wake
from deep sleep on RTC alarm.

Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Add PMU on Tegra210

The NVIDIA Tegra210 contains an ARM PMU v3 that can be used to gather
statistics about the processors and their memory system. Add a device
tree nod

arm64: tegra: Add PMU on Tegra210

The NVIDIA Tegra210 contains an ARM PMU v3 that can be used to gather
statistics about the processors and their memory system. Add a device
tree node so that this functionality can be exposed.

Reported-by: William Cohen <giantklein@gmail.com>
Tested-by: William Cohen <giantklein@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Add blank lines for better readability

Separate the individual thermal zones by a blank line for improved
readability.

Signed-off-by: Thierry Reding <treding@nvidi

arm64: tegra: Add blank lines for better readability

Separate the individual thermal zones by a blank line for improved
readability.

Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Add SOR0_OUT clock on Tegra210

This clock was not previously used because it is a fixed clock. However,
adding it here allows operating systems to deal with SOR0 the same w

arm64: tegra: Add SOR0_OUT clock on Tegra210

This clock was not previously used because it is a fixed clock. However,
adding it here allows operating systems to deal with SOR0 the same way
as SOR1.

Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Hook up edp interrupt on Tegra210 SOCTHERM

For some reason this was never hooked up. Do it now so that over-current
interrupts can be logged.

Signed-off-by: Thierr

arm64: tegra: Hook up edp interrupt on Tegra210 SOCTHERM

For some reason this was never hooked up. Do it now so that over-current
interrupts can be logged.

Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Add PEX DPD states as pinctrl properties

Add PEX deep power down states as pinctrl properties to set in PCIe driver.
In Tegra210, BIAS pads are not in power down mode when

arm64: tegra: Add PEX DPD states as pinctrl properties

Add PEX deep power down states as pinctrl properties to set in PCIe driver.
In Tegra210, BIAS pads are not in power down mode when clamps are applied.
To set the pads in DPD, pass the PEX DPD states as pinctrl properties to
PCIe driver.

Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Fix AGIC register range

The Tegra AGIC interrupt controller is an ARM GIC400 interrupt
controller. Per the ARM GIC device-tree binding, the first address
region is for

arm64: tegra: Fix AGIC register range

The Tegra AGIC interrupt controller is an ARM GIC400 interrupt
controller. Per the ARM GIC device-tree binding, the first address
region is for the GIC distributor registers and the second address
region is for the GIC CPU interface registers. The address space for
the distributor registers is 4kB, but currently this is incorrectly
defined as 8kB for the Tegra AGIC and overlaps with the CPU interface
registers. Correct the address space for the distributor to be 4kB.

Cc: stable@vger.kernel.org
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Fixes: bcdbde433542 ("arm64: tegra: Add AGIC node for Tegra210")
Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Don't use architected timer for suspend on Tegra210

Due to an integration issue the architected timer on Tegra210 does not
remain on during system suspend (a.k.a. SC7). Mar

arm64: tegra: Don't use architected timer for suspend on Tegra210

Due to an integration issue the architected timer on Tegra210 does not
remain on during system suspend (a.k.a. SC7). Mark it accordingly so
that it isn't considered as a means to track suspend time.

Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Add L2 cache topology to Tegra210

Add L2 cache and make it the next level of cache for each of the CPUs.

Signed-off-by: Joseph Lo <josephl@nvidia.com>
Signed-off-b

arm64: tegra: Add L2 cache topology to Tegra210

Add L2 cache and make it the next level of cache for each of the CPUs.

Signed-off-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Add CPU idle states properties for Tegra210

Add idle states properties for generic ARM CPU idle driver. This
includes a cpu-sleep state which is the power down state of CPU

arm64: tegra: Add CPU idle states properties for Tegra210

Add idle states properties for generic ARM CPU idle driver. This
includes a cpu-sleep state which is the power down state of CPU cores.

Signed-off-by: Joseph Lo <josephl@nvidia.com>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Fix timer node for Tegra210

Fix timer node to make it work with Tegra210 timer driver.

Signed-off-by: Joseph Lo <josephl@nvidia.com>
Acked-by: Jon Hunter <jonathan

arm64: tegra: Fix timer node for Tegra210

Fix timer node to make it work with Tegra210 timer driver.

Signed-off-by: Joseph Lo <josephl@nvidia.com>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Update compatible for Tegra210 I2C

Update I2C device node compatible string to be appropriate.

Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
Signed-o

arm64: tegra: Update compatible for Tegra210 I2C

Update I2C device node compatible string to be appropriate.

Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Add SDMMC auto-calibration settings

Add SDMMC initial pad offsets used by auto calibration process.

Add SDMMC fixed drive strengths for Tegra210, Tegra186 and
Tegr

arm64: tegra: Add SDMMC auto-calibration settings

Add SDMMC initial pad offsets used by auto calibration process.

Add SDMMC fixed drive strengths for Tegra210, Tegra186 and
Tegra194 which are used when calibration timeouts.

Fixed drive strengths are based on Pre SI Analysis of the pads.

Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Add CPU clocks on Tegra210

Add CPU clocks for Tegra210.

Signed-off-by: Joseph Lo <josephl@nvidia.com>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by

arm64: tegra: Add CPU clocks on Tegra210

Add CPU clocks for Tegra210.

Signed-off-by: Joseph Lo <josephl@nvidia.com>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Add DFLL clock on Tegra210

Add essential DFLL clock properties for Tegra210.

Signed-off-by: Joseph Lo <josephl@nvidia.com>
Acked-by: Jon Hunter <jonathanh@nvidia.c

arm64: tegra: Add DFLL clock on Tegra210

Add essential DFLL clock properties for Tegra210.

Signed-off-by: Joseph Lo <josephl@nvidia.com>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Fix register range of apbmisc on Tegra210

Fix the register range of apbmisc, that originally inherited from
Tegra124.

Reported-by: Mark Zhang <markz@nvidia.com>

arm64: tegra: Fix register range of apbmisc on Tegra210

Fix the register range of apbmisc, that originally inherited from
Tegra124.

Reported-by: Mark Zhang <markz@nvidia.com>
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: dts: tegra210: Add power-domains for xHCI

Populate the power-domain properties for the xHCI device for Tegra210.

Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Acked-by

arm64: dts: tegra210: Add power-domains for xHCI

Populate the power-domain properties for the xHCI device for Tegra210.

Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: dts: tegra210: Enable HS400

Enable HS400 signaling on Tegra210 SDMMC4 controller.

Signed-off-by: Aapo Vienamo <avienamo@nvidia.com>
Signed-off-by: Thierry Reding <treding

arm64: dts: tegra210: Enable HS400

Enable HS400 signaling on Tegra210 SDMMC4 controller.

Signed-off-by: Aapo Vienamo <avienamo@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: dts: tegra210: Add SDMMC4 DQS trim value

Add the HS400 DQS trim value for Tegra210 SDMMC4.

Signed-off-by: Aapo Vienamo <avienamo@nvidia.com>
Signed-off-by: Thierry Reding

arm64: dts: tegra210: Add SDMMC4 DQS trim value

Add the HS400 DQS trim value for Tegra210 SDMMC4.

Signed-off-by: Aapo Vienamo <avienamo@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

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