1// SPDX-License-Identifier: GPL-2.0 2#include <dt-bindings/clock/tegra210-car.h> 3#include <dt-bindings/gpio/tegra-gpio.h> 4#include <dt-bindings/memory/tegra210-mc.h> 5#include <dt-bindings/pinctrl/pinctrl-tegra.h> 6#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 7#include <dt-bindings/reset/tegra210-car.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/thermal/tegra124-soctherm.h> 10 11/ { 12 compatible = "nvidia,tegra210"; 13 interrupt-parent = <&lic>; 14 #address-cells = <2>; 15 #size-cells = <2>; 16 17 pcie@1003000 { 18 compatible = "nvidia,tegra210-pcie"; 19 device_type = "pci"; 20 reg = <0x0 0x01003000 0x0 0x00000800 /* PADS registers */ 21 0x0 0x01003800 0x0 0x00000800 /* AFI registers */ 22 0x0 0x02000000 0x0 0x10000000>; /* configuration space */ 23 reg-names = "pads", "afi", "cs"; 24 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 25 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 26 interrupt-names = "intr", "msi"; 27 28 #interrupt-cells = <1>; 29 interrupt-map-mask = <0 0 0 0>; 30 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 31 32 bus-range = <0x00 0xff>; 33 #address-cells = <3>; 34 #size-cells = <2>; 35 36 ranges = <0x82000000 0 0x01000000 0x0 0x01000000 0 0x00001000 /* port 0 configuration space */ 37 0x82000000 0 0x01001000 0x0 0x01001000 0 0x00001000 /* port 1 configuration space */ 38 0x81000000 0 0x0 0x0 0x12000000 0 0x00010000 /* downstream I/O (64 KiB) */ 39 0x82000000 0 0x13000000 0x0 0x13000000 0 0x0d000000 /* non-prefetchable memory (208 MiB) */ 40 0xc2000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */ 41 42 clocks = <&tegra_car TEGRA210_CLK_PCIE>, 43 <&tegra_car TEGRA210_CLK_AFI>, 44 <&tegra_car TEGRA210_CLK_PLL_E>, 45 <&tegra_car TEGRA210_CLK_CML0>; 46 clock-names = "pex", "afi", "pll_e", "cml"; 47 resets = <&tegra_car 70>, 48 <&tegra_car 72>, 49 <&tegra_car 74>; 50 reset-names = "pex", "afi", "pcie_x"; 51 status = "disabled"; 52 53 pci@1,0 { 54 device_type = "pci"; 55 assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>; 56 reg = <0x000800 0 0 0 0>; 57 bus-range = <0x00 0xff>; 58 status = "disabled"; 59 60 #address-cells = <3>; 61 #size-cells = <2>; 62 ranges; 63 64 nvidia,num-lanes = <4>; 65 }; 66 67 pci@2,0 { 68 device_type = "pci"; 69 assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>; 70 reg = <0x001000 0 0 0 0>; 71 bus-range = <0x00 0xff>; 72 status = "disabled"; 73 74 #address-cells = <3>; 75 #size-cells = <2>; 76 ranges; 77 78 nvidia,num-lanes = <1>; 79 }; 80 }; 81 82 host1x@50000000 { 83 compatible = "nvidia,tegra210-host1x", "simple-bus"; 84 reg = <0x0 0x50000000 0x0 0x00034000>; 85 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */ 86 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */ 87 clocks = <&tegra_car TEGRA210_CLK_HOST1X>; 88 clock-names = "host1x"; 89 resets = <&tegra_car 28>; 90 reset-names = "host1x"; 91 92 #address-cells = <2>; 93 #size-cells = <2>; 94 95 ranges = <0x0 0x54000000 0x0 0x54000000 0x0 0x01000000>; 96 97 iommus = <&mc TEGRA_SWGROUP_HC>; 98 99 dpaux1: dpaux@54040000 { 100 compatible = "nvidia,tegra210-dpaux"; 101 reg = <0x0 0x54040000 0x0 0x00040000>; 102 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 103 clocks = <&tegra_car TEGRA210_CLK_DPAUX1>, 104 <&tegra_car TEGRA210_CLK_PLL_DP>; 105 clock-names = "dpaux", "parent"; 106 resets = <&tegra_car 207>; 107 reset-names = "dpaux"; 108 power-domains = <&pd_sor>; 109 status = "disabled"; 110 111 state_dpaux1_aux: pinmux-aux { 112 groups = "dpaux-io"; 113 function = "aux"; 114 }; 115 116 state_dpaux1_i2c: pinmux-i2c { 117 groups = "dpaux-io"; 118 function = "i2c"; 119 }; 120 121 state_dpaux1_off: pinmux-off { 122 groups = "dpaux-io"; 123 function = "off"; 124 }; 125 126 i2c-bus { 127 #address-cells = <1>; 128 #size-cells = <0>; 129 }; 130 }; 131 132 vi@54080000 { 133 compatible = "nvidia,tegra210-vi"; 134 reg = <0x0 0x54080000 0x0 0x00040000>; 135 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 136 status = "disabled"; 137 }; 138 139 tsec@54100000 { 140 compatible = "nvidia,tegra210-tsec"; 141 reg = <0x0 0x54100000 0x0 0x00040000>; 142 }; 143 144 dc@54200000 { 145 compatible = "nvidia,tegra210-dc"; 146 reg = <0x0 0x54200000 0x0 0x00040000>; 147 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 148 clocks = <&tegra_car TEGRA210_CLK_DISP1>, 149 <&tegra_car TEGRA210_CLK_PLL_P>; 150 clock-names = "dc", "parent"; 151 resets = <&tegra_car 27>; 152 reset-names = "dc"; 153 154 iommus = <&mc TEGRA_SWGROUP_DC>; 155 156 nvidia,head = <0>; 157 }; 158 159 dc@54240000 { 160 compatible = "nvidia,tegra210-dc"; 161 reg = <0x0 0x54240000 0x0 0x00040000>; 162 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 163 clocks = <&tegra_car TEGRA210_CLK_DISP2>, 164 <&tegra_car TEGRA210_CLK_PLL_P>; 165 clock-names = "dc", "parent"; 166 resets = <&tegra_car 26>; 167 reset-names = "dc"; 168 169 iommus = <&mc TEGRA_SWGROUP_DCB>; 170 171 nvidia,head = <1>; 172 }; 173 174 dsi@54300000 { 175 compatible = "nvidia,tegra210-dsi"; 176 reg = <0x0 0x54300000 0x0 0x00040000>; 177 clocks = <&tegra_car TEGRA210_CLK_DSIA>, 178 <&tegra_car TEGRA210_CLK_DSIALP>, 179 <&tegra_car TEGRA210_CLK_PLL_D_OUT0>; 180 clock-names = "dsi", "lp", "parent"; 181 resets = <&tegra_car 48>; 182 reset-names = "dsi"; 183 power-domains = <&pd_sor>; 184 nvidia,mipi-calibrate = <&mipi 0x0c0>; /* DSIA & DSIB pads */ 185 186 status = "disabled"; 187 188 #address-cells = <1>; 189 #size-cells = <0>; 190 }; 191 192 vic@54340000 { 193 compatible = "nvidia,tegra210-vic"; 194 reg = <0x0 0x54340000 0x0 0x00040000>; 195 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 196 clocks = <&tegra_car TEGRA210_CLK_VIC03>; 197 clock-names = "vic"; 198 resets = <&tegra_car 178>; 199 reset-names = "vic"; 200 201 iommus = <&mc TEGRA_SWGROUP_VIC>; 202 power-domains = <&pd_vic>; 203 }; 204 205 nvjpg@54380000 { 206 compatible = "nvidia,tegra210-nvjpg"; 207 reg = <0x0 0x54380000 0x0 0x00040000>; 208 status = "disabled"; 209 }; 210 211 dsi@54400000 { 212 compatible = "nvidia,tegra210-dsi"; 213 reg = <0x0 0x54400000 0x0 0x00040000>; 214 clocks = <&tegra_car TEGRA210_CLK_DSIB>, 215 <&tegra_car TEGRA210_CLK_DSIBLP>, 216 <&tegra_car TEGRA210_CLK_PLL_D_OUT0>; 217 clock-names = "dsi", "lp", "parent"; 218 resets = <&tegra_car 82>; 219 reset-names = "dsi"; 220 power-domains = <&pd_sor>; 221 nvidia,mipi-calibrate = <&mipi 0x300>; /* DSIC & DSID pads */ 222 223 status = "disabled"; 224 225 #address-cells = <1>; 226 #size-cells = <0>; 227 }; 228 229 nvdec@54480000 { 230 compatible = "nvidia,tegra210-nvdec"; 231 reg = <0x0 0x54480000 0x0 0x00040000>; 232 status = "disabled"; 233 }; 234 235 nvenc@544c0000 { 236 compatible = "nvidia,tegra210-nvenc"; 237 reg = <0x0 0x544c0000 0x0 0x00040000>; 238 status = "disabled"; 239 }; 240 241 tsec@54500000 { 242 compatible = "nvidia,tegra210-tsec"; 243 reg = <0x0 0x54500000 0x0 0x00040000>; 244 status = "disabled"; 245 }; 246 247 sor@54540000 { 248 compatible = "nvidia,tegra210-sor"; 249 reg = <0x0 0x54540000 0x0 0x00040000>; 250 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 251 clocks = <&tegra_car TEGRA210_CLK_SOR0>, 252 <&tegra_car TEGRA210_CLK_PLL_D_OUT0>, 253 <&tegra_car TEGRA210_CLK_PLL_DP>, 254 <&tegra_car TEGRA210_CLK_SOR_SAFE>; 255 clock-names = "sor", "parent", "dp", "safe"; 256 resets = <&tegra_car 182>; 257 reset-names = "sor"; 258 pinctrl-0 = <&state_dpaux_aux>; 259 pinctrl-1 = <&state_dpaux_i2c>; 260 pinctrl-2 = <&state_dpaux_off>; 261 pinctrl-names = "aux", "i2c", "off"; 262 power-domains = <&pd_sor>; 263 status = "disabled"; 264 }; 265 266 sor@54580000 { 267 compatible = "nvidia,tegra210-sor1"; 268 reg = <0x0 0x54580000 0x0 0x00040000>; 269 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 270 clocks = <&tegra_car TEGRA210_CLK_SOR1>, 271 <&tegra_car TEGRA210_CLK_SOR1_OUT>, 272 <&tegra_car TEGRA210_CLK_PLL_D2_OUT0>, 273 <&tegra_car TEGRA210_CLK_PLL_DP>, 274 <&tegra_car TEGRA210_CLK_SOR_SAFE>; 275 clock-names = "sor", "out", "parent", "dp", "safe"; 276 resets = <&tegra_car 183>; 277 reset-names = "sor"; 278 pinctrl-0 = <&state_dpaux1_aux>; 279 pinctrl-1 = <&state_dpaux1_i2c>; 280 pinctrl-2 = <&state_dpaux1_off>; 281 pinctrl-names = "aux", "i2c", "off"; 282 power-domains = <&pd_sor>; 283 status = "disabled"; 284 }; 285 286 dpaux: dpaux@545c0000 { 287 compatible = "nvidia,tegra124-dpaux"; 288 reg = <0x0 0x545c0000 0x0 0x00040000>; 289 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 290 clocks = <&tegra_car TEGRA210_CLK_DPAUX>, 291 <&tegra_car TEGRA210_CLK_PLL_DP>; 292 clock-names = "dpaux", "parent"; 293 resets = <&tegra_car 181>; 294 reset-names = "dpaux"; 295 power-domains = <&pd_sor>; 296 status = "disabled"; 297 298 state_dpaux_aux: pinmux-aux { 299 groups = "dpaux-io"; 300 function = "aux"; 301 }; 302 303 state_dpaux_i2c: pinmux-i2c { 304 groups = "dpaux-io"; 305 function = "i2c"; 306 }; 307 308 state_dpaux_off: pinmux-off { 309 groups = "dpaux-io"; 310 function = "off"; 311 }; 312 313 i2c-bus { 314 #address-cells = <1>; 315 #size-cells = <0>; 316 }; 317 }; 318 319 isp@54600000 { 320 compatible = "nvidia,tegra210-isp"; 321 reg = <0x0 0x54600000 0x0 0x00040000>; 322 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 323 status = "disabled"; 324 }; 325 326 isp@54680000 { 327 compatible = "nvidia,tegra210-isp"; 328 reg = <0x0 0x54680000 0x0 0x00040000>; 329 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 330 status = "disabled"; 331 }; 332 333 i2c@546c0000 { 334 compatible = "nvidia,tegra210-i2c-vi"; 335 reg = <0x0 0x546c0000 0x0 0x00040000>; 336 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 337 status = "disabled"; 338 }; 339 }; 340 341 gic: interrupt-controller@50041000 { 342 compatible = "arm,gic-400"; 343 #interrupt-cells = <3>; 344 interrupt-controller; 345 reg = <0x0 0x50041000 0x0 0x1000>, 346 <0x0 0x50042000 0x0 0x2000>, 347 <0x0 0x50044000 0x0 0x2000>, 348 <0x0 0x50046000 0x0 0x2000>; 349 interrupts = <GIC_PPI 9 350 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 351 interrupt-parent = <&gic>; 352 }; 353 354 gpu@57000000 { 355 compatible = "nvidia,gm20b"; 356 reg = <0x0 0x57000000 0x0 0x01000000>, 357 <0x0 0x58000000 0x0 0x01000000>; 358 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 359 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 360 interrupt-names = "stall", "nonstall"; 361 clocks = <&tegra_car TEGRA210_CLK_GPU>, 362 <&tegra_car TEGRA210_CLK_PLL_P_OUT5>, 363 <&tegra_car TEGRA210_CLK_PLL_G_REF>; 364 clock-names = "gpu", "pwr", "ref"; 365 resets = <&tegra_car 184>; 366 reset-names = "gpu"; 367 368 iommus = <&mc TEGRA_SWGROUP_GPU>; 369 370 status = "disabled"; 371 }; 372 373 lic: interrupt-controller@60004000 { 374 compatible = "nvidia,tegra210-ictlr"; 375 reg = <0x0 0x60004000 0x0 0x40>, /* primary controller */ 376 <0x0 0x60004100 0x0 0x40>, /* secondary controller */ 377 <0x0 0x60004200 0x0 0x40>, /* tertiary controller */ 378 <0x0 0x60004300 0x0 0x40>, /* quaternary controller */ 379 <0x0 0x60004400 0x0 0x40>, /* quinary controller */ 380 <0x0 0x60004500 0x0 0x40>; /* senary controller */ 381 interrupt-controller; 382 #interrupt-cells = <3>; 383 interrupt-parent = <&gic>; 384 }; 385 386 timer@60005000 { 387 compatible = "nvidia,tegra210-timer", "nvidia,tegra20-timer"; 388 reg = <0x0 0x60005000 0x0 0x400>; 389 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 390 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 391 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 392 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 393 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 394 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 395 clocks = <&tegra_car TEGRA210_CLK_TIMER>; 396 clock-names = "timer"; 397 }; 398 399 tegra_car: clock@60006000 { 400 compatible = "nvidia,tegra210-car"; 401 reg = <0x0 0x60006000 0x0 0x1000>; 402 #clock-cells = <1>; 403 #reset-cells = <1>; 404 }; 405 406 flow-controller@60007000 { 407 compatible = "nvidia,tegra210-flowctrl"; 408 reg = <0x0 0x60007000 0x0 0x1000>; 409 }; 410 411 gpio: gpio@6000d000 { 412 compatible = "nvidia,tegra210-gpio", "nvidia,tegra30-gpio"; 413 reg = <0x0 0x6000d000 0x0 0x1000>; 414 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 415 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 416 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 417 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 418 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 419 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 420 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 421 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 422 #gpio-cells = <2>; 423 gpio-controller; 424 #interrupt-cells = <2>; 425 interrupt-controller; 426 }; 427 428 apbdma: dma@60020000 { 429 compatible = "nvidia,tegra210-apbdma", "nvidia,tegra148-apbdma"; 430 reg = <0x0 0x60020000 0x0 0x1400>; 431 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 432 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 433 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 434 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 435 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 436 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 437 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 438 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 439 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 440 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 441 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 442 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 443 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 444 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 445 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 446 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 447 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 448 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 449 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 450 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 451 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 452 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 453 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 454 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 455 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 456 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 457 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 458 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 459 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 460 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 461 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 462 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 463 clocks = <&tegra_car TEGRA210_CLK_APBDMA>; 464 clock-names = "dma"; 465 resets = <&tegra_car 34>; 466 reset-names = "dma"; 467 #dma-cells = <1>; 468 }; 469 470 apbmisc@70000800 { 471 compatible = "nvidia,tegra210-apbmisc", "nvidia,tegra20-apbmisc"; 472 reg = <0x0 0x70000800 0x0 0x64>, /* Chip revision */ 473 <0x0 0x70000008 0x0 0x04>; /* Strapping options */ 474 }; 475 476 pinmux: pinmux@700008d4 { 477 compatible = "nvidia,tegra210-pinmux"; 478 reg = <0x0 0x700008d4 0x0 0x29c>, /* Pad control registers */ 479 <0x0 0x70003000 0x0 0x294>; /* Mux registers */ 480 }; 481 482 /* 483 * There are two serial driver i.e. 8250 based simple serial 484 * driver and APB DMA based serial driver for higher baudrate 485 * and performance. To enable the 8250 based driver, the compatible 486 * is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable 487 * the APB DMA based serial driver, the compatible is 488 * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart". 489 */ 490 uarta: serial@70006000 { 491 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; 492 reg = <0x0 0x70006000 0x0 0x40>; 493 reg-shift = <2>; 494 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 495 clocks = <&tegra_car TEGRA210_CLK_UARTA>; 496 clock-names = "serial"; 497 resets = <&tegra_car 6>; 498 reset-names = "serial"; 499 dmas = <&apbdma 8>, <&apbdma 8>; 500 dma-names = "rx", "tx"; 501 status = "disabled"; 502 }; 503 504 uartb: serial@70006040 { 505 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; 506 reg = <0x0 0x70006040 0x0 0x40>; 507 reg-shift = <2>; 508 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 509 clocks = <&tegra_car TEGRA210_CLK_UARTB>; 510 clock-names = "serial"; 511 resets = <&tegra_car 7>; 512 reset-names = "serial"; 513 dmas = <&apbdma 9>, <&apbdma 9>; 514 dma-names = "rx", "tx"; 515 status = "disabled"; 516 }; 517 518 uartc: serial@70006200 { 519 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; 520 reg = <0x0 0x70006200 0x0 0x40>; 521 reg-shift = <2>; 522 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 523 clocks = <&tegra_car TEGRA210_CLK_UARTC>; 524 clock-names = "serial"; 525 resets = <&tegra_car 55>; 526 reset-names = "serial"; 527 dmas = <&apbdma 10>, <&apbdma 10>; 528 dma-names = "rx", "tx"; 529 status = "disabled"; 530 }; 531 532 uartd: serial@70006300 { 533 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; 534 reg = <0x0 0x70006300 0x0 0x40>; 535 reg-shift = <2>; 536 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 537 clocks = <&tegra_car TEGRA210_CLK_UARTD>; 538 clock-names = "serial"; 539 resets = <&tegra_car 65>; 540 reset-names = "serial"; 541 dmas = <&apbdma 19>, <&apbdma 19>; 542 dma-names = "rx", "tx"; 543 status = "disabled"; 544 }; 545 546 pwm: pwm@7000a000 { 547 compatible = "nvidia,tegra210-pwm", "nvidia,tegra20-pwm"; 548 reg = <0x0 0x7000a000 0x0 0x100>; 549 #pwm-cells = <2>; 550 clocks = <&tegra_car TEGRA210_CLK_PWM>; 551 clock-names = "pwm"; 552 resets = <&tegra_car 17>; 553 reset-names = "pwm"; 554 status = "disabled"; 555 }; 556 557 i2c@7000c000 { 558 compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c"; 559 reg = <0x0 0x7000c000 0x0 0x100>; 560 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 561 #address-cells = <1>; 562 #size-cells = <0>; 563 clocks = <&tegra_car TEGRA210_CLK_I2C1>; 564 clock-names = "div-clk"; 565 resets = <&tegra_car 12>; 566 reset-names = "i2c"; 567 dmas = <&apbdma 21>, <&apbdma 21>; 568 dma-names = "rx", "tx"; 569 status = "disabled"; 570 }; 571 572 i2c@7000c400 { 573 compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c"; 574 reg = <0x0 0x7000c400 0x0 0x100>; 575 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 576 #address-cells = <1>; 577 #size-cells = <0>; 578 clocks = <&tegra_car TEGRA210_CLK_I2C2>; 579 clock-names = "div-clk"; 580 resets = <&tegra_car 54>; 581 reset-names = "i2c"; 582 dmas = <&apbdma 22>, <&apbdma 22>; 583 dma-names = "rx", "tx"; 584 status = "disabled"; 585 }; 586 587 i2c@7000c500 { 588 compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c"; 589 reg = <0x0 0x7000c500 0x0 0x100>; 590 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 591 #address-cells = <1>; 592 #size-cells = <0>; 593 clocks = <&tegra_car TEGRA210_CLK_I2C3>; 594 clock-names = "div-clk"; 595 resets = <&tegra_car 67>; 596 reset-names = "i2c"; 597 dmas = <&apbdma 23>, <&apbdma 23>; 598 dma-names = "rx", "tx"; 599 status = "disabled"; 600 }; 601 602 i2c@7000c700 { 603 compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c"; 604 reg = <0x0 0x7000c700 0x0 0x100>; 605 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 606 #address-cells = <1>; 607 #size-cells = <0>; 608 clocks = <&tegra_car TEGRA210_CLK_I2C4>; 609 clock-names = "div-clk"; 610 resets = <&tegra_car 103>; 611 reset-names = "i2c"; 612 dmas = <&apbdma 26>, <&apbdma 26>; 613 dma-names = "rx", "tx"; 614 pinctrl-0 = <&state_dpaux1_i2c>; 615 pinctrl-1 = <&state_dpaux1_off>; 616 pinctrl-names = "default", "idle"; 617 status = "disabled"; 618 }; 619 620 i2c@7000d000 { 621 compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c"; 622 reg = <0x0 0x7000d000 0x0 0x100>; 623 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 624 #address-cells = <1>; 625 #size-cells = <0>; 626 clocks = <&tegra_car TEGRA210_CLK_I2C5>; 627 clock-names = "div-clk"; 628 resets = <&tegra_car 47>; 629 reset-names = "i2c"; 630 dmas = <&apbdma 24>, <&apbdma 24>; 631 dma-names = "rx", "tx"; 632 status = "disabled"; 633 }; 634 635 i2c@7000d100 { 636 compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c"; 637 reg = <0x0 0x7000d100 0x0 0x100>; 638 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 639 #address-cells = <1>; 640 #size-cells = <0>; 641 clocks = <&tegra_car TEGRA210_CLK_I2C6>; 642 clock-names = "div-clk"; 643 resets = <&tegra_car 166>; 644 reset-names = "i2c"; 645 dmas = <&apbdma 30>, <&apbdma 30>; 646 dma-names = "rx", "tx"; 647 pinctrl-0 = <&state_dpaux_i2c>; 648 pinctrl-1 = <&state_dpaux_off>; 649 pinctrl-names = "default", "idle"; 650 status = "disabled"; 651 }; 652 653 spi@7000d400 { 654 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 655 reg = <0x0 0x7000d400 0x0 0x200>; 656 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 657 #address-cells = <1>; 658 #size-cells = <0>; 659 clocks = <&tegra_car TEGRA210_CLK_SBC1>; 660 clock-names = "spi"; 661 resets = <&tegra_car 41>; 662 reset-names = "spi"; 663 dmas = <&apbdma 15>, <&apbdma 15>; 664 dma-names = "rx", "tx"; 665 status = "disabled"; 666 }; 667 668 spi@7000d600 { 669 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 670 reg = <0x0 0x7000d600 0x0 0x200>; 671 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 672 #address-cells = <1>; 673 #size-cells = <0>; 674 clocks = <&tegra_car TEGRA210_CLK_SBC2>; 675 clock-names = "spi"; 676 resets = <&tegra_car 44>; 677 reset-names = "spi"; 678 dmas = <&apbdma 16>, <&apbdma 16>; 679 dma-names = "rx", "tx"; 680 status = "disabled"; 681 }; 682 683 spi@7000d800 { 684 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 685 reg = <0x0 0x7000d800 0x0 0x200>; 686 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 687 #address-cells = <1>; 688 #size-cells = <0>; 689 clocks = <&tegra_car TEGRA210_CLK_SBC3>; 690 clock-names = "spi"; 691 resets = <&tegra_car 46>; 692 reset-names = "spi"; 693 dmas = <&apbdma 17>, <&apbdma 17>; 694 dma-names = "rx", "tx"; 695 status = "disabled"; 696 }; 697 698 spi@7000da00 { 699 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 700 reg = <0x0 0x7000da00 0x0 0x200>; 701 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 702 #address-cells = <1>; 703 #size-cells = <0>; 704 clocks = <&tegra_car TEGRA210_CLK_SBC4>; 705 clock-names = "spi"; 706 resets = <&tegra_car 68>; 707 reset-names = "spi"; 708 dmas = <&apbdma 18>, <&apbdma 18>; 709 dma-names = "rx", "tx"; 710 status = "disabled"; 711 }; 712 713 rtc@7000e000 { 714 compatible = "nvidia,tegra210-rtc", "nvidia,tegra20-rtc"; 715 reg = <0x0 0x7000e000 0x0 0x100>; 716 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 717 clocks = <&tegra_car TEGRA210_CLK_RTC>; 718 clock-names = "rtc"; 719 }; 720 721 pmc: pmc@7000e400 { 722 compatible = "nvidia,tegra210-pmc"; 723 reg = <0x0 0x7000e400 0x0 0x400>; 724 clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>; 725 clock-names = "pclk", "clk32k_in"; 726 727 powergates { 728 pd_audio: aud { 729 clocks = <&tegra_car TEGRA210_CLK_APE>, 730 <&tegra_car TEGRA210_CLK_APB2APE>; 731 resets = <&tegra_car 198>; 732 #power-domain-cells = <0>; 733 }; 734 735 pd_sor: sor { 736 clocks = <&tegra_car TEGRA210_CLK_SOR0>, 737 <&tegra_car TEGRA210_CLK_SOR1>, 738 <&tegra_car TEGRA210_CLK_CSI>, 739 <&tegra_car TEGRA210_CLK_DSIA>, 740 <&tegra_car TEGRA210_CLK_DSIB>, 741 <&tegra_car TEGRA210_CLK_DPAUX>, 742 <&tegra_car TEGRA210_CLK_DPAUX1>, 743 <&tegra_car TEGRA210_CLK_MIPI_CAL>; 744 resets = <&tegra_car TEGRA210_CLK_SOR0>, 745 <&tegra_car TEGRA210_CLK_SOR1>, 746 <&tegra_car TEGRA210_CLK_CSI>, 747 <&tegra_car TEGRA210_CLK_DSIA>, 748 <&tegra_car TEGRA210_CLK_DSIB>, 749 <&tegra_car TEGRA210_CLK_DPAUX>, 750 <&tegra_car TEGRA210_CLK_DPAUX1>, 751 <&tegra_car TEGRA210_CLK_MIPI_CAL>; 752 #power-domain-cells = <0>; 753 }; 754 755 pd_xusbss: xusba { 756 clocks = <&tegra_car TEGRA210_CLK_XUSB_SS>; 757 resets = <&tegra_car TEGRA210_CLK_XUSB_SS>; 758 #power-domain-cells = <0>; 759 }; 760 761 pd_xusbdev: xusbb { 762 clocks = <&tegra_car TEGRA210_CLK_XUSB_DEV>; 763 resets = <&tegra_car 95>; 764 #power-domain-cells = <0>; 765 }; 766 767 pd_xusbhost: xusbc { 768 clocks = <&tegra_car TEGRA210_CLK_XUSB_HOST>; 769 resets = <&tegra_car TEGRA210_CLK_XUSB_HOST>; 770 #power-domain-cells = <0>; 771 }; 772 773 pd_vic: vic { 774 clocks = <&tegra_car TEGRA210_CLK_VIC03>; 775 clock-names = "vic"; 776 resets = <&tegra_car 178>; 777 reset-names = "vic"; 778 #power-domain-cells = <0>; 779 }; 780 }; 781 782 sdmmc1_3v3: sdmmc1-3v3 { 783 pins = "sdmmc1"; 784 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 785 }; 786 787 sdmmc1_1v8: sdmmc1-1v8 { 788 pins = "sdmmc1"; 789 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 790 }; 791 792 sdmmc3_3v3: sdmmc3-3v3 { 793 pins = "sdmmc3"; 794 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 795 }; 796 797 sdmmc3_1v8: sdmmc3-1v8 { 798 pins = "sdmmc3"; 799 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 800 }; 801 }; 802 803 fuse@7000f800 { 804 compatible = "nvidia,tegra210-efuse"; 805 reg = <0x0 0x7000f800 0x0 0x400>; 806 clocks = <&tegra_car TEGRA210_CLK_FUSE>; 807 clock-names = "fuse"; 808 resets = <&tegra_car 39>; 809 reset-names = "fuse"; 810 }; 811 812 mc: memory-controller@70019000 { 813 compatible = "nvidia,tegra210-mc"; 814 reg = <0x0 0x70019000 0x0 0x1000>; 815 clocks = <&tegra_car TEGRA210_CLK_MC>; 816 clock-names = "mc"; 817 818 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 819 820 #iommu-cells = <1>; 821 }; 822 823 sata@70020000 { 824 compatible = "nvidia,tegra210-ahci"; 825 reg = <0x0 0x70027000 0x0 0x2000>, /* AHCI */ 826 <0x0 0x70020000 0x0 0x7000>, /* SATA */ 827 <0x0 0x70001100 0x0 0x1000>; /* SATA AUX */ 828 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 829 clocks = <&tegra_car TEGRA210_CLK_SATA>, 830 <&tegra_car TEGRA210_CLK_SATA_OOB>; 831 clock-names = "sata", "sata-oob"; 832 resets = <&tegra_car 124>, 833 <&tegra_car 123>, 834 <&tegra_car 129>; 835 reset-names = "sata", "sata-oob", "sata-cold"; 836 status = "disabled"; 837 }; 838 839 hda@70030000 { 840 compatible = "nvidia,tegra210-hda", "nvidia,tegra30-hda"; 841 reg = <0x0 0x70030000 0x0 0x10000>; 842 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 843 clocks = <&tegra_car TEGRA210_CLK_HDA>, 844 <&tegra_car TEGRA210_CLK_HDA2HDMI>, 845 <&tegra_car TEGRA210_CLK_HDA2CODEC_2X>; 846 clock-names = "hda", "hda2hdmi", "hda2codec_2x"; 847 resets = <&tegra_car 125>, /* hda */ 848 <&tegra_car 128>, /* hda2hdmi */ 849 <&tegra_car 111>; /* hda2codec_2x */ 850 reset-names = "hda", "hda2hdmi", "hda2codec_2x"; 851 status = "disabled"; 852 }; 853 854 usb@70090000 { 855 compatible = "nvidia,tegra210-xusb"; 856 reg = <0x0 0x70090000 0x0 0x8000>, 857 <0x0 0x70098000 0x0 0x1000>, 858 <0x0 0x70099000 0x0 0x1000>; 859 reg-names = "hcd", "fpci", "ipfs"; 860 861 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 862 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 863 864 clocks = <&tegra_car TEGRA210_CLK_XUSB_HOST>, 865 <&tegra_car TEGRA210_CLK_XUSB_HOST_SRC>, 866 <&tegra_car TEGRA210_CLK_XUSB_FALCON_SRC>, 867 <&tegra_car TEGRA210_CLK_XUSB_SS>, 868 <&tegra_car TEGRA210_CLK_XUSB_SS_DIV2>, 869 <&tegra_car TEGRA210_CLK_XUSB_SS_SRC>, 870 <&tegra_car TEGRA210_CLK_XUSB_HS_SRC>, 871 <&tegra_car TEGRA210_CLK_XUSB_FS_SRC>, 872 <&tegra_car TEGRA210_CLK_PLL_U_480M>, 873 <&tegra_car TEGRA210_CLK_CLK_M>, 874 <&tegra_car TEGRA210_CLK_PLL_E>; 875 clock-names = "xusb_host", "xusb_host_src", 876 "xusb_falcon_src", "xusb_ss", 877 "xusb_ss_div2", "xusb_ss_src", 878 "xusb_hs_src", "xusb_fs_src", 879 "pll_u_480m", "clk_m", "pll_e"; 880 resets = <&tegra_car 89>, <&tegra_car 156>, 881 <&tegra_car 143>; 882 reset-names = "xusb_host", "xusb_ss", "xusb_src"; 883 power-domains = <&pd_xusbhost>, <&pd_xusbss>; 884 power-domain-names = "xusb_host", "xusb_ss"; 885 886 nvidia,xusb-padctl = <&padctl>; 887 888 status = "disabled"; 889 }; 890 891 padctl: padctl@7009f000 { 892 compatible = "nvidia,tegra210-xusb-padctl"; 893 reg = <0x0 0x7009f000 0x0 0x1000>; 894 resets = <&tegra_car 142>; 895 reset-names = "padctl"; 896 897 status = "disabled"; 898 899 pads { 900 usb2 { 901 clocks = <&tegra_car TEGRA210_CLK_USB2_TRK>; 902 clock-names = "trk"; 903 status = "disabled"; 904 905 lanes { 906 usb2-0 { 907 status = "disabled"; 908 #phy-cells = <0>; 909 }; 910 911 usb2-1 { 912 status = "disabled"; 913 #phy-cells = <0>; 914 }; 915 916 usb2-2 { 917 status = "disabled"; 918 #phy-cells = <0>; 919 }; 920 921 usb2-3 { 922 status = "disabled"; 923 #phy-cells = <0>; 924 }; 925 }; 926 }; 927 928 hsic { 929 clocks = <&tegra_car TEGRA210_CLK_HSIC_TRK>; 930 clock-names = "trk"; 931 status = "disabled"; 932 933 lanes { 934 hsic-0 { 935 status = "disabled"; 936 #phy-cells = <0>; 937 }; 938 939 hsic-1 { 940 status = "disabled"; 941 #phy-cells = <0>; 942 }; 943 }; 944 }; 945 946 pcie { 947 clocks = <&tegra_car TEGRA210_CLK_PLL_E>; 948 clock-names = "pll"; 949 resets = <&tegra_car 205>; 950 reset-names = "phy"; 951 status = "disabled"; 952 953 lanes { 954 pcie-0 { 955 status = "disabled"; 956 #phy-cells = <0>; 957 }; 958 959 pcie-1 { 960 status = "disabled"; 961 #phy-cells = <0>; 962 }; 963 964 pcie-2 { 965 status = "disabled"; 966 #phy-cells = <0>; 967 }; 968 969 pcie-3 { 970 status = "disabled"; 971 #phy-cells = <0>; 972 }; 973 974 pcie-4 { 975 status = "disabled"; 976 #phy-cells = <0>; 977 }; 978 979 pcie-5 { 980 status = "disabled"; 981 #phy-cells = <0>; 982 }; 983 984 pcie-6 { 985 status = "disabled"; 986 #phy-cells = <0>; 987 }; 988 }; 989 }; 990 991 sata { 992 clocks = <&tegra_car TEGRA210_CLK_PLL_E>; 993 clock-names = "pll"; 994 resets = <&tegra_car 204>; 995 reset-names = "phy"; 996 status = "disabled"; 997 998 lanes { 999 sata-0 { 1000 status = "disabled"; 1001 #phy-cells = <0>; 1002 }; 1003 }; 1004 }; 1005 }; 1006 1007 ports { 1008 usb2-0 { 1009 status = "disabled"; 1010 }; 1011 1012 usb2-1 { 1013 status = "disabled"; 1014 }; 1015 1016 usb2-2 { 1017 status = "disabled"; 1018 }; 1019 1020 usb2-3 { 1021 status = "disabled"; 1022 }; 1023 1024 hsic-0 { 1025 status = "disabled"; 1026 }; 1027 1028 usb3-0 { 1029 status = "disabled"; 1030 }; 1031 1032 usb3-1 { 1033 status = "disabled"; 1034 }; 1035 1036 usb3-2 { 1037 status = "disabled"; 1038 }; 1039 1040 usb3-3 { 1041 status = "disabled"; 1042 }; 1043 }; 1044 }; 1045 1046 sdhci@700b0000 { 1047 compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci"; 1048 reg = <0x0 0x700b0000 0x0 0x200>; 1049 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1050 clocks = <&tegra_car TEGRA210_CLK_SDMMC1>; 1051 clock-names = "sdhci"; 1052 resets = <&tegra_car 14>; 1053 reset-names = "sdhci"; 1054 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 1055 pinctrl-0 = <&sdmmc1_3v3>; 1056 pinctrl-1 = <&sdmmc1_1v8>; 1057 nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>; 1058 nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>; 1059 nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>; 1060 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7b>; 1061 nvidia,default-tap = <0x2>; 1062 nvidia,default-trim = <0x4>; 1063 assigned-clocks = <&tegra_car TEGRA210_CLK_SDMMC4>, 1064 <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>, 1065 <&tegra_car TEGRA210_CLK_PLL_C4>; 1066 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; 1067 assigned-clock-rates = <200000000>, <1000000000>, <1000000000>; 1068 status = "disabled"; 1069 }; 1070 1071 sdhci@700b0200 { 1072 compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci"; 1073 reg = <0x0 0x700b0200 0x0 0x200>; 1074 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 1075 clocks = <&tegra_car TEGRA210_CLK_SDMMC2>; 1076 clock-names = "sdhci"; 1077 resets = <&tegra_car 9>; 1078 reset-names = "sdhci"; 1079 nvidia,pad-autocal-pull-up-offset-1v8 = <0x05>; 1080 nvidia,pad-autocal-pull-down-offset-1v8 = <0x05>; 1081 nvidia,default-tap = <0x8>; 1082 nvidia,default-trim = <0x0>; 1083 status = "disabled"; 1084 }; 1085 1086 sdhci@700b0400 { 1087 compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci"; 1088 reg = <0x0 0x700b0400 0x0 0x200>; 1089 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 1090 clocks = <&tegra_car TEGRA210_CLK_SDMMC3>; 1091 clock-names = "sdhci"; 1092 resets = <&tegra_car 69>; 1093 reset-names = "sdhci"; 1094 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 1095 pinctrl-0 = <&sdmmc3_3v3>; 1096 pinctrl-1 = <&sdmmc3_1v8>; 1097 nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>; 1098 nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>; 1099 nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>; 1100 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7b>; 1101 nvidia,default-tap = <0x3>; 1102 nvidia,default-trim = <0x3>; 1103 status = "disabled"; 1104 }; 1105 1106 sdhci@700b0600 { 1107 compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci"; 1108 reg = <0x0 0x700b0600 0x0 0x200>; 1109 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 1110 clocks = <&tegra_car TEGRA210_CLK_SDMMC4>; 1111 clock-names = "sdhci"; 1112 resets = <&tegra_car 15>; 1113 reset-names = "sdhci"; 1114 nvidia,pad-autocal-pull-up-offset-1v8 = <0x05>; 1115 nvidia,pad-autocal-pull-down-offset-1v8 = <0x05>; 1116 nvidia,default-tap = <0x8>; 1117 nvidia,default-trim = <0x0>; 1118 assigned-clocks = <&tegra_car TEGRA210_CLK_SDMMC4>, 1119 <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; 1120 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; 1121 nvidia,dqs-trim = <40>; 1122 mmc-hs400-1_8v; 1123 status = "disabled"; 1124 }; 1125 1126 mipi: mipi@700e3000 { 1127 compatible = "nvidia,tegra210-mipi"; 1128 reg = <0x0 0x700e3000 0x0 0x100>; 1129 clocks = <&tegra_car TEGRA210_CLK_MIPI_CAL>; 1130 clock-names = "mipi-cal"; 1131 power-domains = <&pd_sor>; 1132 #nvidia,mipi-calibrate-cells = <1>; 1133 }; 1134 1135 dfll: clock@70110000 { 1136 compatible = "nvidia,tegra210-dfll"; 1137 reg = <0 0x70110000 0 0x100>, /* DFLL control */ 1138 <0 0x70110000 0 0x100>, /* I2C output control */ 1139 <0 0x70110100 0 0x100>, /* Integrated I2C controller */ 1140 <0 0x70110200 0 0x100>; /* Look-up table RAM */ 1141 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 1142 clocks = <&tegra_car TEGRA210_CLK_DFLL_SOC>, 1143 <&tegra_car TEGRA210_CLK_DFLL_REF>, 1144 <&tegra_car TEGRA210_CLK_I2C5>; 1145 clock-names = "soc", "ref", "i2c"; 1146 resets = <&tegra_car TEGRA210_RST_DFLL_DVCO>; 1147 reset-names = "dvco"; 1148 #clock-cells = <0>; 1149 clock-output-names = "dfllCPU_out"; 1150 status = "disabled"; 1151 }; 1152 1153 aconnect@702c0000 { 1154 compatible = "nvidia,tegra210-aconnect"; 1155 clocks = <&tegra_car TEGRA210_CLK_APE>, 1156 <&tegra_car TEGRA210_CLK_APB2APE>; 1157 clock-names = "ape", "apb2ape"; 1158 power-domains = <&pd_audio>; 1159 #address-cells = <1>; 1160 #size-cells = <1>; 1161 ranges = <0x702c0000 0x0 0x702c0000 0x00040000>; 1162 status = "disabled"; 1163 1164 adma: dma@702e2000 { 1165 compatible = "nvidia,tegra210-adma"; 1166 reg = <0x702e2000 0x2000>; 1167 interrupt-parent = <&agic>; 1168 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 1169 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 1170 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 1171 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 1172 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 1173 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 1174 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 1175 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 1176 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 1177 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 1178 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 1179 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 1180 <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, 1181 <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, 1182 <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, 1183 <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 1184 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 1185 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 1186 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 1187 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 1188 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 1189 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 1190 #dma-cells = <1>; 1191 clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>; 1192 clock-names = "d_audio"; 1193 status = "disabled"; 1194 }; 1195 1196 agic: agic@702f9000 { 1197 compatible = "nvidia,tegra210-agic"; 1198 #interrupt-cells = <3>; 1199 interrupt-controller; 1200 reg = <0x702f9000 0x2000>, 1201 <0x702fa000 0x2000>; 1202 interrupts = <GIC_SPI 102 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 1203 clocks = <&tegra_car TEGRA210_CLK_APE>; 1204 clock-names = "clk"; 1205 status = "disabled"; 1206 }; 1207 }; 1208 1209 spi@70410000 { 1210 compatible = "nvidia,tegra210-qspi"; 1211 reg = <0x0 0x70410000 0x0 0x1000>; 1212 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 1213 #address-cells = <1>; 1214 #size-cells = <0>; 1215 clocks = <&tegra_car TEGRA210_CLK_QSPI>; 1216 clock-names = "qspi"; 1217 resets = <&tegra_car 211>; 1218 reset-names = "qspi"; 1219 dmas = <&apbdma 5>, <&apbdma 5>; 1220 dma-names = "rx", "tx"; 1221 status = "disabled"; 1222 }; 1223 1224 usb@7d000000 { 1225 compatible = "nvidia,tegra210-ehci", "nvidia,tegra30-ehci", "usb-ehci"; 1226 reg = <0x0 0x7d000000 0x0 0x4000>; 1227 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 1228 phy_type = "utmi"; 1229 clocks = <&tegra_car TEGRA210_CLK_USBD>; 1230 clock-names = "usb"; 1231 resets = <&tegra_car 22>; 1232 reset-names = "usb"; 1233 nvidia,phy = <&phy1>; 1234 status = "disabled"; 1235 }; 1236 1237 phy1: usb-phy@7d000000 { 1238 compatible = "nvidia,tegra210-usb-phy", "nvidia,tegra30-usb-phy"; 1239 reg = <0x0 0x7d000000 0x0 0x4000>, 1240 <0x0 0x7d000000 0x0 0x4000>; 1241 phy_type = "utmi"; 1242 clocks = <&tegra_car TEGRA210_CLK_USBD>, 1243 <&tegra_car TEGRA210_CLK_PLL_U>, 1244 <&tegra_car TEGRA210_CLK_USBD>; 1245 clock-names = "reg", "pll_u", "utmi-pads"; 1246 resets = <&tegra_car 22>, <&tegra_car 22>; 1247 reset-names = "usb", "utmi-pads"; 1248 nvidia,hssync-start-delay = <0>; 1249 nvidia,idle-wait-delay = <17>; 1250 nvidia,elastic-limit = <16>; 1251 nvidia,term-range-adj = <6>; 1252 nvidia,xcvr-setup = <9>; 1253 nvidia,xcvr-lsfslew = <0>; 1254 nvidia,xcvr-lsrslew = <3>; 1255 nvidia,hssquelch-level = <2>; 1256 nvidia,hsdiscon-level = <5>; 1257 nvidia,xcvr-hsslew = <12>; 1258 nvidia,has-utmi-pad-registers; 1259 status = "disabled"; 1260 }; 1261 1262 usb@7d004000 { 1263 compatible = "nvidia,tegra210-ehci", "nvidia,tegra30-ehci", "usb-ehci"; 1264 reg = <0x0 0x7d004000 0x0 0x4000>; 1265 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 1266 phy_type = "utmi"; 1267 clocks = <&tegra_car TEGRA210_CLK_USB2>; 1268 clock-names = "usb"; 1269 resets = <&tegra_car 58>; 1270 reset-names = "usb"; 1271 nvidia,phy = <&phy2>; 1272 status = "disabled"; 1273 }; 1274 1275 phy2: usb-phy@7d004000 { 1276 compatible = "nvidia,tegra210-usb-phy", "nvidia,tegra30-usb-phy"; 1277 reg = <0x0 0x7d004000 0x0 0x4000>, 1278 <0x0 0x7d000000 0x0 0x4000>; 1279 phy_type = "utmi"; 1280 clocks = <&tegra_car TEGRA210_CLK_USB2>, 1281 <&tegra_car TEGRA210_CLK_PLL_U>, 1282 <&tegra_car TEGRA210_CLK_USBD>; 1283 clock-names = "reg", "pll_u", "utmi-pads"; 1284 resets = <&tegra_car 58>, <&tegra_car 22>; 1285 reset-names = "usb", "utmi-pads"; 1286 nvidia,hssync-start-delay = <0>; 1287 nvidia,idle-wait-delay = <17>; 1288 nvidia,elastic-limit = <16>; 1289 nvidia,term-range-adj = <6>; 1290 nvidia,xcvr-setup = <9>; 1291 nvidia,xcvr-lsfslew = <0>; 1292 nvidia,xcvr-lsrslew = <3>; 1293 nvidia,hssquelch-level = <2>; 1294 nvidia,hsdiscon-level = <5>; 1295 nvidia,xcvr-hsslew = <12>; 1296 status = "disabled"; 1297 }; 1298 1299 cpus { 1300 #address-cells = <1>; 1301 #size-cells = <0>; 1302 1303 cpu@0 { 1304 device_type = "cpu"; 1305 compatible = "arm,cortex-a57"; 1306 reg = <0>; 1307 clocks = <&tegra_car TEGRA210_CLK_CCLK_G>, 1308 <&tegra_car TEGRA210_CLK_PLL_X>, 1309 <&tegra_car TEGRA210_CLK_PLL_P_OUT4>, 1310 <&dfll>; 1311 clock-names = "cpu_g", "pll_x", "pll_p", "dfll"; 1312 clock-latency = <300000>; 1313 }; 1314 1315 cpu@1 { 1316 device_type = "cpu"; 1317 compatible = "arm,cortex-a57"; 1318 reg = <1>; 1319 }; 1320 1321 cpu@2 { 1322 device_type = "cpu"; 1323 compatible = "arm,cortex-a57"; 1324 reg = <2>; 1325 }; 1326 1327 cpu@3 { 1328 device_type = "cpu"; 1329 compatible = "arm,cortex-a57"; 1330 reg = <3>; 1331 }; 1332 }; 1333 1334 timer { 1335 compatible = "arm,armv8-timer"; 1336 interrupts = <GIC_PPI 13 1337 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1338 <GIC_PPI 14 1339 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1340 <GIC_PPI 11 1341 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1342 <GIC_PPI 10 1343 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 1344 interrupt-parent = <&gic>; 1345 }; 1346 1347 soctherm: thermal-sensor@700e2000 { 1348 compatible = "nvidia,tegra210-soctherm"; 1349 reg = <0x0 0x700e2000 0x0 0x600 /* SOC_THERM reg_base */ 1350 0x0 0x60006000 0x0 0x400>; /* CAR reg_base */ 1351 reg-names = "soctherm-reg", "car-reg"; 1352 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 1353 clocks = <&tegra_car TEGRA210_CLK_TSENSOR>, 1354 <&tegra_car TEGRA210_CLK_SOC_THERM>; 1355 clock-names = "tsensor", "soctherm"; 1356 resets = <&tegra_car 78>; 1357 reset-names = "soctherm"; 1358 #thermal-sensor-cells = <1>; 1359 1360 throttle-cfgs { 1361 throttle_heavy: heavy { 1362 nvidia,priority = <100>; 1363 nvidia,cpu-throt-percent = <85>; 1364 1365 #cooling-cells = <2>; 1366 }; 1367 }; 1368 }; 1369 1370 thermal-zones { 1371 cpu { 1372 polling-delay-passive = <1000>; 1373 polling-delay = <0>; 1374 1375 thermal-sensors = 1376 <&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>; 1377 1378 trips { 1379 cpu-shutdown-trip { 1380 temperature = <102500>; 1381 hysteresis = <0>; 1382 type = "critical"; 1383 }; 1384 1385 cpu_throttle_trip: throttle-trip { 1386 temperature = <98500>; 1387 hysteresis = <1000>; 1388 type = "hot"; 1389 }; 1390 }; 1391 1392 cooling-maps { 1393 map0 { 1394 trip = <&cpu_throttle_trip>; 1395 cooling-device = <&throttle_heavy 1 1>; 1396 }; 1397 }; 1398 }; 1399 mem { 1400 polling-delay-passive = <0>; 1401 polling-delay = <0>; 1402 1403 thermal-sensors = 1404 <&soctherm TEGRA124_SOCTHERM_SENSOR_MEM>; 1405 1406 trips { 1407 mem-shutdown-trip { 1408 temperature = <103000>; 1409 hysteresis = <0>; 1410 type = "critical"; 1411 }; 1412 }; 1413 1414 cooling-maps { 1415 /* 1416 * There are currently no cooling maps, 1417 * because there are no cooling devices. 1418 */ 1419 }; 1420 }; 1421 gpu { 1422 polling-delay-passive = <1000>; 1423 polling-delay = <0>; 1424 1425 thermal-sensors = 1426 <&soctherm TEGRA124_SOCTHERM_SENSOR_GPU>; 1427 1428 trips { 1429 gpu-shutdown-trip { 1430 temperature = <103000>; 1431 hysteresis = <0>; 1432 type = "critical"; 1433 }; 1434 1435 gpu_throttle_trip: throttle-trip { 1436 temperature = <100000>; 1437 hysteresis = <1000>; 1438 type = "hot"; 1439 }; 1440 }; 1441 1442 cooling-maps { 1443 map0 { 1444 trip = <&gpu_throttle_trip>; 1445 cooling-device = <&throttle_heavy 1 1>; 1446 }; 1447 }; 1448 }; 1449 pllx { 1450 polling-delay-passive = <0>; 1451 polling-delay = <0>; 1452 1453 thermal-sensors = 1454 <&soctherm TEGRA124_SOCTHERM_SENSOR_PLLX>; 1455 1456 trips { 1457 pllx-shutdown-trip { 1458 temperature = <103000>; 1459 hysteresis = <0>; 1460 type = "critical"; 1461 }; 1462 }; 1463 1464 cooling-maps { 1465 /* 1466 * There are currently no cooling maps, 1467 * because there are no cooling devices. 1468 */ 1469 }; 1470 }; 1471 }; 1472}; 1473