1// SPDX-License-Identifier: GPL-2.0 2#include <dt-bindings/clock/tegra210-car.h> 3#include <dt-bindings/gpio/tegra-gpio.h> 4#include <dt-bindings/memory/tegra210-mc.h> 5#include <dt-bindings/pinctrl/pinctrl-tegra.h> 6#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 7#include <dt-bindings/reset/tegra210-car.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/thermal/tegra124-soctherm.h> 10 11/ { 12 compatible = "nvidia,tegra210"; 13 interrupt-parent = <&lic>; 14 #address-cells = <2>; 15 #size-cells = <2>; 16 17 pcie@1003000 { 18 compatible = "nvidia,tegra210-pcie"; 19 device_type = "pci"; 20 reg = <0x0 0x01003000 0x0 0x00000800 /* PADS registers */ 21 0x0 0x01003800 0x0 0x00000800 /* AFI registers */ 22 0x0 0x02000000 0x0 0x10000000>; /* configuration space */ 23 reg-names = "pads", "afi", "cs"; 24 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 25 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 26 interrupt-names = "intr", "msi"; 27 28 #interrupt-cells = <1>; 29 interrupt-map-mask = <0 0 0 0>; 30 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 31 32 bus-range = <0x00 0xff>; 33 #address-cells = <3>; 34 #size-cells = <2>; 35 36 ranges = <0x82000000 0 0x01000000 0x0 0x01000000 0 0x00001000 /* port 0 configuration space */ 37 0x82000000 0 0x01001000 0x0 0x01001000 0 0x00001000 /* port 1 configuration space */ 38 0x81000000 0 0x0 0x0 0x12000000 0 0x00010000 /* downstream I/O (64 KiB) */ 39 0x82000000 0 0x13000000 0x0 0x13000000 0 0x0d000000 /* non-prefetchable memory (208 MiB) */ 40 0xc2000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */ 41 42 clocks = <&tegra_car TEGRA210_CLK_PCIE>, 43 <&tegra_car TEGRA210_CLK_AFI>, 44 <&tegra_car TEGRA210_CLK_PLL_E>, 45 <&tegra_car TEGRA210_CLK_CML0>; 46 clock-names = "pex", "afi", "pll_e", "cml"; 47 resets = <&tegra_car 70>, 48 <&tegra_car 72>, 49 <&tegra_car 74>; 50 reset-names = "pex", "afi", "pcie_x"; 51 status = "disabled"; 52 53 pci@1,0 { 54 device_type = "pci"; 55 assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>; 56 reg = <0x000800 0 0 0 0>; 57 bus-range = <0x00 0xff>; 58 status = "disabled"; 59 60 #address-cells = <3>; 61 #size-cells = <2>; 62 ranges; 63 64 nvidia,num-lanes = <4>; 65 }; 66 67 pci@2,0 { 68 device_type = "pci"; 69 assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>; 70 reg = <0x001000 0 0 0 0>; 71 bus-range = <0x00 0xff>; 72 status = "disabled"; 73 74 #address-cells = <3>; 75 #size-cells = <2>; 76 ranges; 77 78 nvidia,num-lanes = <1>; 79 }; 80 }; 81 82 host1x@50000000 { 83 compatible = "nvidia,tegra210-host1x", "simple-bus"; 84 reg = <0x0 0x50000000 0x0 0x00034000>; 85 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */ 86 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */ 87 clocks = <&tegra_car TEGRA210_CLK_HOST1X>; 88 clock-names = "host1x"; 89 resets = <&tegra_car 28>; 90 reset-names = "host1x"; 91 92 #address-cells = <2>; 93 #size-cells = <2>; 94 95 ranges = <0x0 0x54000000 0x0 0x54000000 0x0 0x01000000>; 96 97 iommus = <&mc TEGRA_SWGROUP_HC>; 98 99 dpaux1: dpaux@54040000 { 100 compatible = "nvidia,tegra210-dpaux"; 101 reg = <0x0 0x54040000 0x0 0x00040000>; 102 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 103 clocks = <&tegra_car TEGRA210_CLK_DPAUX1>, 104 <&tegra_car TEGRA210_CLK_PLL_DP>; 105 clock-names = "dpaux", "parent"; 106 resets = <&tegra_car 207>; 107 reset-names = "dpaux"; 108 power-domains = <&pd_sor>; 109 status = "disabled"; 110 111 state_dpaux1_aux: pinmux-aux { 112 groups = "dpaux-io"; 113 function = "aux"; 114 }; 115 116 state_dpaux1_i2c: pinmux-i2c { 117 groups = "dpaux-io"; 118 function = "i2c"; 119 }; 120 121 state_dpaux1_off: pinmux-off { 122 groups = "dpaux-io"; 123 function = "off"; 124 }; 125 126 i2c-bus { 127 #address-cells = <1>; 128 #size-cells = <0>; 129 }; 130 }; 131 132 vi@54080000 { 133 compatible = "nvidia,tegra210-vi"; 134 reg = <0x0 0x54080000 0x0 0x00040000>; 135 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 136 status = "disabled"; 137 }; 138 139 tsec@54100000 { 140 compatible = "nvidia,tegra210-tsec"; 141 reg = <0x0 0x54100000 0x0 0x00040000>; 142 }; 143 144 dc@54200000 { 145 compatible = "nvidia,tegra210-dc"; 146 reg = <0x0 0x54200000 0x0 0x00040000>; 147 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 148 clocks = <&tegra_car TEGRA210_CLK_DISP1>, 149 <&tegra_car TEGRA210_CLK_PLL_P>; 150 clock-names = "dc", "parent"; 151 resets = <&tegra_car 27>; 152 reset-names = "dc"; 153 154 iommus = <&mc TEGRA_SWGROUP_DC>; 155 156 nvidia,head = <0>; 157 }; 158 159 dc@54240000 { 160 compatible = "nvidia,tegra210-dc"; 161 reg = <0x0 0x54240000 0x0 0x00040000>; 162 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 163 clocks = <&tegra_car TEGRA210_CLK_DISP2>, 164 <&tegra_car TEGRA210_CLK_PLL_P>; 165 clock-names = "dc", "parent"; 166 resets = <&tegra_car 26>; 167 reset-names = "dc"; 168 169 iommus = <&mc TEGRA_SWGROUP_DCB>; 170 171 nvidia,head = <1>; 172 }; 173 174 dsi@54300000 { 175 compatible = "nvidia,tegra210-dsi"; 176 reg = <0x0 0x54300000 0x0 0x00040000>; 177 clocks = <&tegra_car TEGRA210_CLK_DSIA>, 178 <&tegra_car TEGRA210_CLK_DSIALP>, 179 <&tegra_car TEGRA210_CLK_PLL_D_OUT0>; 180 clock-names = "dsi", "lp", "parent"; 181 resets = <&tegra_car 48>; 182 reset-names = "dsi"; 183 power-domains = <&pd_sor>; 184 nvidia,mipi-calibrate = <&mipi 0x0c0>; /* DSIA & DSIB pads */ 185 186 status = "disabled"; 187 188 #address-cells = <1>; 189 #size-cells = <0>; 190 }; 191 192 vic@54340000 { 193 compatible = "nvidia,tegra210-vic"; 194 reg = <0x0 0x54340000 0x0 0x00040000>; 195 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 196 clocks = <&tegra_car TEGRA210_CLK_VIC03>; 197 clock-names = "vic"; 198 resets = <&tegra_car 178>; 199 reset-names = "vic"; 200 201 iommus = <&mc TEGRA_SWGROUP_VIC>; 202 power-domains = <&pd_vic>; 203 }; 204 205 nvjpg@54380000 { 206 compatible = "nvidia,tegra210-nvjpg"; 207 reg = <0x0 0x54380000 0x0 0x00040000>; 208 status = "disabled"; 209 }; 210 211 dsi@54400000 { 212 compatible = "nvidia,tegra210-dsi"; 213 reg = <0x0 0x54400000 0x0 0x00040000>; 214 clocks = <&tegra_car TEGRA210_CLK_DSIB>, 215 <&tegra_car TEGRA210_CLK_DSIBLP>, 216 <&tegra_car TEGRA210_CLK_PLL_D_OUT0>; 217 clock-names = "dsi", "lp", "parent"; 218 resets = <&tegra_car 82>; 219 reset-names = "dsi"; 220 power-domains = <&pd_sor>; 221 nvidia,mipi-calibrate = <&mipi 0x300>; /* DSIC & DSID pads */ 222 223 status = "disabled"; 224 225 #address-cells = <1>; 226 #size-cells = <0>; 227 }; 228 229 nvdec@54480000 { 230 compatible = "nvidia,tegra210-nvdec"; 231 reg = <0x0 0x54480000 0x0 0x00040000>; 232 status = "disabled"; 233 }; 234 235 nvenc@544c0000 { 236 compatible = "nvidia,tegra210-nvenc"; 237 reg = <0x0 0x544c0000 0x0 0x00040000>; 238 status = "disabled"; 239 }; 240 241 tsec@54500000 { 242 compatible = "nvidia,tegra210-tsec"; 243 reg = <0x0 0x54500000 0x0 0x00040000>; 244 status = "disabled"; 245 }; 246 247 sor@54540000 { 248 compatible = "nvidia,tegra210-sor"; 249 reg = <0x0 0x54540000 0x0 0x00040000>; 250 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 251 clocks = <&tegra_car TEGRA210_CLK_SOR0>, 252 <&tegra_car TEGRA210_CLK_PLL_D_OUT0>, 253 <&tegra_car TEGRA210_CLK_PLL_DP>, 254 <&tegra_car TEGRA210_CLK_SOR_SAFE>; 255 clock-names = "sor", "parent", "dp", "safe"; 256 resets = <&tegra_car 182>; 257 reset-names = "sor"; 258 pinctrl-0 = <&state_dpaux_aux>; 259 pinctrl-1 = <&state_dpaux_i2c>; 260 pinctrl-2 = <&state_dpaux_off>; 261 pinctrl-names = "aux", "i2c", "off"; 262 power-domains = <&pd_sor>; 263 status = "disabled"; 264 }; 265 266 sor@54580000 { 267 compatible = "nvidia,tegra210-sor1"; 268 reg = <0x0 0x54580000 0x0 0x00040000>; 269 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 270 clocks = <&tegra_car TEGRA210_CLK_SOR1>, 271 <&tegra_car TEGRA210_CLK_SOR1_OUT>, 272 <&tegra_car TEGRA210_CLK_PLL_D2_OUT0>, 273 <&tegra_car TEGRA210_CLK_PLL_DP>, 274 <&tegra_car TEGRA210_CLK_SOR_SAFE>; 275 clock-names = "sor", "out", "parent", "dp", "safe"; 276 resets = <&tegra_car 183>; 277 reset-names = "sor"; 278 pinctrl-0 = <&state_dpaux1_aux>; 279 pinctrl-1 = <&state_dpaux1_i2c>; 280 pinctrl-2 = <&state_dpaux1_off>; 281 pinctrl-names = "aux", "i2c", "off"; 282 power-domains = <&pd_sor>; 283 status = "disabled"; 284 }; 285 286 dpaux: dpaux@545c0000 { 287 compatible = "nvidia,tegra124-dpaux"; 288 reg = <0x0 0x545c0000 0x0 0x00040000>; 289 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 290 clocks = <&tegra_car TEGRA210_CLK_DPAUX>, 291 <&tegra_car TEGRA210_CLK_PLL_DP>; 292 clock-names = "dpaux", "parent"; 293 resets = <&tegra_car 181>; 294 reset-names = "dpaux"; 295 power-domains = <&pd_sor>; 296 status = "disabled"; 297 298 state_dpaux_aux: pinmux-aux { 299 groups = "dpaux-io"; 300 function = "aux"; 301 }; 302 303 state_dpaux_i2c: pinmux-i2c { 304 groups = "dpaux-io"; 305 function = "i2c"; 306 }; 307 308 state_dpaux_off: pinmux-off { 309 groups = "dpaux-io"; 310 function = "off"; 311 }; 312 313 i2c-bus { 314 #address-cells = <1>; 315 #size-cells = <0>; 316 }; 317 }; 318 319 isp@54600000 { 320 compatible = "nvidia,tegra210-isp"; 321 reg = <0x0 0x54600000 0x0 0x00040000>; 322 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 323 status = "disabled"; 324 }; 325 326 isp@54680000 { 327 compatible = "nvidia,tegra210-isp"; 328 reg = <0x0 0x54680000 0x0 0x00040000>; 329 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 330 status = "disabled"; 331 }; 332 333 i2c@546c0000 { 334 compatible = "nvidia,tegra210-i2c-vi"; 335 reg = <0x0 0x546c0000 0x0 0x00040000>; 336 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 337 status = "disabled"; 338 }; 339 }; 340 341 gic: interrupt-controller@50041000 { 342 compatible = "arm,gic-400"; 343 #interrupt-cells = <3>; 344 interrupt-controller; 345 reg = <0x0 0x50041000 0x0 0x1000>, 346 <0x0 0x50042000 0x0 0x2000>, 347 <0x0 0x50044000 0x0 0x2000>, 348 <0x0 0x50046000 0x0 0x2000>; 349 interrupts = <GIC_PPI 9 350 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 351 interrupt-parent = <&gic>; 352 }; 353 354 gpu@57000000 { 355 compatible = "nvidia,gm20b"; 356 reg = <0x0 0x57000000 0x0 0x01000000>, 357 <0x0 0x58000000 0x0 0x01000000>; 358 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 359 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 360 interrupt-names = "stall", "nonstall"; 361 clocks = <&tegra_car TEGRA210_CLK_GPU>, 362 <&tegra_car TEGRA210_CLK_PLL_P_OUT5>, 363 <&tegra_car TEGRA210_CLK_PLL_G_REF>; 364 clock-names = "gpu", "pwr", "ref"; 365 resets = <&tegra_car 184>; 366 reset-names = "gpu"; 367 368 iommus = <&mc TEGRA_SWGROUP_GPU>; 369 370 status = "disabled"; 371 }; 372 373 lic: interrupt-controller@60004000 { 374 compatible = "nvidia,tegra210-ictlr"; 375 reg = <0x0 0x60004000 0x0 0x40>, /* primary controller */ 376 <0x0 0x60004100 0x0 0x40>, /* secondary controller */ 377 <0x0 0x60004200 0x0 0x40>, /* tertiary controller */ 378 <0x0 0x60004300 0x0 0x40>, /* quaternary controller */ 379 <0x0 0x60004400 0x0 0x40>, /* quinary controller */ 380 <0x0 0x60004500 0x0 0x40>; /* senary controller */ 381 interrupt-controller; 382 #interrupt-cells = <3>; 383 interrupt-parent = <&gic>; 384 }; 385 386 timer@60005000 { 387 compatible = "nvidia,tegra210-timer", "nvidia,tegra20-timer"; 388 reg = <0x0 0x60005000 0x0 0x400>; 389 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 390 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 391 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 392 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 393 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 394 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 395 clocks = <&tegra_car TEGRA210_CLK_TIMER>; 396 clock-names = "timer"; 397 }; 398 399 tegra_car: clock@60006000 { 400 compatible = "nvidia,tegra210-car"; 401 reg = <0x0 0x60006000 0x0 0x1000>; 402 #clock-cells = <1>; 403 #reset-cells = <1>; 404 }; 405 406 flow-controller@60007000 { 407 compatible = "nvidia,tegra210-flowctrl"; 408 reg = <0x0 0x60007000 0x0 0x1000>; 409 }; 410 411 gpio: gpio@6000d000 { 412 compatible = "nvidia,tegra210-gpio", "nvidia,tegra30-gpio"; 413 reg = <0x0 0x6000d000 0x0 0x1000>; 414 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 415 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 416 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 417 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 418 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 419 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 420 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 421 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 422 #gpio-cells = <2>; 423 gpio-controller; 424 #interrupt-cells = <2>; 425 interrupt-controller; 426 }; 427 428 apbdma: dma@60020000 { 429 compatible = "nvidia,tegra210-apbdma", "nvidia,tegra148-apbdma"; 430 reg = <0x0 0x60020000 0x0 0x1400>; 431 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 432 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 433 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 434 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 435 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 436 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 437 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 438 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 439 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 440 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 441 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 442 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 443 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 444 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 445 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 446 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 447 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 448 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 449 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 450 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 451 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 452 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 453 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 454 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 455 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 456 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 457 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 458 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 459 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 460 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 461 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 462 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 463 clocks = <&tegra_car TEGRA210_CLK_APBDMA>; 464 clock-names = "dma"; 465 resets = <&tegra_car 34>; 466 reset-names = "dma"; 467 #dma-cells = <1>; 468 }; 469 470 apbmisc@70000800 { 471 compatible = "nvidia,tegra210-apbmisc", "nvidia,tegra20-apbmisc"; 472 reg = <0x0 0x70000800 0x0 0x64>, /* Chip revision */ 473 <0x0 0x70000008 0x0 0x04>; /* Strapping options */ 474 }; 475 476 pinmux: pinmux@700008d4 { 477 compatible = "nvidia,tegra210-pinmux"; 478 reg = <0x0 0x700008d4 0x0 0x29c>, /* Pad control registers */ 479 <0x0 0x70003000 0x0 0x294>; /* Mux registers */ 480 sdmmc1_3v3_drv: sdmmc1-3v3-drv { 481 sdmmc1 { 482 nvidia,pins = "drive_sdmmc1"; 483 nvidia,pull-down-strength = <0x8>; 484 nvidia,pull-up-strength = <0x8>; 485 }; 486 }; 487 sdmmc1_1v8_drv: sdmmc1-1v8-drv { 488 sdmmc1 { 489 nvidia,pins = "drive_sdmmc1"; 490 nvidia,pull-down-strength = <0x4>; 491 nvidia,pull-up-strength = <0x3>; 492 }; 493 }; 494 sdmmc2_1v8_drv: sdmmc2-1v8-drv { 495 sdmmc2 { 496 nvidia,pins = "drive_sdmmc2"; 497 nvidia,pull-down-strength = <0x10>; 498 nvidia,pull-up-strength = <0x10>; 499 }; 500 }; 501 sdmmc3_3v3_drv: sdmmc3-3v3-drv { 502 sdmmc3 { 503 nvidia,pins = "drive_sdmmc3"; 504 nvidia,pull-down-strength = <0x8>; 505 nvidia,pull-up-strength = <0x8>; 506 }; 507 }; 508 sdmmc3_1v8_drv: sdmmc3-1v8-drv { 509 sdmmc3 { 510 nvidia,pins = "drive_sdmmc3"; 511 nvidia,pull-down-strength = <0x4>; 512 nvidia,pull-up-strength = <0x3>; 513 }; 514 }; 515 sdmmc4_1v8_drv: sdmmc4-1v8-drv { 516 sdmmc4 { 517 nvidia,pins = "drive_sdmmc4"; 518 nvidia,pull-down-strength = <0x10>; 519 nvidia,pull-up-strength = <0x10>; 520 }; 521 }; 522 }; 523 524 /* 525 * There are two serial driver i.e. 8250 based simple serial 526 * driver and APB DMA based serial driver for higher baudrate 527 * and performance. To enable the 8250 based driver, the compatible 528 * is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable 529 * the APB DMA based serial driver, the compatible is 530 * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart". 531 */ 532 uarta: serial@70006000 { 533 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; 534 reg = <0x0 0x70006000 0x0 0x40>; 535 reg-shift = <2>; 536 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 537 clocks = <&tegra_car TEGRA210_CLK_UARTA>; 538 clock-names = "serial"; 539 resets = <&tegra_car 6>; 540 reset-names = "serial"; 541 dmas = <&apbdma 8>, <&apbdma 8>; 542 dma-names = "rx", "tx"; 543 status = "disabled"; 544 }; 545 546 uartb: serial@70006040 { 547 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; 548 reg = <0x0 0x70006040 0x0 0x40>; 549 reg-shift = <2>; 550 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 551 clocks = <&tegra_car TEGRA210_CLK_UARTB>; 552 clock-names = "serial"; 553 resets = <&tegra_car 7>; 554 reset-names = "serial"; 555 dmas = <&apbdma 9>, <&apbdma 9>; 556 dma-names = "rx", "tx"; 557 status = "disabled"; 558 }; 559 560 uartc: serial@70006200 { 561 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; 562 reg = <0x0 0x70006200 0x0 0x40>; 563 reg-shift = <2>; 564 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 565 clocks = <&tegra_car TEGRA210_CLK_UARTC>; 566 clock-names = "serial"; 567 resets = <&tegra_car 55>; 568 reset-names = "serial"; 569 dmas = <&apbdma 10>, <&apbdma 10>; 570 dma-names = "rx", "tx"; 571 status = "disabled"; 572 }; 573 574 uartd: serial@70006300 { 575 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; 576 reg = <0x0 0x70006300 0x0 0x40>; 577 reg-shift = <2>; 578 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 579 clocks = <&tegra_car TEGRA210_CLK_UARTD>; 580 clock-names = "serial"; 581 resets = <&tegra_car 65>; 582 reset-names = "serial"; 583 dmas = <&apbdma 19>, <&apbdma 19>; 584 dma-names = "rx", "tx"; 585 status = "disabled"; 586 }; 587 588 pwm: pwm@7000a000 { 589 compatible = "nvidia,tegra210-pwm", "nvidia,tegra20-pwm"; 590 reg = <0x0 0x7000a000 0x0 0x100>; 591 #pwm-cells = <2>; 592 clocks = <&tegra_car TEGRA210_CLK_PWM>; 593 clock-names = "pwm"; 594 resets = <&tegra_car 17>; 595 reset-names = "pwm"; 596 status = "disabled"; 597 }; 598 599 i2c@7000c000 { 600 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; 601 reg = <0x0 0x7000c000 0x0 0x100>; 602 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 603 #address-cells = <1>; 604 #size-cells = <0>; 605 clocks = <&tegra_car TEGRA210_CLK_I2C1>; 606 clock-names = "div-clk"; 607 resets = <&tegra_car 12>; 608 reset-names = "i2c"; 609 dmas = <&apbdma 21>, <&apbdma 21>; 610 dma-names = "rx", "tx"; 611 status = "disabled"; 612 }; 613 614 i2c@7000c400 { 615 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; 616 reg = <0x0 0x7000c400 0x0 0x100>; 617 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 618 #address-cells = <1>; 619 #size-cells = <0>; 620 clocks = <&tegra_car TEGRA210_CLK_I2C2>; 621 clock-names = "div-clk"; 622 resets = <&tegra_car 54>; 623 reset-names = "i2c"; 624 dmas = <&apbdma 22>, <&apbdma 22>; 625 dma-names = "rx", "tx"; 626 status = "disabled"; 627 }; 628 629 i2c@7000c500 { 630 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; 631 reg = <0x0 0x7000c500 0x0 0x100>; 632 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 633 #address-cells = <1>; 634 #size-cells = <0>; 635 clocks = <&tegra_car TEGRA210_CLK_I2C3>; 636 clock-names = "div-clk"; 637 resets = <&tegra_car 67>; 638 reset-names = "i2c"; 639 dmas = <&apbdma 23>, <&apbdma 23>; 640 dma-names = "rx", "tx"; 641 status = "disabled"; 642 }; 643 644 i2c@7000c700 { 645 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; 646 reg = <0x0 0x7000c700 0x0 0x100>; 647 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 648 #address-cells = <1>; 649 #size-cells = <0>; 650 clocks = <&tegra_car TEGRA210_CLK_I2C4>; 651 clock-names = "div-clk"; 652 resets = <&tegra_car 103>; 653 reset-names = "i2c"; 654 dmas = <&apbdma 26>, <&apbdma 26>; 655 dma-names = "rx", "tx"; 656 pinctrl-0 = <&state_dpaux1_i2c>; 657 pinctrl-1 = <&state_dpaux1_off>; 658 pinctrl-names = "default", "idle"; 659 status = "disabled"; 660 }; 661 662 i2c@7000d000 { 663 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; 664 reg = <0x0 0x7000d000 0x0 0x100>; 665 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 666 #address-cells = <1>; 667 #size-cells = <0>; 668 clocks = <&tegra_car TEGRA210_CLK_I2C5>; 669 clock-names = "div-clk"; 670 resets = <&tegra_car 47>; 671 reset-names = "i2c"; 672 dmas = <&apbdma 24>, <&apbdma 24>; 673 dma-names = "rx", "tx"; 674 status = "disabled"; 675 }; 676 677 i2c@7000d100 { 678 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; 679 reg = <0x0 0x7000d100 0x0 0x100>; 680 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 681 #address-cells = <1>; 682 #size-cells = <0>; 683 clocks = <&tegra_car TEGRA210_CLK_I2C6>; 684 clock-names = "div-clk"; 685 resets = <&tegra_car 166>; 686 reset-names = "i2c"; 687 dmas = <&apbdma 30>, <&apbdma 30>; 688 dma-names = "rx", "tx"; 689 pinctrl-0 = <&state_dpaux_i2c>; 690 pinctrl-1 = <&state_dpaux_off>; 691 pinctrl-names = "default", "idle"; 692 status = "disabled"; 693 }; 694 695 spi@7000d400 { 696 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 697 reg = <0x0 0x7000d400 0x0 0x200>; 698 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 699 #address-cells = <1>; 700 #size-cells = <0>; 701 clocks = <&tegra_car TEGRA210_CLK_SBC1>; 702 clock-names = "spi"; 703 resets = <&tegra_car 41>; 704 reset-names = "spi"; 705 dmas = <&apbdma 15>, <&apbdma 15>; 706 dma-names = "rx", "tx"; 707 status = "disabled"; 708 }; 709 710 spi@7000d600 { 711 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 712 reg = <0x0 0x7000d600 0x0 0x200>; 713 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 714 #address-cells = <1>; 715 #size-cells = <0>; 716 clocks = <&tegra_car TEGRA210_CLK_SBC2>; 717 clock-names = "spi"; 718 resets = <&tegra_car 44>; 719 reset-names = "spi"; 720 dmas = <&apbdma 16>, <&apbdma 16>; 721 dma-names = "rx", "tx"; 722 status = "disabled"; 723 }; 724 725 spi@7000d800 { 726 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 727 reg = <0x0 0x7000d800 0x0 0x200>; 728 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 729 #address-cells = <1>; 730 #size-cells = <0>; 731 clocks = <&tegra_car TEGRA210_CLK_SBC3>; 732 clock-names = "spi"; 733 resets = <&tegra_car 46>; 734 reset-names = "spi"; 735 dmas = <&apbdma 17>, <&apbdma 17>; 736 dma-names = "rx", "tx"; 737 status = "disabled"; 738 }; 739 740 spi@7000da00 { 741 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 742 reg = <0x0 0x7000da00 0x0 0x200>; 743 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 744 #address-cells = <1>; 745 #size-cells = <0>; 746 clocks = <&tegra_car TEGRA210_CLK_SBC4>; 747 clock-names = "spi"; 748 resets = <&tegra_car 68>; 749 reset-names = "spi"; 750 dmas = <&apbdma 18>, <&apbdma 18>; 751 dma-names = "rx", "tx"; 752 status = "disabled"; 753 }; 754 755 rtc@7000e000 { 756 compatible = "nvidia,tegra210-rtc", "nvidia,tegra20-rtc"; 757 reg = <0x0 0x7000e000 0x0 0x100>; 758 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 759 clocks = <&tegra_car TEGRA210_CLK_RTC>; 760 clock-names = "rtc"; 761 }; 762 763 pmc: pmc@7000e400 { 764 compatible = "nvidia,tegra210-pmc"; 765 reg = <0x0 0x7000e400 0x0 0x400>; 766 clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>; 767 clock-names = "pclk", "clk32k_in"; 768 769 powergates { 770 pd_audio: aud { 771 clocks = <&tegra_car TEGRA210_CLK_APE>, 772 <&tegra_car TEGRA210_CLK_APB2APE>; 773 resets = <&tegra_car 198>; 774 #power-domain-cells = <0>; 775 }; 776 777 pd_sor: sor { 778 clocks = <&tegra_car TEGRA210_CLK_SOR0>, 779 <&tegra_car TEGRA210_CLK_SOR1>, 780 <&tegra_car TEGRA210_CLK_CSI>, 781 <&tegra_car TEGRA210_CLK_DSIA>, 782 <&tegra_car TEGRA210_CLK_DSIB>, 783 <&tegra_car TEGRA210_CLK_DPAUX>, 784 <&tegra_car TEGRA210_CLK_DPAUX1>, 785 <&tegra_car TEGRA210_CLK_MIPI_CAL>; 786 resets = <&tegra_car TEGRA210_CLK_SOR0>, 787 <&tegra_car TEGRA210_CLK_SOR1>, 788 <&tegra_car TEGRA210_CLK_CSI>, 789 <&tegra_car TEGRA210_CLK_DSIA>, 790 <&tegra_car TEGRA210_CLK_DSIB>, 791 <&tegra_car TEGRA210_CLK_DPAUX>, 792 <&tegra_car TEGRA210_CLK_DPAUX1>, 793 <&tegra_car TEGRA210_CLK_MIPI_CAL>; 794 #power-domain-cells = <0>; 795 }; 796 797 pd_xusbss: xusba { 798 clocks = <&tegra_car TEGRA210_CLK_XUSB_SS>; 799 resets = <&tegra_car TEGRA210_CLK_XUSB_SS>; 800 #power-domain-cells = <0>; 801 }; 802 803 pd_xusbdev: xusbb { 804 clocks = <&tegra_car TEGRA210_CLK_XUSB_DEV>; 805 resets = <&tegra_car 95>; 806 #power-domain-cells = <0>; 807 }; 808 809 pd_xusbhost: xusbc { 810 clocks = <&tegra_car TEGRA210_CLK_XUSB_HOST>; 811 resets = <&tegra_car TEGRA210_CLK_XUSB_HOST>; 812 #power-domain-cells = <0>; 813 }; 814 815 pd_vic: vic { 816 clocks = <&tegra_car TEGRA210_CLK_VIC03>; 817 clock-names = "vic"; 818 resets = <&tegra_car 178>; 819 reset-names = "vic"; 820 #power-domain-cells = <0>; 821 }; 822 }; 823 824 sdmmc1_3v3: sdmmc1-3v3 { 825 pins = "sdmmc1"; 826 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 827 }; 828 829 sdmmc1_1v8: sdmmc1-1v8 { 830 pins = "sdmmc1"; 831 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 832 }; 833 834 sdmmc3_3v3: sdmmc3-3v3 { 835 pins = "sdmmc3"; 836 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 837 }; 838 839 sdmmc3_1v8: sdmmc3-1v8 { 840 pins = "sdmmc3"; 841 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 842 }; 843 }; 844 845 fuse@7000f800 { 846 compatible = "nvidia,tegra210-efuse"; 847 reg = <0x0 0x7000f800 0x0 0x400>; 848 clocks = <&tegra_car TEGRA210_CLK_FUSE>; 849 clock-names = "fuse"; 850 resets = <&tegra_car 39>; 851 reset-names = "fuse"; 852 }; 853 854 mc: memory-controller@70019000 { 855 compatible = "nvidia,tegra210-mc"; 856 reg = <0x0 0x70019000 0x0 0x1000>; 857 clocks = <&tegra_car TEGRA210_CLK_MC>; 858 clock-names = "mc"; 859 860 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 861 862 #iommu-cells = <1>; 863 }; 864 865 sata@70020000 { 866 compatible = "nvidia,tegra210-ahci"; 867 reg = <0x0 0x70027000 0x0 0x2000>, /* AHCI */ 868 <0x0 0x70020000 0x0 0x7000>, /* SATA */ 869 <0x0 0x70001100 0x0 0x1000>; /* SATA AUX */ 870 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 871 clocks = <&tegra_car TEGRA210_CLK_SATA>, 872 <&tegra_car TEGRA210_CLK_SATA_OOB>; 873 clock-names = "sata", "sata-oob"; 874 resets = <&tegra_car 124>, 875 <&tegra_car 123>, 876 <&tegra_car 129>; 877 reset-names = "sata", "sata-oob", "sata-cold"; 878 status = "disabled"; 879 }; 880 881 hda@70030000 { 882 compatible = "nvidia,tegra210-hda", "nvidia,tegra30-hda"; 883 reg = <0x0 0x70030000 0x0 0x10000>; 884 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 885 clocks = <&tegra_car TEGRA210_CLK_HDA>, 886 <&tegra_car TEGRA210_CLK_HDA2HDMI>, 887 <&tegra_car TEGRA210_CLK_HDA2CODEC_2X>; 888 clock-names = "hda", "hda2hdmi", "hda2codec_2x"; 889 resets = <&tegra_car 125>, /* hda */ 890 <&tegra_car 128>, /* hda2hdmi */ 891 <&tegra_car 111>; /* hda2codec_2x */ 892 reset-names = "hda", "hda2hdmi", "hda2codec_2x"; 893 status = "disabled"; 894 }; 895 896 usb@70090000 { 897 compatible = "nvidia,tegra210-xusb"; 898 reg = <0x0 0x70090000 0x0 0x8000>, 899 <0x0 0x70098000 0x0 0x1000>, 900 <0x0 0x70099000 0x0 0x1000>; 901 reg-names = "hcd", "fpci", "ipfs"; 902 903 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 904 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 905 906 clocks = <&tegra_car TEGRA210_CLK_XUSB_HOST>, 907 <&tegra_car TEGRA210_CLK_XUSB_HOST_SRC>, 908 <&tegra_car TEGRA210_CLK_XUSB_FALCON_SRC>, 909 <&tegra_car TEGRA210_CLK_XUSB_SS>, 910 <&tegra_car TEGRA210_CLK_XUSB_SS_DIV2>, 911 <&tegra_car TEGRA210_CLK_XUSB_SS_SRC>, 912 <&tegra_car TEGRA210_CLK_XUSB_HS_SRC>, 913 <&tegra_car TEGRA210_CLK_XUSB_FS_SRC>, 914 <&tegra_car TEGRA210_CLK_PLL_U_480M>, 915 <&tegra_car TEGRA210_CLK_CLK_M>, 916 <&tegra_car TEGRA210_CLK_PLL_E>; 917 clock-names = "xusb_host", "xusb_host_src", 918 "xusb_falcon_src", "xusb_ss", 919 "xusb_ss_div2", "xusb_ss_src", 920 "xusb_hs_src", "xusb_fs_src", 921 "pll_u_480m", "clk_m", "pll_e"; 922 resets = <&tegra_car 89>, <&tegra_car 156>, 923 <&tegra_car 143>; 924 reset-names = "xusb_host", "xusb_ss", "xusb_src"; 925 power-domains = <&pd_xusbhost>, <&pd_xusbss>; 926 power-domain-names = "xusb_host", "xusb_ss"; 927 928 nvidia,xusb-padctl = <&padctl>; 929 930 status = "disabled"; 931 }; 932 933 padctl: padctl@7009f000 { 934 compatible = "nvidia,tegra210-xusb-padctl"; 935 reg = <0x0 0x7009f000 0x0 0x1000>; 936 resets = <&tegra_car 142>; 937 reset-names = "padctl"; 938 939 status = "disabled"; 940 941 pads { 942 usb2 { 943 clocks = <&tegra_car TEGRA210_CLK_USB2_TRK>; 944 clock-names = "trk"; 945 status = "disabled"; 946 947 lanes { 948 usb2-0 { 949 status = "disabled"; 950 #phy-cells = <0>; 951 }; 952 953 usb2-1 { 954 status = "disabled"; 955 #phy-cells = <0>; 956 }; 957 958 usb2-2 { 959 status = "disabled"; 960 #phy-cells = <0>; 961 }; 962 963 usb2-3 { 964 status = "disabled"; 965 #phy-cells = <0>; 966 }; 967 }; 968 }; 969 970 hsic { 971 clocks = <&tegra_car TEGRA210_CLK_HSIC_TRK>; 972 clock-names = "trk"; 973 status = "disabled"; 974 975 lanes { 976 hsic-0 { 977 status = "disabled"; 978 #phy-cells = <0>; 979 }; 980 981 hsic-1 { 982 status = "disabled"; 983 #phy-cells = <0>; 984 }; 985 }; 986 }; 987 988 pcie { 989 clocks = <&tegra_car TEGRA210_CLK_PLL_E>; 990 clock-names = "pll"; 991 resets = <&tegra_car 205>; 992 reset-names = "phy"; 993 status = "disabled"; 994 995 lanes { 996 pcie-0 { 997 status = "disabled"; 998 #phy-cells = <0>; 999 }; 1000 1001 pcie-1 { 1002 status = "disabled"; 1003 #phy-cells = <0>; 1004 }; 1005 1006 pcie-2 { 1007 status = "disabled"; 1008 #phy-cells = <0>; 1009 }; 1010 1011 pcie-3 { 1012 status = "disabled"; 1013 #phy-cells = <0>; 1014 }; 1015 1016 pcie-4 { 1017 status = "disabled"; 1018 #phy-cells = <0>; 1019 }; 1020 1021 pcie-5 { 1022 status = "disabled"; 1023 #phy-cells = <0>; 1024 }; 1025 1026 pcie-6 { 1027 status = "disabled"; 1028 #phy-cells = <0>; 1029 }; 1030 }; 1031 }; 1032 1033 sata { 1034 clocks = <&tegra_car TEGRA210_CLK_PLL_E>; 1035 clock-names = "pll"; 1036 resets = <&tegra_car 204>; 1037 reset-names = "phy"; 1038 status = "disabled"; 1039 1040 lanes { 1041 sata-0 { 1042 status = "disabled"; 1043 #phy-cells = <0>; 1044 }; 1045 }; 1046 }; 1047 }; 1048 1049 ports { 1050 usb2-0 { 1051 status = "disabled"; 1052 }; 1053 1054 usb2-1 { 1055 status = "disabled"; 1056 }; 1057 1058 usb2-2 { 1059 status = "disabled"; 1060 }; 1061 1062 usb2-3 { 1063 status = "disabled"; 1064 }; 1065 1066 hsic-0 { 1067 status = "disabled"; 1068 }; 1069 1070 usb3-0 { 1071 status = "disabled"; 1072 }; 1073 1074 usb3-1 { 1075 status = "disabled"; 1076 }; 1077 1078 usb3-2 { 1079 status = "disabled"; 1080 }; 1081 1082 usb3-3 { 1083 status = "disabled"; 1084 }; 1085 }; 1086 }; 1087 1088 sdhci@700b0000 { 1089 compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci"; 1090 reg = <0x0 0x700b0000 0x0 0x200>; 1091 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1092 clocks = <&tegra_car TEGRA210_CLK_SDMMC1>; 1093 clock-names = "sdhci"; 1094 resets = <&tegra_car 14>; 1095 reset-names = "sdhci"; 1096 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8", 1097 "sdmmc-3v3-drv", "sdmmc-1v8-drv"; 1098 pinctrl-0 = <&sdmmc1_3v3>; 1099 pinctrl-1 = <&sdmmc1_1v8>; 1100 pinctrl-2 = <&sdmmc1_3v3_drv>; 1101 pinctrl-3 = <&sdmmc1_1v8_drv>; 1102 nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>; 1103 nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>; 1104 nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>; 1105 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7b>; 1106 nvidia,default-tap = <0x2>; 1107 nvidia,default-trim = <0x4>; 1108 assigned-clocks = <&tegra_car TEGRA210_CLK_SDMMC4>, 1109 <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>, 1110 <&tegra_car TEGRA210_CLK_PLL_C4>; 1111 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; 1112 assigned-clock-rates = <200000000>, <1000000000>, <1000000000>; 1113 status = "disabled"; 1114 }; 1115 1116 sdhci@700b0200 { 1117 compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci"; 1118 reg = <0x0 0x700b0200 0x0 0x200>; 1119 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 1120 clocks = <&tegra_car TEGRA210_CLK_SDMMC2>; 1121 clock-names = "sdhci"; 1122 resets = <&tegra_car 9>; 1123 reset-names = "sdhci"; 1124 pinctrl-names = "sdmmc-1v8-drv"; 1125 pinctrl-0 = <&sdmmc2_1v8_drv>; 1126 nvidia,pad-autocal-pull-up-offset-1v8 = <0x05>; 1127 nvidia,pad-autocal-pull-down-offset-1v8 = <0x05>; 1128 nvidia,default-tap = <0x8>; 1129 nvidia,default-trim = <0x0>; 1130 status = "disabled"; 1131 }; 1132 1133 sdhci@700b0400 { 1134 compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci"; 1135 reg = <0x0 0x700b0400 0x0 0x200>; 1136 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 1137 clocks = <&tegra_car TEGRA210_CLK_SDMMC3>; 1138 clock-names = "sdhci"; 1139 resets = <&tegra_car 69>; 1140 reset-names = "sdhci"; 1141 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8", 1142 "sdmmc-3v3-drv", "sdmmc-1v8-drv"; 1143 pinctrl-0 = <&sdmmc3_3v3>; 1144 pinctrl-1 = <&sdmmc3_1v8>; 1145 pinctrl-2 = <&sdmmc3_3v3_drv>; 1146 pinctrl-3 = <&sdmmc3_1v8_drv>; 1147 nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>; 1148 nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>; 1149 nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>; 1150 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7b>; 1151 nvidia,default-tap = <0x3>; 1152 nvidia,default-trim = <0x3>; 1153 status = "disabled"; 1154 }; 1155 1156 sdhci@700b0600 { 1157 compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci"; 1158 reg = <0x0 0x700b0600 0x0 0x200>; 1159 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 1160 clocks = <&tegra_car TEGRA210_CLK_SDMMC4>; 1161 clock-names = "sdhci"; 1162 resets = <&tegra_car 15>; 1163 reset-names = "sdhci"; 1164 pinctrl-names = "sdmmc-3v3-drv", "sdmmc-1v8-drv"; 1165 pinctrl-0 = <&sdmmc4_1v8_drv>; 1166 pinctrl-1 = <&sdmmc4_1v8_drv>; 1167 nvidia,pad-autocal-pull-up-offset-1v8 = <0x05>; 1168 nvidia,pad-autocal-pull-down-offset-1v8 = <0x05>; 1169 nvidia,default-tap = <0x8>; 1170 nvidia,default-trim = <0x0>; 1171 assigned-clocks = <&tegra_car TEGRA210_CLK_SDMMC4>, 1172 <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; 1173 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; 1174 nvidia,dqs-trim = <40>; 1175 mmc-hs400-1_8v; 1176 status = "disabled"; 1177 }; 1178 1179 mipi: mipi@700e3000 { 1180 compatible = "nvidia,tegra210-mipi"; 1181 reg = <0x0 0x700e3000 0x0 0x100>; 1182 clocks = <&tegra_car TEGRA210_CLK_MIPI_CAL>; 1183 clock-names = "mipi-cal"; 1184 power-domains = <&pd_sor>; 1185 #nvidia,mipi-calibrate-cells = <1>; 1186 }; 1187 1188 dfll: clock@70110000 { 1189 compatible = "nvidia,tegra210-dfll"; 1190 reg = <0 0x70110000 0 0x100>, /* DFLL control */ 1191 <0 0x70110000 0 0x100>, /* I2C output control */ 1192 <0 0x70110100 0 0x100>, /* Integrated I2C controller */ 1193 <0 0x70110200 0 0x100>; /* Look-up table RAM */ 1194 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 1195 clocks = <&tegra_car TEGRA210_CLK_DFLL_SOC>, 1196 <&tegra_car TEGRA210_CLK_DFLL_REF>, 1197 <&tegra_car TEGRA210_CLK_I2C5>; 1198 clock-names = "soc", "ref", "i2c"; 1199 resets = <&tegra_car TEGRA210_RST_DFLL_DVCO>; 1200 reset-names = "dvco"; 1201 #clock-cells = <0>; 1202 clock-output-names = "dfllCPU_out"; 1203 status = "disabled"; 1204 }; 1205 1206 aconnect@702c0000 { 1207 compatible = "nvidia,tegra210-aconnect"; 1208 clocks = <&tegra_car TEGRA210_CLK_APE>, 1209 <&tegra_car TEGRA210_CLK_APB2APE>; 1210 clock-names = "ape", "apb2ape"; 1211 power-domains = <&pd_audio>; 1212 #address-cells = <1>; 1213 #size-cells = <1>; 1214 ranges = <0x702c0000 0x0 0x702c0000 0x00040000>; 1215 status = "disabled"; 1216 1217 adma: dma@702e2000 { 1218 compatible = "nvidia,tegra210-adma"; 1219 reg = <0x702e2000 0x2000>; 1220 interrupt-parent = <&agic>; 1221 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 1222 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 1223 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 1224 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 1225 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 1226 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 1227 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 1228 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 1229 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 1230 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 1231 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 1232 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 1233 <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, 1234 <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, 1235 <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, 1236 <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 1237 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 1238 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 1239 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 1240 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 1241 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 1242 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 1243 #dma-cells = <1>; 1244 clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>; 1245 clock-names = "d_audio"; 1246 status = "disabled"; 1247 }; 1248 1249 agic: agic@702f9000 { 1250 compatible = "nvidia,tegra210-agic"; 1251 #interrupt-cells = <3>; 1252 interrupt-controller; 1253 reg = <0x702f9000 0x2000>, 1254 <0x702fa000 0x2000>; 1255 interrupts = <GIC_SPI 102 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 1256 clocks = <&tegra_car TEGRA210_CLK_APE>; 1257 clock-names = "clk"; 1258 status = "disabled"; 1259 }; 1260 }; 1261 1262 spi@70410000 { 1263 compatible = "nvidia,tegra210-qspi"; 1264 reg = <0x0 0x70410000 0x0 0x1000>; 1265 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 1266 #address-cells = <1>; 1267 #size-cells = <0>; 1268 clocks = <&tegra_car TEGRA210_CLK_QSPI>; 1269 clock-names = "qspi"; 1270 resets = <&tegra_car 211>; 1271 reset-names = "qspi"; 1272 dmas = <&apbdma 5>, <&apbdma 5>; 1273 dma-names = "rx", "tx"; 1274 status = "disabled"; 1275 }; 1276 1277 usb@7d000000 { 1278 compatible = "nvidia,tegra210-ehci", "nvidia,tegra30-ehci", "usb-ehci"; 1279 reg = <0x0 0x7d000000 0x0 0x4000>; 1280 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 1281 phy_type = "utmi"; 1282 clocks = <&tegra_car TEGRA210_CLK_USBD>; 1283 clock-names = "usb"; 1284 resets = <&tegra_car 22>; 1285 reset-names = "usb"; 1286 nvidia,phy = <&phy1>; 1287 status = "disabled"; 1288 }; 1289 1290 phy1: usb-phy@7d000000 { 1291 compatible = "nvidia,tegra210-usb-phy", "nvidia,tegra30-usb-phy"; 1292 reg = <0x0 0x7d000000 0x0 0x4000>, 1293 <0x0 0x7d000000 0x0 0x4000>; 1294 phy_type = "utmi"; 1295 clocks = <&tegra_car TEGRA210_CLK_USBD>, 1296 <&tegra_car TEGRA210_CLK_PLL_U>, 1297 <&tegra_car TEGRA210_CLK_USBD>; 1298 clock-names = "reg", "pll_u", "utmi-pads"; 1299 resets = <&tegra_car 22>, <&tegra_car 22>; 1300 reset-names = "usb", "utmi-pads"; 1301 nvidia,hssync-start-delay = <0>; 1302 nvidia,idle-wait-delay = <17>; 1303 nvidia,elastic-limit = <16>; 1304 nvidia,term-range-adj = <6>; 1305 nvidia,xcvr-setup = <9>; 1306 nvidia,xcvr-lsfslew = <0>; 1307 nvidia,xcvr-lsrslew = <3>; 1308 nvidia,hssquelch-level = <2>; 1309 nvidia,hsdiscon-level = <5>; 1310 nvidia,xcvr-hsslew = <12>; 1311 nvidia,has-utmi-pad-registers; 1312 status = "disabled"; 1313 }; 1314 1315 usb@7d004000 { 1316 compatible = "nvidia,tegra210-ehci", "nvidia,tegra30-ehci", "usb-ehci"; 1317 reg = <0x0 0x7d004000 0x0 0x4000>; 1318 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 1319 phy_type = "utmi"; 1320 clocks = <&tegra_car TEGRA210_CLK_USB2>; 1321 clock-names = "usb"; 1322 resets = <&tegra_car 58>; 1323 reset-names = "usb"; 1324 nvidia,phy = <&phy2>; 1325 status = "disabled"; 1326 }; 1327 1328 phy2: usb-phy@7d004000 { 1329 compatible = "nvidia,tegra210-usb-phy", "nvidia,tegra30-usb-phy"; 1330 reg = <0x0 0x7d004000 0x0 0x4000>, 1331 <0x0 0x7d000000 0x0 0x4000>; 1332 phy_type = "utmi"; 1333 clocks = <&tegra_car TEGRA210_CLK_USB2>, 1334 <&tegra_car TEGRA210_CLK_PLL_U>, 1335 <&tegra_car TEGRA210_CLK_USBD>; 1336 clock-names = "reg", "pll_u", "utmi-pads"; 1337 resets = <&tegra_car 58>, <&tegra_car 22>; 1338 reset-names = "usb", "utmi-pads"; 1339 nvidia,hssync-start-delay = <0>; 1340 nvidia,idle-wait-delay = <17>; 1341 nvidia,elastic-limit = <16>; 1342 nvidia,term-range-adj = <6>; 1343 nvidia,xcvr-setup = <9>; 1344 nvidia,xcvr-lsfslew = <0>; 1345 nvidia,xcvr-lsrslew = <3>; 1346 nvidia,hssquelch-level = <2>; 1347 nvidia,hsdiscon-level = <5>; 1348 nvidia,xcvr-hsslew = <12>; 1349 status = "disabled"; 1350 }; 1351 1352 cpus { 1353 #address-cells = <1>; 1354 #size-cells = <0>; 1355 1356 cpu@0 { 1357 device_type = "cpu"; 1358 compatible = "arm,cortex-a57"; 1359 reg = <0>; 1360 clocks = <&tegra_car TEGRA210_CLK_CCLK_G>, 1361 <&tegra_car TEGRA210_CLK_PLL_X>, 1362 <&tegra_car TEGRA210_CLK_PLL_P_OUT4>, 1363 <&dfll>; 1364 clock-names = "cpu_g", "pll_x", "pll_p", "dfll"; 1365 clock-latency = <300000>; 1366 }; 1367 1368 cpu@1 { 1369 device_type = "cpu"; 1370 compatible = "arm,cortex-a57"; 1371 reg = <1>; 1372 }; 1373 1374 cpu@2 { 1375 device_type = "cpu"; 1376 compatible = "arm,cortex-a57"; 1377 reg = <2>; 1378 }; 1379 1380 cpu@3 { 1381 device_type = "cpu"; 1382 compatible = "arm,cortex-a57"; 1383 reg = <3>; 1384 }; 1385 }; 1386 1387 timer { 1388 compatible = "arm,armv8-timer"; 1389 interrupts = <GIC_PPI 13 1390 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1391 <GIC_PPI 14 1392 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1393 <GIC_PPI 11 1394 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1395 <GIC_PPI 10 1396 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 1397 interrupt-parent = <&gic>; 1398 }; 1399 1400 soctherm: thermal-sensor@700e2000 { 1401 compatible = "nvidia,tegra210-soctherm"; 1402 reg = <0x0 0x700e2000 0x0 0x600 /* SOC_THERM reg_base */ 1403 0x0 0x60006000 0x0 0x400>; /* CAR reg_base */ 1404 reg-names = "soctherm-reg", "car-reg"; 1405 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 1406 clocks = <&tegra_car TEGRA210_CLK_TSENSOR>, 1407 <&tegra_car TEGRA210_CLK_SOC_THERM>; 1408 clock-names = "tsensor", "soctherm"; 1409 resets = <&tegra_car 78>; 1410 reset-names = "soctherm"; 1411 #thermal-sensor-cells = <1>; 1412 1413 throttle-cfgs { 1414 throttle_heavy: heavy { 1415 nvidia,priority = <100>; 1416 nvidia,cpu-throt-percent = <85>; 1417 1418 #cooling-cells = <2>; 1419 }; 1420 }; 1421 }; 1422 1423 thermal-zones { 1424 cpu { 1425 polling-delay-passive = <1000>; 1426 polling-delay = <0>; 1427 1428 thermal-sensors = 1429 <&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>; 1430 1431 trips { 1432 cpu-shutdown-trip { 1433 temperature = <102500>; 1434 hysteresis = <0>; 1435 type = "critical"; 1436 }; 1437 1438 cpu_throttle_trip: throttle-trip { 1439 temperature = <98500>; 1440 hysteresis = <1000>; 1441 type = "hot"; 1442 }; 1443 }; 1444 1445 cooling-maps { 1446 map0 { 1447 trip = <&cpu_throttle_trip>; 1448 cooling-device = <&throttle_heavy 1 1>; 1449 }; 1450 }; 1451 }; 1452 mem { 1453 polling-delay-passive = <0>; 1454 polling-delay = <0>; 1455 1456 thermal-sensors = 1457 <&soctherm TEGRA124_SOCTHERM_SENSOR_MEM>; 1458 1459 trips { 1460 mem-shutdown-trip { 1461 temperature = <103000>; 1462 hysteresis = <0>; 1463 type = "critical"; 1464 }; 1465 }; 1466 1467 cooling-maps { 1468 /* 1469 * There are currently no cooling maps, 1470 * because there are no cooling devices. 1471 */ 1472 }; 1473 }; 1474 gpu { 1475 polling-delay-passive = <1000>; 1476 polling-delay = <0>; 1477 1478 thermal-sensors = 1479 <&soctherm TEGRA124_SOCTHERM_SENSOR_GPU>; 1480 1481 trips { 1482 gpu-shutdown-trip { 1483 temperature = <103000>; 1484 hysteresis = <0>; 1485 type = "critical"; 1486 }; 1487 1488 gpu_throttle_trip: throttle-trip { 1489 temperature = <100000>; 1490 hysteresis = <1000>; 1491 type = "hot"; 1492 }; 1493 }; 1494 1495 cooling-maps { 1496 map0 { 1497 trip = <&gpu_throttle_trip>; 1498 cooling-device = <&throttle_heavy 1 1>; 1499 }; 1500 }; 1501 }; 1502 pllx { 1503 polling-delay-passive = <0>; 1504 polling-delay = <0>; 1505 1506 thermal-sensors = 1507 <&soctherm TEGRA124_SOCTHERM_SENSOR_PLLX>; 1508 1509 trips { 1510 pllx-shutdown-trip { 1511 temperature = <103000>; 1512 hysteresis = <0>; 1513 type = "critical"; 1514 }; 1515 }; 1516 1517 cooling-maps { 1518 /* 1519 * There are currently no cooling maps, 1520 * because there are no cooling devices. 1521 */ 1522 }; 1523 }; 1524 }; 1525}; 1526