1// SPDX-License-Identifier: GPL-2.0 2#include <dt-bindings/clock/tegra210-car.h> 3#include <dt-bindings/gpio/tegra-gpio.h> 4#include <dt-bindings/memory/tegra210-mc.h> 5#include <dt-bindings/pinctrl/pinctrl-tegra.h> 6#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 7#include <dt-bindings/reset/tegra210-car.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/thermal/tegra124-soctherm.h> 10 11/ { 12 compatible = "nvidia,tegra210"; 13 interrupt-parent = <&lic>; 14 #address-cells = <2>; 15 #size-cells = <2>; 16 17 pcie@1003000 { 18 compatible = "nvidia,tegra210-pcie"; 19 device_type = "pci"; 20 reg = <0x0 0x01003000 0x0 0x00000800 /* PADS registers */ 21 0x0 0x01003800 0x0 0x00000800 /* AFI registers */ 22 0x0 0x02000000 0x0 0x10000000>; /* configuration space */ 23 reg-names = "pads", "afi", "cs"; 24 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 25 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 26 interrupt-names = "intr", "msi"; 27 28 #interrupt-cells = <1>; 29 interrupt-map-mask = <0 0 0 0>; 30 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 31 32 bus-range = <0x00 0xff>; 33 #address-cells = <3>; 34 #size-cells = <2>; 35 36 ranges = <0x82000000 0 0x01000000 0x0 0x01000000 0 0x00001000 /* port 0 configuration space */ 37 0x82000000 0 0x01001000 0x0 0x01001000 0 0x00001000 /* port 1 configuration space */ 38 0x81000000 0 0x0 0x0 0x12000000 0 0x00010000 /* downstream I/O (64 KiB) */ 39 0x82000000 0 0x13000000 0x0 0x13000000 0 0x0d000000 /* non-prefetchable memory (208 MiB) */ 40 0xc2000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */ 41 42 clocks = <&tegra_car TEGRA210_CLK_PCIE>, 43 <&tegra_car TEGRA210_CLK_AFI>, 44 <&tegra_car TEGRA210_CLK_PLL_E>, 45 <&tegra_car TEGRA210_CLK_CML0>; 46 clock-names = "pex", "afi", "pll_e", "cml"; 47 resets = <&tegra_car 70>, 48 <&tegra_car 72>, 49 <&tegra_car 74>; 50 reset-names = "pex", "afi", "pcie_x"; 51 status = "disabled"; 52 53 pci@1,0 { 54 device_type = "pci"; 55 assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>; 56 reg = <0x000800 0 0 0 0>; 57 bus-range = <0x00 0xff>; 58 status = "disabled"; 59 60 #address-cells = <3>; 61 #size-cells = <2>; 62 ranges; 63 64 nvidia,num-lanes = <4>; 65 }; 66 67 pci@2,0 { 68 device_type = "pci"; 69 assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>; 70 reg = <0x001000 0 0 0 0>; 71 bus-range = <0x00 0xff>; 72 status = "disabled"; 73 74 #address-cells = <3>; 75 #size-cells = <2>; 76 ranges; 77 78 nvidia,num-lanes = <1>; 79 }; 80 }; 81 82 host1x@50000000 { 83 compatible = "nvidia,tegra210-host1x", "simple-bus"; 84 reg = <0x0 0x50000000 0x0 0x00034000>; 85 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */ 86 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */ 87 clocks = <&tegra_car TEGRA210_CLK_HOST1X>; 88 clock-names = "host1x"; 89 resets = <&tegra_car 28>; 90 reset-names = "host1x"; 91 92 #address-cells = <2>; 93 #size-cells = <2>; 94 95 ranges = <0x0 0x54000000 0x0 0x54000000 0x0 0x01000000>; 96 97 iommus = <&mc TEGRA_SWGROUP_HC>; 98 99 dpaux1: dpaux@54040000 { 100 compatible = "nvidia,tegra210-dpaux"; 101 reg = <0x0 0x54040000 0x0 0x00040000>; 102 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 103 clocks = <&tegra_car TEGRA210_CLK_DPAUX1>, 104 <&tegra_car TEGRA210_CLK_PLL_DP>; 105 clock-names = "dpaux", "parent"; 106 resets = <&tegra_car 207>; 107 reset-names = "dpaux"; 108 power-domains = <&pd_sor>; 109 status = "disabled"; 110 111 state_dpaux1_aux: pinmux-aux { 112 groups = "dpaux-io"; 113 function = "aux"; 114 }; 115 116 state_dpaux1_i2c: pinmux-i2c { 117 groups = "dpaux-io"; 118 function = "i2c"; 119 }; 120 121 state_dpaux1_off: pinmux-off { 122 groups = "dpaux-io"; 123 function = "off"; 124 }; 125 126 i2c-bus { 127 #address-cells = <1>; 128 #size-cells = <0>; 129 }; 130 }; 131 132 vi@54080000 { 133 compatible = "nvidia,tegra210-vi"; 134 reg = <0x0 0x54080000 0x0 0x00040000>; 135 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 136 status = "disabled"; 137 }; 138 139 tsec@54100000 { 140 compatible = "nvidia,tegra210-tsec"; 141 reg = <0x0 0x54100000 0x0 0x00040000>; 142 }; 143 144 dc@54200000 { 145 compatible = "nvidia,tegra210-dc"; 146 reg = <0x0 0x54200000 0x0 0x00040000>; 147 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 148 clocks = <&tegra_car TEGRA210_CLK_DISP1>, 149 <&tegra_car TEGRA210_CLK_PLL_P>; 150 clock-names = "dc", "parent"; 151 resets = <&tegra_car 27>; 152 reset-names = "dc"; 153 154 iommus = <&mc TEGRA_SWGROUP_DC>; 155 156 nvidia,head = <0>; 157 }; 158 159 dc@54240000 { 160 compatible = "nvidia,tegra210-dc"; 161 reg = <0x0 0x54240000 0x0 0x00040000>; 162 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 163 clocks = <&tegra_car TEGRA210_CLK_DISP2>, 164 <&tegra_car TEGRA210_CLK_PLL_P>; 165 clock-names = "dc", "parent"; 166 resets = <&tegra_car 26>; 167 reset-names = "dc"; 168 169 iommus = <&mc TEGRA_SWGROUP_DCB>; 170 171 nvidia,head = <1>; 172 }; 173 174 dsi@54300000 { 175 compatible = "nvidia,tegra210-dsi"; 176 reg = <0x0 0x54300000 0x0 0x00040000>; 177 clocks = <&tegra_car TEGRA210_CLK_DSIA>, 178 <&tegra_car TEGRA210_CLK_DSIALP>, 179 <&tegra_car TEGRA210_CLK_PLL_D_OUT0>; 180 clock-names = "dsi", "lp", "parent"; 181 resets = <&tegra_car 48>; 182 reset-names = "dsi"; 183 power-domains = <&pd_sor>; 184 nvidia,mipi-calibrate = <&mipi 0x0c0>; /* DSIA & DSIB pads */ 185 186 status = "disabled"; 187 188 #address-cells = <1>; 189 #size-cells = <0>; 190 }; 191 192 vic@54340000 { 193 compatible = "nvidia,tegra210-vic"; 194 reg = <0x0 0x54340000 0x0 0x00040000>; 195 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 196 clocks = <&tegra_car TEGRA210_CLK_VIC03>; 197 clock-names = "vic"; 198 resets = <&tegra_car 178>; 199 reset-names = "vic"; 200 201 iommus = <&mc TEGRA_SWGROUP_VIC>; 202 power-domains = <&pd_vic>; 203 }; 204 205 nvjpg@54380000 { 206 compatible = "nvidia,tegra210-nvjpg"; 207 reg = <0x0 0x54380000 0x0 0x00040000>; 208 status = "disabled"; 209 }; 210 211 dsi@54400000 { 212 compatible = "nvidia,tegra210-dsi"; 213 reg = <0x0 0x54400000 0x0 0x00040000>; 214 clocks = <&tegra_car TEGRA210_CLK_DSIB>, 215 <&tegra_car TEGRA210_CLK_DSIBLP>, 216 <&tegra_car TEGRA210_CLK_PLL_D_OUT0>; 217 clock-names = "dsi", "lp", "parent"; 218 resets = <&tegra_car 82>; 219 reset-names = "dsi"; 220 power-domains = <&pd_sor>; 221 nvidia,mipi-calibrate = <&mipi 0x300>; /* DSIC & DSID pads */ 222 223 status = "disabled"; 224 225 #address-cells = <1>; 226 #size-cells = <0>; 227 }; 228 229 nvdec@54480000 { 230 compatible = "nvidia,tegra210-nvdec"; 231 reg = <0x0 0x54480000 0x0 0x00040000>; 232 status = "disabled"; 233 }; 234 235 nvenc@544c0000 { 236 compatible = "nvidia,tegra210-nvenc"; 237 reg = <0x0 0x544c0000 0x0 0x00040000>; 238 status = "disabled"; 239 }; 240 241 tsec@54500000 { 242 compatible = "nvidia,tegra210-tsec"; 243 reg = <0x0 0x54500000 0x0 0x00040000>; 244 status = "disabled"; 245 }; 246 247 sor@54540000 { 248 compatible = "nvidia,tegra210-sor"; 249 reg = <0x0 0x54540000 0x0 0x00040000>; 250 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 251 clocks = <&tegra_car TEGRA210_CLK_SOR0>, 252 <&tegra_car TEGRA210_CLK_PLL_D_OUT0>, 253 <&tegra_car TEGRA210_CLK_PLL_DP>, 254 <&tegra_car TEGRA210_CLK_SOR_SAFE>; 255 clock-names = "sor", "parent", "dp", "safe"; 256 resets = <&tegra_car 182>; 257 reset-names = "sor"; 258 pinctrl-0 = <&state_dpaux_aux>; 259 pinctrl-1 = <&state_dpaux_i2c>; 260 pinctrl-2 = <&state_dpaux_off>; 261 pinctrl-names = "aux", "i2c", "off"; 262 power-domains = <&pd_sor>; 263 status = "disabled"; 264 }; 265 266 sor@54580000 { 267 compatible = "nvidia,tegra210-sor1"; 268 reg = <0x0 0x54580000 0x0 0x00040000>; 269 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 270 clocks = <&tegra_car TEGRA210_CLK_SOR1>, 271 <&tegra_car TEGRA210_CLK_SOR1_OUT>, 272 <&tegra_car TEGRA210_CLK_PLL_D2_OUT0>, 273 <&tegra_car TEGRA210_CLK_PLL_DP>, 274 <&tegra_car TEGRA210_CLK_SOR_SAFE>; 275 clock-names = "sor", "out", "parent", "dp", "safe"; 276 resets = <&tegra_car 183>; 277 reset-names = "sor"; 278 pinctrl-0 = <&state_dpaux1_aux>; 279 pinctrl-1 = <&state_dpaux1_i2c>; 280 pinctrl-2 = <&state_dpaux1_off>; 281 pinctrl-names = "aux", "i2c", "off"; 282 power-domains = <&pd_sor>; 283 status = "disabled"; 284 }; 285 286 dpaux: dpaux@545c0000 { 287 compatible = "nvidia,tegra124-dpaux"; 288 reg = <0x0 0x545c0000 0x0 0x00040000>; 289 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 290 clocks = <&tegra_car TEGRA210_CLK_DPAUX>, 291 <&tegra_car TEGRA210_CLK_PLL_DP>; 292 clock-names = "dpaux", "parent"; 293 resets = <&tegra_car 181>; 294 reset-names = "dpaux"; 295 power-domains = <&pd_sor>; 296 status = "disabled"; 297 298 state_dpaux_aux: pinmux-aux { 299 groups = "dpaux-io"; 300 function = "aux"; 301 }; 302 303 state_dpaux_i2c: pinmux-i2c { 304 groups = "dpaux-io"; 305 function = "i2c"; 306 }; 307 308 state_dpaux_off: pinmux-off { 309 groups = "dpaux-io"; 310 function = "off"; 311 }; 312 313 i2c-bus { 314 #address-cells = <1>; 315 #size-cells = <0>; 316 }; 317 }; 318 319 isp@54600000 { 320 compatible = "nvidia,tegra210-isp"; 321 reg = <0x0 0x54600000 0x0 0x00040000>; 322 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 323 status = "disabled"; 324 }; 325 326 isp@54680000 { 327 compatible = "nvidia,tegra210-isp"; 328 reg = <0x0 0x54680000 0x0 0x00040000>; 329 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 330 status = "disabled"; 331 }; 332 333 i2c@546c0000 { 334 compatible = "nvidia,tegra210-i2c-vi"; 335 reg = <0x0 0x546c0000 0x0 0x00040000>; 336 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 337 status = "disabled"; 338 }; 339 }; 340 341 gic: interrupt-controller@50041000 { 342 compatible = "arm,gic-400"; 343 #interrupt-cells = <3>; 344 interrupt-controller; 345 reg = <0x0 0x50041000 0x0 0x1000>, 346 <0x0 0x50042000 0x0 0x2000>, 347 <0x0 0x50044000 0x0 0x2000>, 348 <0x0 0x50046000 0x0 0x2000>; 349 interrupts = <GIC_PPI 9 350 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 351 interrupt-parent = <&gic>; 352 }; 353 354 gpu@57000000 { 355 compatible = "nvidia,gm20b"; 356 reg = <0x0 0x57000000 0x0 0x01000000>, 357 <0x0 0x58000000 0x0 0x01000000>; 358 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 359 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 360 interrupt-names = "stall", "nonstall"; 361 clocks = <&tegra_car TEGRA210_CLK_GPU>, 362 <&tegra_car TEGRA210_CLK_PLL_P_OUT5>, 363 <&tegra_car TEGRA210_CLK_PLL_G_REF>; 364 clock-names = "gpu", "pwr", "ref"; 365 resets = <&tegra_car 184>; 366 reset-names = "gpu"; 367 368 iommus = <&mc TEGRA_SWGROUP_GPU>; 369 370 status = "disabled"; 371 }; 372 373 lic: interrupt-controller@60004000 { 374 compatible = "nvidia,tegra210-ictlr"; 375 reg = <0x0 0x60004000 0x0 0x40>, /* primary controller */ 376 <0x0 0x60004100 0x0 0x40>, /* secondary controller */ 377 <0x0 0x60004200 0x0 0x40>, /* tertiary controller */ 378 <0x0 0x60004300 0x0 0x40>, /* quaternary controller */ 379 <0x0 0x60004400 0x0 0x40>, /* quinary controller */ 380 <0x0 0x60004500 0x0 0x40>; /* senary controller */ 381 interrupt-controller; 382 #interrupt-cells = <3>; 383 interrupt-parent = <&gic>; 384 }; 385 386 timer@60005000 { 387 compatible = "nvidia,tegra210-timer"; 388 reg = <0x0 0x60005000 0x0 0x400>; 389 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, 390 <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 391 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 392 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 393 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 394 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 395 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 396 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 397 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 398 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 399 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 400 <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>, 401 <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>, 402 <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; 403 clocks = <&tegra_car TEGRA210_CLK_TIMER>; 404 clock-names = "timer"; 405 }; 406 407 tegra_car: clock@60006000 { 408 compatible = "nvidia,tegra210-car"; 409 reg = <0x0 0x60006000 0x0 0x1000>; 410 #clock-cells = <1>; 411 #reset-cells = <1>; 412 }; 413 414 flow-controller@60007000 { 415 compatible = "nvidia,tegra210-flowctrl"; 416 reg = <0x0 0x60007000 0x0 0x1000>; 417 }; 418 419 gpio: gpio@6000d000 { 420 compatible = "nvidia,tegra210-gpio", "nvidia,tegra30-gpio"; 421 reg = <0x0 0x6000d000 0x0 0x1000>; 422 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 423 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 424 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 425 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 426 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 427 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 428 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 429 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 430 #gpio-cells = <2>; 431 gpio-controller; 432 #interrupt-cells = <2>; 433 interrupt-controller; 434 }; 435 436 apbdma: dma@60020000 { 437 compatible = "nvidia,tegra210-apbdma", "nvidia,tegra148-apbdma"; 438 reg = <0x0 0x60020000 0x0 0x1400>; 439 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 440 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 441 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 442 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 443 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 444 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 445 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 446 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 447 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 448 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 449 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 450 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 451 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 452 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 453 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 454 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 455 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 456 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 457 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 458 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 459 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 460 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 461 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 462 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 463 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 464 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 465 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 466 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 467 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 468 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 469 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 470 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 471 clocks = <&tegra_car TEGRA210_CLK_APBDMA>; 472 clock-names = "dma"; 473 resets = <&tegra_car 34>; 474 reset-names = "dma"; 475 #dma-cells = <1>; 476 }; 477 478 apbmisc@70000800 { 479 compatible = "nvidia,tegra210-apbmisc", "nvidia,tegra20-apbmisc"; 480 reg = <0x0 0x70000800 0x0 0x64>, /* Chip revision */ 481 <0x0 0x70000008 0x0 0x04>; /* Strapping options */ 482 }; 483 484 pinmux: pinmux@700008d4 { 485 compatible = "nvidia,tegra210-pinmux"; 486 reg = <0x0 0x700008d4 0x0 0x29c>, /* Pad control registers */ 487 <0x0 0x70003000 0x0 0x294>; /* Mux registers */ 488 sdmmc1_3v3_drv: sdmmc1-3v3-drv { 489 sdmmc1 { 490 nvidia,pins = "drive_sdmmc1"; 491 nvidia,pull-down-strength = <0x8>; 492 nvidia,pull-up-strength = <0x8>; 493 }; 494 }; 495 sdmmc1_1v8_drv: sdmmc1-1v8-drv { 496 sdmmc1 { 497 nvidia,pins = "drive_sdmmc1"; 498 nvidia,pull-down-strength = <0x4>; 499 nvidia,pull-up-strength = <0x3>; 500 }; 501 }; 502 sdmmc2_1v8_drv: sdmmc2-1v8-drv { 503 sdmmc2 { 504 nvidia,pins = "drive_sdmmc2"; 505 nvidia,pull-down-strength = <0x10>; 506 nvidia,pull-up-strength = <0x10>; 507 }; 508 }; 509 sdmmc3_3v3_drv: sdmmc3-3v3-drv { 510 sdmmc3 { 511 nvidia,pins = "drive_sdmmc3"; 512 nvidia,pull-down-strength = <0x8>; 513 nvidia,pull-up-strength = <0x8>; 514 }; 515 }; 516 sdmmc3_1v8_drv: sdmmc3-1v8-drv { 517 sdmmc3 { 518 nvidia,pins = "drive_sdmmc3"; 519 nvidia,pull-down-strength = <0x4>; 520 nvidia,pull-up-strength = <0x3>; 521 }; 522 }; 523 sdmmc4_1v8_drv: sdmmc4-1v8-drv { 524 sdmmc4 { 525 nvidia,pins = "drive_sdmmc4"; 526 nvidia,pull-down-strength = <0x10>; 527 nvidia,pull-up-strength = <0x10>; 528 }; 529 }; 530 }; 531 532 /* 533 * There are two serial driver i.e. 8250 based simple serial 534 * driver and APB DMA based serial driver for higher baudrate 535 * and performance. To enable the 8250 based driver, the compatible 536 * is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable 537 * the APB DMA based serial driver, the compatible is 538 * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart". 539 */ 540 uarta: serial@70006000 { 541 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; 542 reg = <0x0 0x70006000 0x0 0x40>; 543 reg-shift = <2>; 544 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 545 clocks = <&tegra_car TEGRA210_CLK_UARTA>; 546 clock-names = "serial"; 547 resets = <&tegra_car 6>; 548 reset-names = "serial"; 549 dmas = <&apbdma 8>, <&apbdma 8>; 550 dma-names = "rx", "tx"; 551 status = "disabled"; 552 }; 553 554 uartb: serial@70006040 { 555 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; 556 reg = <0x0 0x70006040 0x0 0x40>; 557 reg-shift = <2>; 558 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 559 clocks = <&tegra_car TEGRA210_CLK_UARTB>; 560 clock-names = "serial"; 561 resets = <&tegra_car 7>; 562 reset-names = "serial"; 563 dmas = <&apbdma 9>, <&apbdma 9>; 564 dma-names = "rx", "tx"; 565 status = "disabled"; 566 }; 567 568 uartc: serial@70006200 { 569 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; 570 reg = <0x0 0x70006200 0x0 0x40>; 571 reg-shift = <2>; 572 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 573 clocks = <&tegra_car TEGRA210_CLK_UARTC>; 574 clock-names = "serial"; 575 resets = <&tegra_car 55>; 576 reset-names = "serial"; 577 dmas = <&apbdma 10>, <&apbdma 10>; 578 dma-names = "rx", "tx"; 579 status = "disabled"; 580 }; 581 582 uartd: serial@70006300 { 583 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; 584 reg = <0x0 0x70006300 0x0 0x40>; 585 reg-shift = <2>; 586 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 587 clocks = <&tegra_car TEGRA210_CLK_UARTD>; 588 clock-names = "serial"; 589 resets = <&tegra_car 65>; 590 reset-names = "serial"; 591 dmas = <&apbdma 19>, <&apbdma 19>; 592 dma-names = "rx", "tx"; 593 status = "disabled"; 594 }; 595 596 pwm: pwm@7000a000 { 597 compatible = "nvidia,tegra210-pwm", "nvidia,tegra20-pwm"; 598 reg = <0x0 0x7000a000 0x0 0x100>; 599 #pwm-cells = <2>; 600 clocks = <&tegra_car TEGRA210_CLK_PWM>; 601 clock-names = "pwm"; 602 resets = <&tegra_car 17>; 603 reset-names = "pwm"; 604 status = "disabled"; 605 }; 606 607 i2c@7000c000 { 608 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; 609 reg = <0x0 0x7000c000 0x0 0x100>; 610 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 611 #address-cells = <1>; 612 #size-cells = <0>; 613 clocks = <&tegra_car TEGRA210_CLK_I2C1>; 614 clock-names = "div-clk"; 615 resets = <&tegra_car 12>; 616 reset-names = "i2c"; 617 dmas = <&apbdma 21>, <&apbdma 21>; 618 dma-names = "rx", "tx"; 619 status = "disabled"; 620 }; 621 622 i2c@7000c400 { 623 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; 624 reg = <0x0 0x7000c400 0x0 0x100>; 625 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 626 #address-cells = <1>; 627 #size-cells = <0>; 628 clocks = <&tegra_car TEGRA210_CLK_I2C2>; 629 clock-names = "div-clk"; 630 resets = <&tegra_car 54>; 631 reset-names = "i2c"; 632 dmas = <&apbdma 22>, <&apbdma 22>; 633 dma-names = "rx", "tx"; 634 status = "disabled"; 635 }; 636 637 i2c@7000c500 { 638 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; 639 reg = <0x0 0x7000c500 0x0 0x100>; 640 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 641 #address-cells = <1>; 642 #size-cells = <0>; 643 clocks = <&tegra_car TEGRA210_CLK_I2C3>; 644 clock-names = "div-clk"; 645 resets = <&tegra_car 67>; 646 reset-names = "i2c"; 647 dmas = <&apbdma 23>, <&apbdma 23>; 648 dma-names = "rx", "tx"; 649 status = "disabled"; 650 }; 651 652 i2c@7000c700 { 653 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; 654 reg = <0x0 0x7000c700 0x0 0x100>; 655 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 656 #address-cells = <1>; 657 #size-cells = <0>; 658 clocks = <&tegra_car TEGRA210_CLK_I2C4>; 659 clock-names = "div-clk"; 660 resets = <&tegra_car 103>; 661 reset-names = "i2c"; 662 dmas = <&apbdma 26>, <&apbdma 26>; 663 dma-names = "rx", "tx"; 664 pinctrl-0 = <&state_dpaux1_i2c>; 665 pinctrl-1 = <&state_dpaux1_off>; 666 pinctrl-names = "default", "idle"; 667 status = "disabled"; 668 }; 669 670 i2c@7000d000 { 671 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; 672 reg = <0x0 0x7000d000 0x0 0x100>; 673 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 674 #address-cells = <1>; 675 #size-cells = <0>; 676 clocks = <&tegra_car TEGRA210_CLK_I2C5>; 677 clock-names = "div-clk"; 678 resets = <&tegra_car 47>; 679 reset-names = "i2c"; 680 dmas = <&apbdma 24>, <&apbdma 24>; 681 dma-names = "rx", "tx"; 682 status = "disabled"; 683 }; 684 685 i2c@7000d100 { 686 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; 687 reg = <0x0 0x7000d100 0x0 0x100>; 688 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 689 #address-cells = <1>; 690 #size-cells = <0>; 691 clocks = <&tegra_car TEGRA210_CLK_I2C6>; 692 clock-names = "div-clk"; 693 resets = <&tegra_car 166>; 694 reset-names = "i2c"; 695 dmas = <&apbdma 30>, <&apbdma 30>; 696 dma-names = "rx", "tx"; 697 pinctrl-0 = <&state_dpaux_i2c>; 698 pinctrl-1 = <&state_dpaux_off>; 699 pinctrl-names = "default", "idle"; 700 status = "disabled"; 701 }; 702 703 spi@7000d400 { 704 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 705 reg = <0x0 0x7000d400 0x0 0x200>; 706 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 707 #address-cells = <1>; 708 #size-cells = <0>; 709 clocks = <&tegra_car TEGRA210_CLK_SBC1>; 710 clock-names = "spi"; 711 resets = <&tegra_car 41>; 712 reset-names = "spi"; 713 dmas = <&apbdma 15>, <&apbdma 15>; 714 dma-names = "rx", "tx"; 715 status = "disabled"; 716 }; 717 718 spi@7000d600 { 719 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 720 reg = <0x0 0x7000d600 0x0 0x200>; 721 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 722 #address-cells = <1>; 723 #size-cells = <0>; 724 clocks = <&tegra_car TEGRA210_CLK_SBC2>; 725 clock-names = "spi"; 726 resets = <&tegra_car 44>; 727 reset-names = "spi"; 728 dmas = <&apbdma 16>, <&apbdma 16>; 729 dma-names = "rx", "tx"; 730 status = "disabled"; 731 }; 732 733 spi@7000d800 { 734 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 735 reg = <0x0 0x7000d800 0x0 0x200>; 736 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 737 #address-cells = <1>; 738 #size-cells = <0>; 739 clocks = <&tegra_car TEGRA210_CLK_SBC3>; 740 clock-names = "spi"; 741 resets = <&tegra_car 46>; 742 reset-names = "spi"; 743 dmas = <&apbdma 17>, <&apbdma 17>; 744 dma-names = "rx", "tx"; 745 status = "disabled"; 746 }; 747 748 spi@7000da00 { 749 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 750 reg = <0x0 0x7000da00 0x0 0x200>; 751 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 752 #address-cells = <1>; 753 #size-cells = <0>; 754 clocks = <&tegra_car TEGRA210_CLK_SBC4>; 755 clock-names = "spi"; 756 resets = <&tegra_car 68>; 757 reset-names = "spi"; 758 dmas = <&apbdma 18>, <&apbdma 18>; 759 dma-names = "rx", "tx"; 760 status = "disabled"; 761 }; 762 763 rtc@7000e000 { 764 compatible = "nvidia,tegra210-rtc", "nvidia,tegra20-rtc"; 765 reg = <0x0 0x7000e000 0x0 0x100>; 766 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 767 clocks = <&tegra_car TEGRA210_CLK_RTC>; 768 clock-names = "rtc"; 769 }; 770 771 pmc: pmc@7000e400 { 772 compatible = "nvidia,tegra210-pmc"; 773 reg = <0x0 0x7000e400 0x0 0x400>; 774 clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>; 775 clock-names = "pclk", "clk32k_in"; 776 777 powergates { 778 pd_audio: aud { 779 clocks = <&tegra_car TEGRA210_CLK_APE>, 780 <&tegra_car TEGRA210_CLK_APB2APE>; 781 resets = <&tegra_car 198>; 782 #power-domain-cells = <0>; 783 }; 784 785 pd_sor: sor { 786 clocks = <&tegra_car TEGRA210_CLK_SOR0>, 787 <&tegra_car TEGRA210_CLK_SOR1>, 788 <&tegra_car TEGRA210_CLK_CSI>, 789 <&tegra_car TEGRA210_CLK_DSIA>, 790 <&tegra_car TEGRA210_CLK_DSIB>, 791 <&tegra_car TEGRA210_CLK_DPAUX>, 792 <&tegra_car TEGRA210_CLK_DPAUX1>, 793 <&tegra_car TEGRA210_CLK_MIPI_CAL>; 794 resets = <&tegra_car TEGRA210_CLK_SOR0>, 795 <&tegra_car TEGRA210_CLK_SOR1>, 796 <&tegra_car TEGRA210_CLK_CSI>, 797 <&tegra_car TEGRA210_CLK_DSIA>, 798 <&tegra_car TEGRA210_CLK_DSIB>, 799 <&tegra_car TEGRA210_CLK_DPAUX>, 800 <&tegra_car TEGRA210_CLK_DPAUX1>, 801 <&tegra_car TEGRA210_CLK_MIPI_CAL>; 802 #power-domain-cells = <0>; 803 }; 804 805 pd_xusbss: xusba { 806 clocks = <&tegra_car TEGRA210_CLK_XUSB_SS>; 807 resets = <&tegra_car TEGRA210_CLK_XUSB_SS>; 808 #power-domain-cells = <0>; 809 }; 810 811 pd_xusbdev: xusbb { 812 clocks = <&tegra_car TEGRA210_CLK_XUSB_DEV>; 813 resets = <&tegra_car 95>; 814 #power-domain-cells = <0>; 815 }; 816 817 pd_xusbhost: xusbc { 818 clocks = <&tegra_car TEGRA210_CLK_XUSB_HOST>; 819 resets = <&tegra_car TEGRA210_CLK_XUSB_HOST>; 820 #power-domain-cells = <0>; 821 }; 822 823 pd_vic: vic { 824 clocks = <&tegra_car TEGRA210_CLK_VIC03>; 825 clock-names = "vic"; 826 resets = <&tegra_car 178>; 827 reset-names = "vic"; 828 #power-domain-cells = <0>; 829 }; 830 }; 831 832 sdmmc1_3v3: sdmmc1-3v3 { 833 pins = "sdmmc1"; 834 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 835 }; 836 837 sdmmc1_1v8: sdmmc1-1v8 { 838 pins = "sdmmc1"; 839 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 840 }; 841 842 sdmmc3_3v3: sdmmc3-3v3 { 843 pins = "sdmmc3"; 844 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 845 }; 846 847 sdmmc3_1v8: sdmmc3-1v8 { 848 pins = "sdmmc3"; 849 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 850 }; 851 }; 852 853 fuse@7000f800 { 854 compatible = "nvidia,tegra210-efuse"; 855 reg = <0x0 0x7000f800 0x0 0x400>; 856 clocks = <&tegra_car TEGRA210_CLK_FUSE>; 857 clock-names = "fuse"; 858 resets = <&tegra_car 39>; 859 reset-names = "fuse"; 860 }; 861 862 mc: memory-controller@70019000 { 863 compatible = "nvidia,tegra210-mc"; 864 reg = <0x0 0x70019000 0x0 0x1000>; 865 clocks = <&tegra_car TEGRA210_CLK_MC>; 866 clock-names = "mc"; 867 868 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 869 870 #iommu-cells = <1>; 871 }; 872 873 sata@70020000 { 874 compatible = "nvidia,tegra210-ahci"; 875 reg = <0x0 0x70027000 0x0 0x2000>, /* AHCI */ 876 <0x0 0x70020000 0x0 0x7000>, /* SATA */ 877 <0x0 0x70001100 0x0 0x1000>; /* SATA AUX */ 878 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 879 clocks = <&tegra_car TEGRA210_CLK_SATA>, 880 <&tegra_car TEGRA210_CLK_SATA_OOB>; 881 clock-names = "sata", "sata-oob"; 882 resets = <&tegra_car 124>, 883 <&tegra_car 123>, 884 <&tegra_car 129>; 885 reset-names = "sata", "sata-oob", "sata-cold"; 886 status = "disabled"; 887 }; 888 889 hda@70030000 { 890 compatible = "nvidia,tegra210-hda", "nvidia,tegra30-hda"; 891 reg = <0x0 0x70030000 0x0 0x10000>; 892 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 893 clocks = <&tegra_car TEGRA210_CLK_HDA>, 894 <&tegra_car TEGRA210_CLK_HDA2HDMI>, 895 <&tegra_car TEGRA210_CLK_HDA2CODEC_2X>; 896 clock-names = "hda", "hda2hdmi", "hda2codec_2x"; 897 resets = <&tegra_car 125>, /* hda */ 898 <&tegra_car 128>, /* hda2hdmi */ 899 <&tegra_car 111>; /* hda2codec_2x */ 900 reset-names = "hda", "hda2hdmi", "hda2codec_2x"; 901 status = "disabled"; 902 }; 903 904 usb@70090000 { 905 compatible = "nvidia,tegra210-xusb"; 906 reg = <0x0 0x70090000 0x0 0x8000>, 907 <0x0 0x70098000 0x0 0x1000>, 908 <0x0 0x70099000 0x0 0x1000>; 909 reg-names = "hcd", "fpci", "ipfs"; 910 911 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 912 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 913 914 clocks = <&tegra_car TEGRA210_CLK_XUSB_HOST>, 915 <&tegra_car TEGRA210_CLK_XUSB_HOST_SRC>, 916 <&tegra_car TEGRA210_CLK_XUSB_FALCON_SRC>, 917 <&tegra_car TEGRA210_CLK_XUSB_SS>, 918 <&tegra_car TEGRA210_CLK_XUSB_SS_DIV2>, 919 <&tegra_car TEGRA210_CLK_XUSB_SS_SRC>, 920 <&tegra_car TEGRA210_CLK_XUSB_HS_SRC>, 921 <&tegra_car TEGRA210_CLK_XUSB_FS_SRC>, 922 <&tegra_car TEGRA210_CLK_PLL_U_480M>, 923 <&tegra_car TEGRA210_CLK_CLK_M>, 924 <&tegra_car TEGRA210_CLK_PLL_E>; 925 clock-names = "xusb_host", "xusb_host_src", 926 "xusb_falcon_src", "xusb_ss", 927 "xusb_ss_div2", "xusb_ss_src", 928 "xusb_hs_src", "xusb_fs_src", 929 "pll_u_480m", "clk_m", "pll_e"; 930 resets = <&tegra_car 89>, <&tegra_car 156>, 931 <&tegra_car 143>; 932 reset-names = "xusb_host", "xusb_ss", "xusb_src"; 933 power-domains = <&pd_xusbhost>, <&pd_xusbss>; 934 power-domain-names = "xusb_host", "xusb_ss"; 935 936 nvidia,xusb-padctl = <&padctl>; 937 938 status = "disabled"; 939 }; 940 941 padctl: padctl@7009f000 { 942 compatible = "nvidia,tegra210-xusb-padctl"; 943 reg = <0x0 0x7009f000 0x0 0x1000>; 944 resets = <&tegra_car 142>; 945 reset-names = "padctl"; 946 947 status = "disabled"; 948 949 pads { 950 usb2 { 951 clocks = <&tegra_car TEGRA210_CLK_USB2_TRK>; 952 clock-names = "trk"; 953 status = "disabled"; 954 955 lanes { 956 usb2-0 { 957 status = "disabled"; 958 #phy-cells = <0>; 959 }; 960 961 usb2-1 { 962 status = "disabled"; 963 #phy-cells = <0>; 964 }; 965 966 usb2-2 { 967 status = "disabled"; 968 #phy-cells = <0>; 969 }; 970 971 usb2-3 { 972 status = "disabled"; 973 #phy-cells = <0>; 974 }; 975 }; 976 }; 977 978 hsic { 979 clocks = <&tegra_car TEGRA210_CLK_HSIC_TRK>; 980 clock-names = "trk"; 981 status = "disabled"; 982 983 lanes { 984 hsic-0 { 985 status = "disabled"; 986 #phy-cells = <0>; 987 }; 988 989 hsic-1 { 990 status = "disabled"; 991 #phy-cells = <0>; 992 }; 993 }; 994 }; 995 996 pcie { 997 clocks = <&tegra_car TEGRA210_CLK_PLL_E>; 998 clock-names = "pll"; 999 resets = <&tegra_car 205>; 1000 reset-names = "phy"; 1001 status = "disabled"; 1002 1003 lanes { 1004 pcie-0 { 1005 status = "disabled"; 1006 #phy-cells = <0>; 1007 }; 1008 1009 pcie-1 { 1010 status = "disabled"; 1011 #phy-cells = <0>; 1012 }; 1013 1014 pcie-2 { 1015 status = "disabled"; 1016 #phy-cells = <0>; 1017 }; 1018 1019 pcie-3 { 1020 status = "disabled"; 1021 #phy-cells = <0>; 1022 }; 1023 1024 pcie-4 { 1025 status = "disabled"; 1026 #phy-cells = <0>; 1027 }; 1028 1029 pcie-5 { 1030 status = "disabled"; 1031 #phy-cells = <0>; 1032 }; 1033 1034 pcie-6 { 1035 status = "disabled"; 1036 #phy-cells = <0>; 1037 }; 1038 }; 1039 }; 1040 1041 sata { 1042 clocks = <&tegra_car TEGRA210_CLK_PLL_E>; 1043 clock-names = "pll"; 1044 resets = <&tegra_car 204>; 1045 reset-names = "phy"; 1046 status = "disabled"; 1047 1048 lanes { 1049 sata-0 { 1050 status = "disabled"; 1051 #phy-cells = <0>; 1052 }; 1053 }; 1054 }; 1055 }; 1056 1057 ports { 1058 usb2-0 { 1059 status = "disabled"; 1060 }; 1061 1062 usb2-1 { 1063 status = "disabled"; 1064 }; 1065 1066 usb2-2 { 1067 status = "disabled"; 1068 }; 1069 1070 usb2-3 { 1071 status = "disabled"; 1072 }; 1073 1074 hsic-0 { 1075 status = "disabled"; 1076 }; 1077 1078 usb3-0 { 1079 status = "disabled"; 1080 }; 1081 1082 usb3-1 { 1083 status = "disabled"; 1084 }; 1085 1086 usb3-2 { 1087 status = "disabled"; 1088 }; 1089 1090 usb3-3 { 1091 status = "disabled"; 1092 }; 1093 }; 1094 }; 1095 1096 sdhci@700b0000 { 1097 compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci"; 1098 reg = <0x0 0x700b0000 0x0 0x200>; 1099 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1100 clocks = <&tegra_car TEGRA210_CLK_SDMMC1>; 1101 clock-names = "sdhci"; 1102 resets = <&tegra_car 14>; 1103 reset-names = "sdhci"; 1104 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8", 1105 "sdmmc-3v3-drv", "sdmmc-1v8-drv"; 1106 pinctrl-0 = <&sdmmc1_3v3>; 1107 pinctrl-1 = <&sdmmc1_1v8>; 1108 pinctrl-2 = <&sdmmc1_3v3_drv>; 1109 pinctrl-3 = <&sdmmc1_1v8_drv>; 1110 nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>; 1111 nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>; 1112 nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>; 1113 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7b>; 1114 nvidia,default-tap = <0x2>; 1115 nvidia,default-trim = <0x4>; 1116 assigned-clocks = <&tegra_car TEGRA210_CLK_SDMMC4>, 1117 <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>, 1118 <&tegra_car TEGRA210_CLK_PLL_C4>; 1119 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; 1120 assigned-clock-rates = <200000000>, <1000000000>, <1000000000>; 1121 status = "disabled"; 1122 }; 1123 1124 sdhci@700b0200 { 1125 compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci"; 1126 reg = <0x0 0x700b0200 0x0 0x200>; 1127 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 1128 clocks = <&tegra_car TEGRA210_CLK_SDMMC2>; 1129 clock-names = "sdhci"; 1130 resets = <&tegra_car 9>; 1131 reset-names = "sdhci"; 1132 pinctrl-names = "sdmmc-1v8-drv"; 1133 pinctrl-0 = <&sdmmc2_1v8_drv>; 1134 nvidia,pad-autocal-pull-up-offset-1v8 = <0x05>; 1135 nvidia,pad-autocal-pull-down-offset-1v8 = <0x05>; 1136 nvidia,default-tap = <0x8>; 1137 nvidia,default-trim = <0x0>; 1138 status = "disabled"; 1139 }; 1140 1141 sdhci@700b0400 { 1142 compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci"; 1143 reg = <0x0 0x700b0400 0x0 0x200>; 1144 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 1145 clocks = <&tegra_car TEGRA210_CLK_SDMMC3>; 1146 clock-names = "sdhci"; 1147 resets = <&tegra_car 69>; 1148 reset-names = "sdhci"; 1149 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8", 1150 "sdmmc-3v3-drv", "sdmmc-1v8-drv"; 1151 pinctrl-0 = <&sdmmc3_3v3>; 1152 pinctrl-1 = <&sdmmc3_1v8>; 1153 pinctrl-2 = <&sdmmc3_3v3_drv>; 1154 pinctrl-3 = <&sdmmc3_1v8_drv>; 1155 nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>; 1156 nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>; 1157 nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>; 1158 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7b>; 1159 nvidia,default-tap = <0x3>; 1160 nvidia,default-trim = <0x3>; 1161 status = "disabled"; 1162 }; 1163 1164 sdhci@700b0600 { 1165 compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci"; 1166 reg = <0x0 0x700b0600 0x0 0x200>; 1167 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 1168 clocks = <&tegra_car TEGRA210_CLK_SDMMC4>; 1169 clock-names = "sdhci"; 1170 resets = <&tegra_car 15>; 1171 reset-names = "sdhci"; 1172 pinctrl-names = "sdmmc-3v3-drv", "sdmmc-1v8-drv"; 1173 pinctrl-0 = <&sdmmc4_1v8_drv>; 1174 pinctrl-1 = <&sdmmc4_1v8_drv>; 1175 nvidia,pad-autocal-pull-up-offset-1v8 = <0x05>; 1176 nvidia,pad-autocal-pull-down-offset-1v8 = <0x05>; 1177 nvidia,default-tap = <0x8>; 1178 nvidia,default-trim = <0x0>; 1179 assigned-clocks = <&tegra_car TEGRA210_CLK_SDMMC4>, 1180 <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; 1181 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; 1182 nvidia,dqs-trim = <40>; 1183 mmc-hs400-1_8v; 1184 status = "disabled"; 1185 }; 1186 1187 mipi: mipi@700e3000 { 1188 compatible = "nvidia,tegra210-mipi"; 1189 reg = <0x0 0x700e3000 0x0 0x100>; 1190 clocks = <&tegra_car TEGRA210_CLK_MIPI_CAL>; 1191 clock-names = "mipi-cal"; 1192 power-domains = <&pd_sor>; 1193 #nvidia,mipi-calibrate-cells = <1>; 1194 }; 1195 1196 dfll: clock@70110000 { 1197 compatible = "nvidia,tegra210-dfll"; 1198 reg = <0 0x70110000 0 0x100>, /* DFLL control */ 1199 <0 0x70110000 0 0x100>, /* I2C output control */ 1200 <0 0x70110100 0 0x100>, /* Integrated I2C controller */ 1201 <0 0x70110200 0 0x100>; /* Look-up table RAM */ 1202 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 1203 clocks = <&tegra_car TEGRA210_CLK_DFLL_SOC>, 1204 <&tegra_car TEGRA210_CLK_DFLL_REF>, 1205 <&tegra_car TEGRA210_CLK_I2C5>; 1206 clock-names = "soc", "ref", "i2c"; 1207 resets = <&tegra_car TEGRA210_RST_DFLL_DVCO>; 1208 reset-names = "dvco"; 1209 #clock-cells = <0>; 1210 clock-output-names = "dfllCPU_out"; 1211 status = "disabled"; 1212 }; 1213 1214 aconnect@702c0000 { 1215 compatible = "nvidia,tegra210-aconnect"; 1216 clocks = <&tegra_car TEGRA210_CLK_APE>, 1217 <&tegra_car TEGRA210_CLK_APB2APE>; 1218 clock-names = "ape", "apb2ape"; 1219 power-domains = <&pd_audio>; 1220 #address-cells = <1>; 1221 #size-cells = <1>; 1222 ranges = <0x702c0000 0x0 0x702c0000 0x00040000>; 1223 status = "disabled"; 1224 1225 adma: dma@702e2000 { 1226 compatible = "nvidia,tegra210-adma"; 1227 reg = <0x702e2000 0x2000>; 1228 interrupt-parent = <&agic>; 1229 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 1230 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 1231 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 1232 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 1233 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 1234 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 1235 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 1236 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 1237 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 1238 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 1239 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 1240 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 1241 <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, 1242 <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, 1243 <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, 1244 <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 1245 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 1246 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 1247 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 1248 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 1249 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 1250 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 1251 #dma-cells = <1>; 1252 clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>; 1253 clock-names = "d_audio"; 1254 status = "disabled"; 1255 }; 1256 1257 agic: agic@702f9000 { 1258 compatible = "nvidia,tegra210-agic"; 1259 #interrupt-cells = <3>; 1260 interrupt-controller; 1261 reg = <0x702f9000 0x2000>, 1262 <0x702fa000 0x2000>; 1263 interrupts = <GIC_SPI 102 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 1264 clocks = <&tegra_car TEGRA210_CLK_APE>; 1265 clock-names = "clk"; 1266 status = "disabled"; 1267 }; 1268 }; 1269 1270 spi@70410000 { 1271 compatible = "nvidia,tegra210-qspi"; 1272 reg = <0x0 0x70410000 0x0 0x1000>; 1273 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 1274 #address-cells = <1>; 1275 #size-cells = <0>; 1276 clocks = <&tegra_car TEGRA210_CLK_QSPI>; 1277 clock-names = "qspi"; 1278 resets = <&tegra_car 211>; 1279 reset-names = "qspi"; 1280 dmas = <&apbdma 5>, <&apbdma 5>; 1281 dma-names = "rx", "tx"; 1282 status = "disabled"; 1283 }; 1284 1285 usb@7d000000 { 1286 compatible = "nvidia,tegra210-ehci", "nvidia,tegra30-ehci", "usb-ehci"; 1287 reg = <0x0 0x7d000000 0x0 0x4000>; 1288 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 1289 phy_type = "utmi"; 1290 clocks = <&tegra_car TEGRA210_CLK_USBD>; 1291 clock-names = "usb"; 1292 resets = <&tegra_car 22>; 1293 reset-names = "usb"; 1294 nvidia,phy = <&phy1>; 1295 status = "disabled"; 1296 }; 1297 1298 phy1: usb-phy@7d000000 { 1299 compatible = "nvidia,tegra210-usb-phy", "nvidia,tegra30-usb-phy"; 1300 reg = <0x0 0x7d000000 0x0 0x4000>, 1301 <0x0 0x7d000000 0x0 0x4000>; 1302 phy_type = "utmi"; 1303 clocks = <&tegra_car TEGRA210_CLK_USBD>, 1304 <&tegra_car TEGRA210_CLK_PLL_U>, 1305 <&tegra_car TEGRA210_CLK_USBD>; 1306 clock-names = "reg", "pll_u", "utmi-pads"; 1307 resets = <&tegra_car 22>, <&tegra_car 22>; 1308 reset-names = "usb", "utmi-pads"; 1309 nvidia,hssync-start-delay = <0>; 1310 nvidia,idle-wait-delay = <17>; 1311 nvidia,elastic-limit = <16>; 1312 nvidia,term-range-adj = <6>; 1313 nvidia,xcvr-setup = <9>; 1314 nvidia,xcvr-lsfslew = <0>; 1315 nvidia,xcvr-lsrslew = <3>; 1316 nvidia,hssquelch-level = <2>; 1317 nvidia,hsdiscon-level = <5>; 1318 nvidia,xcvr-hsslew = <12>; 1319 nvidia,has-utmi-pad-registers; 1320 status = "disabled"; 1321 }; 1322 1323 usb@7d004000 { 1324 compatible = "nvidia,tegra210-ehci", "nvidia,tegra30-ehci", "usb-ehci"; 1325 reg = <0x0 0x7d004000 0x0 0x4000>; 1326 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 1327 phy_type = "utmi"; 1328 clocks = <&tegra_car TEGRA210_CLK_USB2>; 1329 clock-names = "usb"; 1330 resets = <&tegra_car 58>; 1331 reset-names = "usb"; 1332 nvidia,phy = <&phy2>; 1333 status = "disabled"; 1334 }; 1335 1336 phy2: usb-phy@7d004000 { 1337 compatible = "nvidia,tegra210-usb-phy", "nvidia,tegra30-usb-phy"; 1338 reg = <0x0 0x7d004000 0x0 0x4000>, 1339 <0x0 0x7d000000 0x0 0x4000>; 1340 phy_type = "utmi"; 1341 clocks = <&tegra_car TEGRA210_CLK_USB2>, 1342 <&tegra_car TEGRA210_CLK_PLL_U>, 1343 <&tegra_car TEGRA210_CLK_USBD>; 1344 clock-names = "reg", "pll_u", "utmi-pads"; 1345 resets = <&tegra_car 58>, <&tegra_car 22>; 1346 reset-names = "usb", "utmi-pads"; 1347 nvidia,hssync-start-delay = <0>; 1348 nvidia,idle-wait-delay = <17>; 1349 nvidia,elastic-limit = <16>; 1350 nvidia,term-range-adj = <6>; 1351 nvidia,xcvr-setup = <9>; 1352 nvidia,xcvr-lsfslew = <0>; 1353 nvidia,xcvr-lsrslew = <3>; 1354 nvidia,hssquelch-level = <2>; 1355 nvidia,hsdiscon-level = <5>; 1356 nvidia,xcvr-hsslew = <12>; 1357 status = "disabled"; 1358 }; 1359 1360 cpus { 1361 #address-cells = <1>; 1362 #size-cells = <0>; 1363 1364 cpu@0 { 1365 device_type = "cpu"; 1366 compatible = "arm,cortex-a57"; 1367 reg = <0>; 1368 clocks = <&tegra_car TEGRA210_CLK_CCLK_G>, 1369 <&tegra_car TEGRA210_CLK_PLL_X>, 1370 <&tegra_car TEGRA210_CLK_PLL_P_OUT4>, 1371 <&dfll>; 1372 clock-names = "cpu_g", "pll_x", "pll_p", "dfll"; 1373 clock-latency = <300000>; 1374 cpu-idle-states = <&CPU_SLEEP>; 1375 }; 1376 1377 cpu@1 { 1378 device_type = "cpu"; 1379 compatible = "arm,cortex-a57"; 1380 reg = <1>; 1381 cpu-idle-states = <&CPU_SLEEP>; 1382 }; 1383 1384 cpu@2 { 1385 device_type = "cpu"; 1386 compatible = "arm,cortex-a57"; 1387 reg = <2>; 1388 cpu-idle-states = <&CPU_SLEEP>; 1389 }; 1390 1391 cpu@3 { 1392 device_type = "cpu"; 1393 compatible = "arm,cortex-a57"; 1394 reg = <3>; 1395 cpu-idle-states = <&CPU_SLEEP>; 1396 }; 1397 1398 idle-states { 1399 entry-method = "psci"; 1400 1401 CPU_SLEEP: cpu-sleep { 1402 compatible = "arm,idle-state"; 1403 arm,psci-suspend-param = <0x40000007>; 1404 entry-latency-us = <100>; 1405 exit-latency-us = <30>; 1406 min-residency-us = <1000>; 1407 wakeup-latency-us = <130>; 1408 idle-state-name = "cpu-sleep"; 1409 status = "disabled"; 1410 }; 1411 }; 1412 }; 1413 1414 timer { 1415 compatible = "arm,armv8-timer"; 1416 interrupts = <GIC_PPI 13 1417 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1418 <GIC_PPI 14 1419 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1420 <GIC_PPI 11 1421 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1422 <GIC_PPI 10 1423 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 1424 interrupt-parent = <&gic>; 1425 }; 1426 1427 soctherm: thermal-sensor@700e2000 { 1428 compatible = "nvidia,tegra210-soctherm"; 1429 reg = <0x0 0x700e2000 0x0 0x600 /* SOC_THERM reg_base */ 1430 0x0 0x60006000 0x0 0x400>; /* CAR reg_base */ 1431 reg-names = "soctherm-reg", "car-reg"; 1432 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 1433 clocks = <&tegra_car TEGRA210_CLK_TSENSOR>, 1434 <&tegra_car TEGRA210_CLK_SOC_THERM>; 1435 clock-names = "tsensor", "soctherm"; 1436 resets = <&tegra_car 78>; 1437 reset-names = "soctherm"; 1438 #thermal-sensor-cells = <1>; 1439 1440 throttle-cfgs { 1441 throttle_heavy: heavy { 1442 nvidia,priority = <100>; 1443 nvidia,cpu-throt-percent = <85>; 1444 1445 #cooling-cells = <2>; 1446 }; 1447 }; 1448 }; 1449 1450 thermal-zones { 1451 cpu { 1452 polling-delay-passive = <1000>; 1453 polling-delay = <0>; 1454 1455 thermal-sensors = 1456 <&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>; 1457 1458 trips { 1459 cpu-shutdown-trip { 1460 temperature = <102500>; 1461 hysteresis = <0>; 1462 type = "critical"; 1463 }; 1464 1465 cpu_throttle_trip: throttle-trip { 1466 temperature = <98500>; 1467 hysteresis = <1000>; 1468 type = "hot"; 1469 }; 1470 }; 1471 1472 cooling-maps { 1473 map0 { 1474 trip = <&cpu_throttle_trip>; 1475 cooling-device = <&throttle_heavy 1 1>; 1476 }; 1477 }; 1478 }; 1479 mem { 1480 polling-delay-passive = <0>; 1481 polling-delay = <0>; 1482 1483 thermal-sensors = 1484 <&soctherm TEGRA124_SOCTHERM_SENSOR_MEM>; 1485 1486 trips { 1487 mem-shutdown-trip { 1488 temperature = <103000>; 1489 hysteresis = <0>; 1490 type = "critical"; 1491 }; 1492 }; 1493 1494 cooling-maps { 1495 /* 1496 * There are currently no cooling maps, 1497 * because there are no cooling devices. 1498 */ 1499 }; 1500 }; 1501 gpu { 1502 polling-delay-passive = <1000>; 1503 polling-delay = <0>; 1504 1505 thermal-sensors = 1506 <&soctherm TEGRA124_SOCTHERM_SENSOR_GPU>; 1507 1508 trips { 1509 gpu-shutdown-trip { 1510 temperature = <103000>; 1511 hysteresis = <0>; 1512 type = "critical"; 1513 }; 1514 1515 gpu_throttle_trip: throttle-trip { 1516 temperature = <100000>; 1517 hysteresis = <1000>; 1518 type = "hot"; 1519 }; 1520 }; 1521 1522 cooling-maps { 1523 map0 { 1524 trip = <&gpu_throttle_trip>; 1525 cooling-device = <&throttle_heavy 1 1>; 1526 }; 1527 }; 1528 }; 1529 pllx { 1530 polling-delay-passive = <0>; 1531 polling-delay = <0>; 1532 1533 thermal-sensors = 1534 <&soctherm TEGRA124_SOCTHERM_SENSOR_PLLX>; 1535 1536 trips { 1537 pllx-shutdown-trip { 1538 temperature = <103000>; 1539 hysteresis = <0>; 1540 type = "critical"; 1541 }; 1542 }; 1543 1544 cooling-maps { 1545 /* 1546 * There are currently no cooling maps, 1547 * because there are no cooling devices. 1548 */ 1549 }; 1550 }; 1551 }; 1552}; 1553