1// SPDX-License-Identifier: GPL-2.0 2#include <dt-bindings/clock/tegra210-car.h> 3#include <dt-bindings/gpio/tegra-gpio.h> 4#include <dt-bindings/memory/tegra210-mc.h> 5#include <dt-bindings/pinctrl/pinctrl-tegra.h> 6#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 7#include <dt-bindings/reset/tegra210-car.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/thermal/tegra124-soctherm.h> 10#include <dt-bindings/soc/tegra-pmc.h> 11 12/ { 13 compatible = "nvidia,tegra210"; 14 interrupt-parent = <&lic>; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 18 pcie@1003000 { 19 compatible = "nvidia,tegra210-pcie"; 20 device_type = "pci"; 21 reg = <0x0 0x01003000 0x0 0x00000800 /* PADS registers */ 22 0x0 0x01003800 0x0 0x00000800 /* AFI registers */ 23 0x0 0x02000000 0x0 0x10000000>; /* configuration space */ 24 reg-names = "pads", "afi", "cs"; 25 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 26 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 27 interrupt-names = "intr", "msi"; 28 29 #interrupt-cells = <1>; 30 interrupt-map-mask = <0 0 0 0>; 31 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 32 33 bus-range = <0x00 0xff>; 34 #address-cells = <3>; 35 #size-cells = <2>; 36 37 ranges = <0x82000000 0 0x01000000 0x0 0x01000000 0 0x00001000 /* port 0 configuration space */ 38 0x82000000 0 0x01001000 0x0 0x01001000 0 0x00001000 /* port 1 configuration space */ 39 0x81000000 0 0x0 0x0 0x12000000 0 0x00010000 /* downstream I/O (64 KiB) */ 40 0x82000000 0 0x13000000 0x0 0x13000000 0 0x0d000000 /* non-prefetchable memory (208 MiB) */ 41 0xc2000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */ 42 43 clocks = <&tegra_car TEGRA210_CLK_PCIE>, 44 <&tegra_car TEGRA210_CLK_AFI>, 45 <&tegra_car TEGRA210_CLK_PLL_E>, 46 <&tegra_car TEGRA210_CLK_CML0>; 47 clock-names = "pex", "afi", "pll_e", "cml"; 48 resets = <&tegra_car 70>, 49 <&tegra_car 72>, 50 <&tegra_car 74>; 51 reset-names = "pex", "afi", "pcie_x"; 52 53 pinctrl-names = "default", "idle"; 54 pinctrl-0 = <&pex_dpd_disable>; 55 pinctrl-1 = <&pex_dpd_enable>; 56 57 status = "disabled"; 58 59 pci@1,0 { 60 device_type = "pci"; 61 assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>; 62 reg = <0x000800 0 0 0 0>; 63 bus-range = <0x00 0xff>; 64 status = "disabled"; 65 66 #address-cells = <3>; 67 #size-cells = <2>; 68 ranges; 69 70 nvidia,num-lanes = <4>; 71 }; 72 73 pci@2,0 { 74 device_type = "pci"; 75 assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>; 76 reg = <0x001000 0 0 0 0>; 77 bus-range = <0x00 0xff>; 78 status = "disabled"; 79 80 #address-cells = <3>; 81 #size-cells = <2>; 82 ranges; 83 84 nvidia,num-lanes = <1>; 85 }; 86 }; 87 88 host1x@50000000 { 89 compatible = "nvidia,tegra210-host1x", "simple-bus"; 90 reg = <0x0 0x50000000 0x0 0x00034000>; 91 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */ 92 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */ 93 clocks = <&tegra_car TEGRA210_CLK_HOST1X>; 94 clock-names = "host1x"; 95 resets = <&tegra_car 28>; 96 reset-names = "host1x"; 97 98 #address-cells = <2>; 99 #size-cells = <2>; 100 101 ranges = <0x0 0x54000000 0x0 0x54000000 0x0 0x01000000>; 102 103 iommus = <&mc TEGRA_SWGROUP_HC>; 104 105 dpaux1: dpaux@54040000 { 106 compatible = "nvidia,tegra210-dpaux"; 107 reg = <0x0 0x54040000 0x0 0x00040000>; 108 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 109 clocks = <&tegra_car TEGRA210_CLK_DPAUX1>, 110 <&tegra_car TEGRA210_CLK_PLL_DP>; 111 clock-names = "dpaux", "parent"; 112 resets = <&tegra_car 207>; 113 reset-names = "dpaux"; 114 power-domains = <&pd_sor>; 115 status = "disabled"; 116 117 state_dpaux1_aux: pinmux-aux { 118 groups = "dpaux-io"; 119 function = "aux"; 120 }; 121 122 state_dpaux1_i2c: pinmux-i2c { 123 groups = "dpaux-io"; 124 function = "i2c"; 125 }; 126 127 state_dpaux1_off: pinmux-off { 128 groups = "dpaux-io"; 129 function = "off"; 130 }; 131 132 i2c-bus { 133 #address-cells = <1>; 134 #size-cells = <0>; 135 }; 136 }; 137 138 vi@54080000 { 139 compatible = "nvidia,tegra210-vi"; 140 reg = <0x0 0x54080000 0x0 0x00040000>; 141 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 142 status = "disabled"; 143 }; 144 145 tsec@54100000 { 146 compatible = "nvidia,tegra210-tsec"; 147 reg = <0x0 0x54100000 0x0 0x00040000>; 148 }; 149 150 dc@54200000 { 151 compatible = "nvidia,tegra210-dc"; 152 reg = <0x0 0x54200000 0x0 0x00040000>; 153 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 154 clocks = <&tegra_car TEGRA210_CLK_DISP1>, 155 <&tegra_car TEGRA210_CLK_PLL_P>; 156 clock-names = "dc", "parent"; 157 resets = <&tegra_car 27>; 158 reset-names = "dc"; 159 160 iommus = <&mc TEGRA_SWGROUP_DC>; 161 162 nvidia,head = <0>; 163 }; 164 165 dc@54240000 { 166 compatible = "nvidia,tegra210-dc"; 167 reg = <0x0 0x54240000 0x0 0x00040000>; 168 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 169 clocks = <&tegra_car TEGRA210_CLK_DISP2>, 170 <&tegra_car TEGRA210_CLK_PLL_P>; 171 clock-names = "dc", "parent"; 172 resets = <&tegra_car 26>; 173 reset-names = "dc"; 174 175 iommus = <&mc TEGRA_SWGROUP_DCB>; 176 177 nvidia,head = <1>; 178 }; 179 180 dsi@54300000 { 181 compatible = "nvidia,tegra210-dsi"; 182 reg = <0x0 0x54300000 0x0 0x00040000>; 183 clocks = <&tegra_car TEGRA210_CLK_DSIA>, 184 <&tegra_car TEGRA210_CLK_DSIALP>, 185 <&tegra_car TEGRA210_CLK_PLL_D_OUT0>; 186 clock-names = "dsi", "lp", "parent"; 187 resets = <&tegra_car 48>; 188 reset-names = "dsi"; 189 power-domains = <&pd_sor>; 190 nvidia,mipi-calibrate = <&mipi 0x0c0>; /* DSIA & DSIB pads */ 191 192 status = "disabled"; 193 194 #address-cells = <1>; 195 #size-cells = <0>; 196 }; 197 198 vic@54340000 { 199 compatible = "nvidia,tegra210-vic"; 200 reg = <0x0 0x54340000 0x0 0x00040000>; 201 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 202 clocks = <&tegra_car TEGRA210_CLK_VIC03>; 203 clock-names = "vic"; 204 resets = <&tegra_car 178>; 205 reset-names = "vic"; 206 207 iommus = <&mc TEGRA_SWGROUP_VIC>; 208 power-domains = <&pd_vic>; 209 }; 210 211 nvjpg@54380000 { 212 compatible = "nvidia,tegra210-nvjpg"; 213 reg = <0x0 0x54380000 0x0 0x00040000>; 214 status = "disabled"; 215 }; 216 217 dsi@54400000 { 218 compatible = "nvidia,tegra210-dsi"; 219 reg = <0x0 0x54400000 0x0 0x00040000>; 220 clocks = <&tegra_car TEGRA210_CLK_DSIB>, 221 <&tegra_car TEGRA210_CLK_DSIBLP>, 222 <&tegra_car TEGRA210_CLK_PLL_D_OUT0>; 223 clock-names = "dsi", "lp", "parent"; 224 resets = <&tegra_car 82>; 225 reset-names = "dsi"; 226 power-domains = <&pd_sor>; 227 nvidia,mipi-calibrate = <&mipi 0x300>; /* DSIC & DSID pads */ 228 229 status = "disabled"; 230 231 #address-cells = <1>; 232 #size-cells = <0>; 233 }; 234 235 nvdec@54480000 { 236 compatible = "nvidia,tegra210-nvdec"; 237 reg = <0x0 0x54480000 0x0 0x00040000>; 238 status = "disabled"; 239 }; 240 241 nvenc@544c0000 { 242 compatible = "nvidia,tegra210-nvenc"; 243 reg = <0x0 0x544c0000 0x0 0x00040000>; 244 status = "disabled"; 245 }; 246 247 tsec@54500000 { 248 compatible = "nvidia,tegra210-tsec"; 249 reg = <0x0 0x54500000 0x0 0x00040000>; 250 status = "disabled"; 251 }; 252 253 sor@54540000 { 254 compatible = "nvidia,tegra210-sor"; 255 reg = <0x0 0x54540000 0x0 0x00040000>; 256 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 257 clocks = <&tegra_car TEGRA210_CLK_SOR0>, 258 <&tegra_car TEGRA210_CLK_SOR0_OUT>, 259 <&tegra_car TEGRA210_CLK_PLL_D_OUT0>, 260 <&tegra_car TEGRA210_CLK_PLL_DP>, 261 <&tegra_car TEGRA210_CLK_SOR_SAFE>; 262 clock-names = "sor", "out", "parent", "dp", "safe"; 263 resets = <&tegra_car 182>; 264 reset-names = "sor"; 265 pinctrl-0 = <&state_dpaux_aux>; 266 pinctrl-1 = <&state_dpaux_i2c>; 267 pinctrl-2 = <&state_dpaux_off>; 268 pinctrl-names = "aux", "i2c", "off"; 269 power-domains = <&pd_sor>; 270 status = "disabled"; 271 }; 272 273 sor@54580000 { 274 compatible = "nvidia,tegra210-sor1"; 275 reg = <0x0 0x54580000 0x0 0x00040000>; 276 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 277 clocks = <&tegra_car TEGRA210_CLK_SOR1>, 278 <&tegra_car TEGRA210_CLK_SOR1_OUT>, 279 <&tegra_car TEGRA210_CLK_PLL_D2_OUT0>, 280 <&tegra_car TEGRA210_CLK_PLL_DP>, 281 <&tegra_car TEGRA210_CLK_SOR_SAFE>; 282 clock-names = "sor", "out", "parent", "dp", "safe"; 283 resets = <&tegra_car 183>; 284 reset-names = "sor"; 285 pinctrl-0 = <&state_dpaux1_aux>; 286 pinctrl-1 = <&state_dpaux1_i2c>; 287 pinctrl-2 = <&state_dpaux1_off>; 288 pinctrl-names = "aux", "i2c", "off"; 289 power-domains = <&pd_sor>; 290 status = "disabled"; 291 }; 292 293 dpaux: dpaux@545c0000 { 294 compatible = "nvidia,tegra124-dpaux"; 295 reg = <0x0 0x545c0000 0x0 0x00040000>; 296 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 297 clocks = <&tegra_car TEGRA210_CLK_DPAUX>, 298 <&tegra_car TEGRA210_CLK_PLL_DP>; 299 clock-names = "dpaux", "parent"; 300 resets = <&tegra_car 181>; 301 reset-names = "dpaux"; 302 power-domains = <&pd_sor>; 303 status = "disabled"; 304 305 state_dpaux_aux: pinmux-aux { 306 groups = "dpaux-io"; 307 function = "aux"; 308 }; 309 310 state_dpaux_i2c: pinmux-i2c { 311 groups = "dpaux-io"; 312 function = "i2c"; 313 }; 314 315 state_dpaux_off: pinmux-off { 316 groups = "dpaux-io"; 317 function = "off"; 318 }; 319 320 i2c-bus { 321 #address-cells = <1>; 322 #size-cells = <0>; 323 }; 324 }; 325 326 isp@54600000 { 327 compatible = "nvidia,tegra210-isp"; 328 reg = <0x0 0x54600000 0x0 0x00040000>; 329 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 330 status = "disabled"; 331 }; 332 333 isp@54680000 { 334 compatible = "nvidia,tegra210-isp"; 335 reg = <0x0 0x54680000 0x0 0x00040000>; 336 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 337 status = "disabled"; 338 }; 339 340 i2c@546c0000 { 341 compatible = "nvidia,tegra210-i2c-vi"; 342 reg = <0x0 0x546c0000 0x0 0x00040000>; 343 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 344 status = "disabled"; 345 }; 346 }; 347 348 gic: interrupt-controller@50041000 { 349 compatible = "arm,gic-400"; 350 #interrupt-cells = <3>; 351 interrupt-controller; 352 reg = <0x0 0x50041000 0x0 0x1000>, 353 <0x0 0x50042000 0x0 0x2000>, 354 <0x0 0x50044000 0x0 0x2000>, 355 <0x0 0x50046000 0x0 0x2000>; 356 interrupts = <GIC_PPI 9 357 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 358 interrupt-parent = <&gic>; 359 }; 360 361 gpu@57000000 { 362 compatible = "nvidia,gm20b"; 363 reg = <0x0 0x57000000 0x0 0x01000000>, 364 <0x0 0x58000000 0x0 0x01000000>; 365 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 366 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 367 interrupt-names = "stall", "nonstall"; 368 clocks = <&tegra_car TEGRA210_CLK_GPU>, 369 <&tegra_car TEGRA210_CLK_PLL_P_OUT5>, 370 <&tegra_car TEGRA210_CLK_PLL_G_REF>; 371 clock-names = "gpu", "pwr", "ref"; 372 resets = <&tegra_car 184>; 373 reset-names = "gpu"; 374 375 iommus = <&mc TEGRA_SWGROUP_GPU>; 376 377 status = "disabled"; 378 }; 379 380 lic: interrupt-controller@60004000 { 381 compatible = "nvidia,tegra210-ictlr"; 382 reg = <0x0 0x60004000 0x0 0x40>, /* primary controller */ 383 <0x0 0x60004100 0x0 0x40>, /* secondary controller */ 384 <0x0 0x60004200 0x0 0x40>, /* tertiary controller */ 385 <0x0 0x60004300 0x0 0x40>, /* quaternary controller */ 386 <0x0 0x60004400 0x0 0x40>, /* quinary controller */ 387 <0x0 0x60004500 0x0 0x40>; /* senary controller */ 388 interrupt-controller; 389 #interrupt-cells = <3>; 390 interrupt-parent = <&gic>; 391 }; 392 393 timer@60005000 { 394 compatible = "nvidia,tegra210-timer"; 395 reg = <0x0 0x60005000 0x0 0x400>; 396 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, 397 <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 398 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 399 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 400 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 401 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 402 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 403 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 404 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 405 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 406 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 407 <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>, 408 <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>, 409 <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; 410 clocks = <&tegra_car TEGRA210_CLK_TIMER>; 411 clock-names = "timer"; 412 }; 413 414 tegra_car: clock@60006000 { 415 compatible = "nvidia,tegra210-car"; 416 reg = <0x0 0x60006000 0x0 0x1000>; 417 #clock-cells = <1>; 418 #reset-cells = <1>; 419 }; 420 421 flow-controller@60007000 { 422 compatible = "nvidia,tegra210-flowctrl"; 423 reg = <0x0 0x60007000 0x0 0x1000>; 424 }; 425 426 gpio: gpio@6000d000 { 427 compatible = "nvidia,tegra210-gpio", "nvidia,tegra30-gpio"; 428 reg = <0x0 0x6000d000 0x0 0x1000>; 429 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 430 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 431 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 432 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 433 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 434 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 435 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 436 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 437 #gpio-cells = <2>; 438 gpio-controller; 439 #interrupt-cells = <2>; 440 interrupt-controller; 441 }; 442 443 apbdma: dma@60020000 { 444 compatible = "nvidia,tegra210-apbdma", "nvidia,tegra148-apbdma"; 445 reg = <0x0 0x60020000 0x0 0x1400>; 446 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 447 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 448 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 449 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 450 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 451 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 452 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 453 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 454 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 455 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 456 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 457 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 458 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 459 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 460 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 461 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 462 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 463 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 464 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 465 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 466 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 467 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 468 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 469 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 470 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 471 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 472 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 473 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 474 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 475 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 476 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 477 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 478 clocks = <&tegra_car TEGRA210_CLK_APBDMA>; 479 clock-names = "dma"; 480 resets = <&tegra_car 34>; 481 reset-names = "dma"; 482 #dma-cells = <1>; 483 }; 484 485 apbmisc@70000800 { 486 compatible = "nvidia,tegra210-apbmisc", "nvidia,tegra20-apbmisc"; 487 reg = <0x0 0x70000800 0x0 0x64>, /* Chip revision */ 488 <0x0 0x70000008 0x0 0x04>; /* Strapping options */ 489 }; 490 491 pinmux: pinmux@700008d4 { 492 compatible = "nvidia,tegra210-pinmux"; 493 reg = <0x0 0x700008d4 0x0 0x29c>, /* Pad control registers */ 494 <0x0 0x70003000 0x0 0x294>; /* Mux registers */ 495 sdmmc1_3v3_drv: sdmmc1-3v3-drv { 496 sdmmc1 { 497 nvidia,pins = "drive_sdmmc1"; 498 nvidia,pull-down-strength = <0x8>; 499 nvidia,pull-up-strength = <0x8>; 500 }; 501 }; 502 sdmmc1_1v8_drv: sdmmc1-1v8-drv { 503 sdmmc1 { 504 nvidia,pins = "drive_sdmmc1"; 505 nvidia,pull-down-strength = <0x4>; 506 nvidia,pull-up-strength = <0x3>; 507 }; 508 }; 509 sdmmc2_1v8_drv: sdmmc2-1v8-drv { 510 sdmmc2 { 511 nvidia,pins = "drive_sdmmc2"; 512 nvidia,pull-down-strength = <0x10>; 513 nvidia,pull-up-strength = <0x10>; 514 }; 515 }; 516 sdmmc3_3v3_drv: sdmmc3-3v3-drv { 517 sdmmc3 { 518 nvidia,pins = "drive_sdmmc3"; 519 nvidia,pull-down-strength = <0x8>; 520 nvidia,pull-up-strength = <0x8>; 521 }; 522 }; 523 sdmmc3_1v8_drv: sdmmc3-1v8-drv { 524 sdmmc3 { 525 nvidia,pins = "drive_sdmmc3"; 526 nvidia,pull-down-strength = <0x4>; 527 nvidia,pull-up-strength = <0x3>; 528 }; 529 }; 530 sdmmc4_1v8_drv: sdmmc4-1v8-drv { 531 sdmmc4 { 532 nvidia,pins = "drive_sdmmc4"; 533 nvidia,pull-down-strength = <0x10>; 534 nvidia,pull-up-strength = <0x10>; 535 }; 536 }; 537 }; 538 539 /* 540 * There are two serial driver i.e. 8250 based simple serial 541 * driver and APB DMA based serial driver for higher baudrate 542 * and performance. To enable the 8250 based driver, the compatible 543 * is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable 544 * the APB DMA based serial driver, the compatible is 545 * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart". 546 */ 547 uarta: serial@70006000 { 548 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; 549 reg = <0x0 0x70006000 0x0 0x40>; 550 reg-shift = <2>; 551 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 552 clocks = <&tegra_car TEGRA210_CLK_UARTA>; 553 clock-names = "serial"; 554 resets = <&tegra_car 6>; 555 reset-names = "serial"; 556 dmas = <&apbdma 8>, <&apbdma 8>; 557 dma-names = "rx", "tx"; 558 status = "disabled"; 559 }; 560 561 uartb: serial@70006040 { 562 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; 563 reg = <0x0 0x70006040 0x0 0x40>; 564 reg-shift = <2>; 565 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 566 clocks = <&tegra_car TEGRA210_CLK_UARTB>; 567 clock-names = "serial"; 568 resets = <&tegra_car 7>; 569 reset-names = "serial"; 570 dmas = <&apbdma 9>, <&apbdma 9>; 571 dma-names = "rx", "tx"; 572 status = "disabled"; 573 }; 574 575 uartc: serial@70006200 { 576 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; 577 reg = <0x0 0x70006200 0x0 0x40>; 578 reg-shift = <2>; 579 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 580 clocks = <&tegra_car TEGRA210_CLK_UARTC>; 581 clock-names = "serial"; 582 resets = <&tegra_car 55>; 583 reset-names = "serial"; 584 dmas = <&apbdma 10>, <&apbdma 10>; 585 dma-names = "rx", "tx"; 586 status = "disabled"; 587 }; 588 589 uartd: serial@70006300 { 590 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; 591 reg = <0x0 0x70006300 0x0 0x40>; 592 reg-shift = <2>; 593 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 594 clocks = <&tegra_car TEGRA210_CLK_UARTD>; 595 clock-names = "serial"; 596 resets = <&tegra_car 65>; 597 reset-names = "serial"; 598 dmas = <&apbdma 19>, <&apbdma 19>; 599 dma-names = "rx", "tx"; 600 status = "disabled"; 601 }; 602 603 pwm: pwm@7000a000 { 604 compatible = "nvidia,tegra210-pwm", "nvidia,tegra20-pwm"; 605 reg = <0x0 0x7000a000 0x0 0x100>; 606 #pwm-cells = <2>; 607 clocks = <&tegra_car TEGRA210_CLK_PWM>; 608 clock-names = "pwm"; 609 resets = <&tegra_car 17>; 610 reset-names = "pwm"; 611 status = "disabled"; 612 }; 613 614 i2c@7000c000 { 615 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; 616 reg = <0x0 0x7000c000 0x0 0x100>; 617 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 618 #address-cells = <1>; 619 #size-cells = <0>; 620 clocks = <&tegra_car TEGRA210_CLK_I2C1>; 621 clock-names = "div-clk"; 622 resets = <&tegra_car 12>; 623 reset-names = "i2c"; 624 dmas = <&apbdma 21>, <&apbdma 21>; 625 dma-names = "rx", "tx"; 626 status = "disabled"; 627 }; 628 629 i2c@7000c400 { 630 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; 631 reg = <0x0 0x7000c400 0x0 0x100>; 632 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 633 #address-cells = <1>; 634 #size-cells = <0>; 635 clocks = <&tegra_car TEGRA210_CLK_I2C2>; 636 clock-names = "div-clk"; 637 resets = <&tegra_car 54>; 638 reset-names = "i2c"; 639 dmas = <&apbdma 22>, <&apbdma 22>; 640 dma-names = "rx", "tx"; 641 status = "disabled"; 642 }; 643 644 i2c@7000c500 { 645 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; 646 reg = <0x0 0x7000c500 0x0 0x100>; 647 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 648 #address-cells = <1>; 649 #size-cells = <0>; 650 clocks = <&tegra_car TEGRA210_CLK_I2C3>; 651 clock-names = "div-clk"; 652 resets = <&tegra_car 67>; 653 reset-names = "i2c"; 654 dmas = <&apbdma 23>, <&apbdma 23>; 655 dma-names = "rx", "tx"; 656 status = "disabled"; 657 }; 658 659 i2c@7000c700 { 660 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; 661 reg = <0x0 0x7000c700 0x0 0x100>; 662 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 663 #address-cells = <1>; 664 #size-cells = <0>; 665 clocks = <&tegra_car TEGRA210_CLK_I2C4>; 666 clock-names = "div-clk"; 667 resets = <&tegra_car 103>; 668 reset-names = "i2c"; 669 dmas = <&apbdma 26>, <&apbdma 26>; 670 dma-names = "rx", "tx"; 671 pinctrl-0 = <&state_dpaux1_i2c>; 672 pinctrl-1 = <&state_dpaux1_off>; 673 pinctrl-names = "default", "idle"; 674 status = "disabled"; 675 }; 676 677 i2c@7000d000 { 678 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; 679 reg = <0x0 0x7000d000 0x0 0x100>; 680 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 681 #address-cells = <1>; 682 #size-cells = <0>; 683 clocks = <&tegra_car TEGRA210_CLK_I2C5>; 684 clock-names = "div-clk"; 685 resets = <&tegra_car 47>; 686 reset-names = "i2c"; 687 dmas = <&apbdma 24>, <&apbdma 24>; 688 dma-names = "rx", "tx"; 689 status = "disabled"; 690 }; 691 692 i2c@7000d100 { 693 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; 694 reg = <0x0 0x7000d100 0x0 0x100>; 695 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 696 #address-cells = <1>; 697 #size-cells = <0>; 698 clocks = <&tegra_car TEGRA210_CLK_I2C6>; 699 clock-names = "div-clk"; 700 resets = <&tegra_car 166>; 701 reset-names = "i2c"; 702 dmas = <&apbdma 30>, <&apbdma 30>; 703 dma-names = "rx", "tx"; 704 pinctrl-0 = <&state_dpaux_i2c>; 705 pinctrl-1 = <&state_dpaux_off>; 706 pinctrl-names = "default", "idle"; 707 status = "disabled"; 708 }; 709 710 spi@7000d400 { 711 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 712 reg = <0x0 0x7000d400 0x0 0x200>; 713 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 714 #address-cells = <1>; 715 #size-cells = <0>; 716 clocks = <&tegra_car TEGRA210_CLK_SBC1>; 717 clock-names = "spi"; 718 resets = <&tegra_car 41>; 719 reset-names = "spi"; 720 dmas = <&apbdma 15>, <&apbdma 15>; 721 dma-names = "rx", "tx"; 722 status = "disabled"; 723 }; 724 725 spi@7000d600 { 726 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 727 reg = <0x0 0x7000d600 0x0 0x200>; 728 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 729 #address-cells = <1>; 730 #size-cells = <0>; 731 clocks = <&tegra_car TEGRA210_CLK_SBC2>; 732 clock-names = "spi"; 733 resets = <&tegra_car 44>; 734 reset-names = "spi"; 735 dmas = <&apbdma 16>, <&apbdma 16>; 736 dma-names = "rx", "tx"; 737 status = "disabled"; 738 }; 739 740 spi@7000d800 { 741 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 742 reg = <0x0 0x7000d800 0x0 0x200>; 743 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 744 #address-cells = <1>; 745 #size-cells = <0>; 746 clocks = <&tegra_car TEGRA210_CLK_SBC3>; 747 clock-names = "spi"; 748 resets = <&tegra_car 46>; 749 reset-names = "spi"; 750 dmas = <&apbdma 17>, <&apbdma 17>; 751 dma-names = "rx", "tx"; 752 status = "disabled"; 753 }; 754 755 spi@7000da00 { 756 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 757 reg = <0x0 0x7000da00 0x0 0x200>; 758 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 759 #address-cells = <1>; 760 #size-cells = <0>; 761 clocks = <&tegra_car TEGRA210_CLK_SBC4>; 762 clock-names = "spi"; 763 resets = <&tegra_car 68>; 764 reset-names = "spi"; 765 dmas = <&apbdma 18>, <&apbdma 18>; 766 dma-names = "rx", "tx"; 767 status = "disabled"; 768 }; 769 770 rtc@7000e000 { 771 compatible = "nvidia,tegra210-rtc", "nvidia,tegra20-rtc"; 772 reg = <0x0 0x7000e000 0x0 0x100>; 773 interrupts = <16 IRQ_TYPE_LEVEL_HIGH>; 774 interrupt-parent = <&tegra_pmc>; 775 clocks = <&tegra_car TEGRA210_CLK_RTC>; 776 clock-names = "rtc"; 777 }; 778 779 tegra_pmc: pmc@7000e400 { 780 compatible = "nvidia,tegra210-pmc"; 781 reg = <0x0 0x7000e400 0x0 0x400>; 782 clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>; 783 clock-names = "pclk", "clk32k_in"; 784 #clock-cells = <1>; 785 #interrupt-cells = <2>; 786 interrupt-controller; 787 788 powergates { 789 pd_audio: aud { 790 clocks = <&tegra_car TEGRA210_CLK_APE>, 791 <&tegra_car TEGRA210_CLK_APB2APE>; 792 resets = <&tegra_car 198>; 793 #power-domain-cells = <0>; 794 }; 795 796 pd_sor: sor { 797 clocks = <&tegra_car TEGRA210_CLK_SOR0>, 798 <&tegra_car TEGRA210_CLK_SOR1>, 799 <&tegra_car TEGRA210_CLK_CSI>, 800 <&tegra_car TEGRA210_CLK_DSIA>, 801 <&tegra_car TEGRA210_CLK_DSIB>, 802 <&tegra_car TEGRA210_CLK_DPAUX>, 803 <&tegra_car TEGRA210_CLK_DPAUX1>, 804 <&tegra_car TEGRA210_CLK_MIPI_CAL>; 805 resets = <&tegra_car TEGRA210_CLK_SOR0>, 806 <&tegra_car TEGRA210_CLK_SOR1>, 807 <&tegra_car TEGRA210_CLK_CSI>, 808 <&tegra_car TEGRA210_CLK_DSIA>, 809 <&tegra_car TEGRA210_CLK_DSIB>, 810 <&tegra_car TEGRA210_CLK_DPAUX>, 811 <&tegra_car TEGRA210_CLK_DPAUX1>, 812 <&tegra_car TEGRA210_CLK_MIPI_CAL>; 813 #power-domain-cells = <0>; 814 }; 815 816 pd_xusbss: xusba { 817 clocks = <&tegra_car TEGRA210_CLK_XUSB_SS>; 818 resets = <&tegra_car TEGRA210_CLK_XUSB_SS>; 819 #power-domain-cells = <0>; 820 }; 821 822 pd_xusbdev: xusbb { 823 clocks = <&tegra_car TEGRA210_CLK_XUSB_DEV>; 824 resets = <&tegra_car 95>; 825 #power-domain-cells = <0>; 826 }; 827 828 pd_xusbhost: xusbc { 829 clocks = <&tegra_car TEGRA210_CLK_XUSB_HOST>; 830 resets = <&tegra_car TEGRA210_CLK_XUSB_HOST>; 831 #power-domain-cells = <0>; 832 }; 833 834 pd_vic: vic { 835 clocks = <&tegra_car TEGRA210_CLK_VIC03>; 836 clock-names = "vic"; 837 resets = <&tegra_car 178>; 838 reset-names = "vic"; 839 #power-domain-cells = <0>; 840 }; 841 }; 842 843 sdmmc1_3v3: sdmmc1-3v3 { 844 pins = "sdmmc1"; 845 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 846 }; 847 848 sdmmc1_1v8: sdmmc1-1v8 { 849 pins = "sdmmc1"; 850 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 851 }; 852 853 sdmmc3_3v3: sdmmc3-3v3 { 854 pins = "sdmmc3"; 855 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 856 }; 857 858 sdmmc3_1v8: sdmmc3-1v8 { 859 pins = "sdmmc3"; 860 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 861 }; 862 863 pex_dpd_disable: pex_en { 864 pex-dpd-disable { 865 pins = "pex-bias", "pex-clk1", "pex-clk2"; 866 low-power-disable; 867 }; 868 }; 869 870 pex_dpd_enable: pex_dis { 871 pex-dpd-enable { 872 pins = "pex-bias", "pex-clk1", "pex-clk2"; 873 low-power-enable; 874 }; 875 }; 876 }; 877 878 fuse@7000f800 { 879 compatible = "nvidia,tegra210-efuse"; 880 reg = <0x0 0x7000f800 0x0 0x400>; 881 clocks = <&tegra_car TEGRA210_CLK_FUSE>; 882 clock-names = "fuse"; 883 resets = <&tegra_car 39>; 884 reset-names = "fuse"; 885 }; 886 887 mc: memory-controller@70019000 { 888 compatible = "nvidia,tegra210-mc"; 889 reg = <0x0 0x70019000 0x0 0x1000>; 890 clocks = <&tegra_car TEGRA210_CLK_MC>; 891 clock-names = "mc"; 892 893 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 894 895 #iommu-cells = <1>; 896 }; 897 898 external-memory-controller@7001b000 { 899 compatible = "nvidia,tegra210-emc"; 900 reg = <0x0 0x7001b000 0x0 0x1000>, 901 <0x0 0x7001e000 0x0 0x1000>, 902 <0x0 0x7001f000 0x0 0x1000>; 903 clocks = <&tegra_car TEGRA210_CLK_EMC>; 904 clock-names = "emc"; 905 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 906 nvidia,memory-controller = <&mc>; 907 }; 908 909 sata@70020000 { 910 compatible = "nvidia,tegra210-ahci"; 911 reg = <0x0 0x70027000 0x0 0x2000>, /* AHCI */ 912 <0x0 0x70020000 0x0 0x7000>, /* SATA */ 913 <0x0 0x70001100 0x0 0x1000>; /* SATA AUX */ 914 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 915 clocks = <&tegra_car TEGRA210_CLK_SATA>, 916 <&tegra_car TEGRA210_CLK_SATA_OOB>; 917 clock-names = "sata", "sata-oob"; 918 resets = <&tegra_car 124>, 919 <&tegra_car 123>, 920 <&tegra_car 129>; 921 reset-names = "sata", "sata-oob", "sata-cold"; 922 status = "disabled"; 923 }; 924 925 hda@70030000 { 926 compatible = "nvidia,tegra210-hda", "nvidia,tegra30-hda"; 927 reg = <0x0 0x70030000 0x0 0x10000>; 928 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 929 clocks = <&tegra_car TEGRA210_CLK_HDA>, 930 <&tegra_car TEGRA210_CLK_HDA2HDMI>, 931 <&tegra_car TEGRA210_CLK_HDA2CODEC_2X>; 932 clock-names = "hda", "hda2hdmi", "hda2codec_2x"; 933 resets = <&tegra_car 125>, /* hda */ 934 <&tegra_car 128>, /* hda2hdmi */ 935 <&tegra_car 111>; /* hda2codec_2x */ 936 reset-names = "hda", "hda2hdmi", "hda2codec_2x"; 937 status = "disabled"; 938 }; 939 940 usb@70090000 { 941 compatible = "nvidia,tegra210-xusb"; 942 reg = <0x0 0x70090000 0x0 0x8000>, 943 <0x0 0x70098000 0x0 0x1000>, 944 <0x0 0x70099000 0x0 0x1000>; 945 reg-names = "hcd", "fpci", "ipfs"; 946 947 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 948 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 949 950 clocks = <&tegra_car TEGRA210_CLK_XUSB_HOST>, 951 <&tegra_car TEGRA210_CLK_XUSB_HOST_SRC>, 952 <&tegra_car TEGRA210_CLK_XUSB_FALCON_SRC>, 953 <&tegra_car TEGRA210_CLK_XUSB_SS>, 954 <&tegra_car TEGRA210_CLK_XUSB_SS_DIV2>, 955 <&tegra_car TEGRA210_CLK_XUSB_SS_SRC>, 956 <&tegra_car TEGRA210_CLK_XUSB_HS_SRC>, 957 <&tegra_car TEGRA210_CLK_XUSB_FS_SRC>, 958 <&tegra_car TEGRA210_CLK_PLL_U_480M>, 959 <&tegra_car TEGRA210_CLK_CLK_M>, 960 <&tegra_car TEGRA210_CLK_PLL_E>; 961 clock-names = "xusb_host", "xusb_host_src", 962 "xusb_falcon_src", "xusb_ss", 963 "xusb_ss_div2", "xusb_ss_src", 964 "xusb_hs_src", "xusb_fs_src", 965 "pll_u_480m", "clk_m", "pll_e"; 966 resets = <&tegra_car 89>, <&tegra_car 156>, 967 <&tegra_car 143>; 968 reset-names = "xusb_host", "xusb_ss", "xusb_src"; 969 power-domains = <&pd_xusbhost>, <&pd_xusbss>; 970 power-domain-names = "xusb_host", "xusb_ss"; 971 972 nvidia,xusb-padctl = <&padctl>; 973 974 status = "disabled"; 975 }; 976 977 padctl: padctl@7009f000 { 978 compatible = "nvidia,tegra210-xusb-padctl"; 979 reg = <0x0 0x7009f000 0x0 0x1000>; 980 resets = <&tegra_car 142>; 981 reset-names = "padctl"; 982 983 status = "disabled"; 984 985 pads { 986 usb2 { 987 clocks = <&tegra_car TEGRA210_CLK_USB2_TRK>; 988 clock-names = "trk"; 989 status = "disabled"; 990 991 lanes { 992 usb2-0 { 993 status = "disabled"; 994 #phy-cells = <0>; 995 }; 996 997 usb2-1 { 998 status = "disabled"; 999 #phy-cells = <0>; 1000 }; 1001 1002 usb2-2 { 1003 status = "disabled"; 1004 #phy-cells = <0>; 1005 }; 1006 1007 usb2-3 { 1008 status = "disabled"; 1009 #phy-cells = <0>; 1010 }; 1011 }; 1012 }; 1013 1014 hsic { 1015 clocks = <&tegra_car TEGRA210_CLK_HSIC_TRK>; 1016 clock-names = "trk"; 1017 status = "disabled"; 1018 1019 lanes { 1020 hsic-0 { 1021 status = "disabled"; 1022 #phy-cells = <0>; 1023 }; 1024 1025 hsic-1 { 1026 status = "disabled"; 1027 #phy-cells = <0>; 1028 }; 1029 }; 1030 }; 1031 1032 pcie { 1033 clocks = <&tegra_car TEGRA210_CLK_PLL_E>; 1034 clock-names = "pll"; 1035 resets = <&tegra_car 205>; 1036 reset-names = "phy"; 1037 status = "disabled"; 1038 1039 lanes { 1040 pcie-0 { 1041 status = "disabled"; 1042 #phy-cells = <0>; 1043 }; 1044 1045 pcie-1 { 1046 status = "disabled"; 1047 #phy-cells = <0>; 1048 }; 1049 1050 pcie-2 { 1051 status = "disabled"; 1052 #phy-cells = <0>; 1053 }; 1054 1055 pcie-3 { 1056 status = "disabled"; 1057 #phy-cells = <0>; 1058 }; 1059 1060 pcie-4 { 1061 status = "disabled"; 1062 #phy-cells = <0>; 1063 }; 1064 1065 pcie-5 { 1066 status = "disabled"; 1067 #phy-cells = <0>; 1068 }; 1069 1070 pcie-6 { 1071 status = "disabled"; 1072 #phy-cells = <0>; 1073 }; 1074 }; 1075 }; 1076 1077 sata { 1078 clocks = <&tegra_car TEGRA210_CLK_PLL_E>; 1079 clock-names = "pll"; 1080 resets = <&tegra_car 204>; 1081 reset-names = "phy"; 1082 status = "disabled"; 1083 1084 lanes { 1085 sata-0 { 1086 status = "disabled"; 1087 #phy-cells = <0>; 1088 }; 1089 }; 1090 }; 1091 }; 1092 1093 ports { 1094 usb2-0 { 1095 status = "disabled"; 1096 }; 1097 1098 usb2-1 { 1099 status = "disabled"; 1100 }; 1101 1102 usb2-2 { 1103 status = "disabled"; 1104 }; 1105 1106 usb2-3 { 1107 status = "disabled"; 1108 }; 1109 1110 hsic-0 { 1111 status = "disabled"; 1112 }; 1113 1114 usb3-0 { 1115 status = "disabled"; 1116 }; 1117 1118 usb3-1 { 1119 status = "disabled"; 1120 }; 1121 1122 usb3-2 { 1123 status = "disabled"; 1124 }; 1125 1126 usb3-3 { 1127 status = "disabled"; 1128 }; 1129 }; 1130 }; 1131 1132 sdhci@700b0000 { 1133 compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci"; 1134 reg = <0x0 0x700b0000 0x0 0x200>; 1135 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1136 clocks = <&tegra_car TEGRA210_CLK_SDMMC1>; 1137 clock-names = "sdhci"; 1138 resets = <&tegra_car 14>; 1139 reset-names = "sdhci"; 1140 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8", 1141 "sdmmc-3v3-drv", "sdmmc-1v8-drv"; 1142 pinctrl-0 = <&sdmmc1_3v3>; 1143 pinctrl-1 = <&sdmmc1_1v8>; 1144 pinctrl-2 = <&sdmmc1_3v3_drv>; 1145 pinctrl-3 = <&sdmmc1_1v8_drv>; 1146 nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>; 1147 nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>; 1148 nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>; 1149 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7b>; 1150 nvidia,default-tap = <0x2>; 1151 nvidia,default-trim = <0x4>; 1152 assigned-clocks = <&tegra_car TEGRA210_CLK_SDMMC4>, 1153 <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>, 1154 <&tegra_car TEGRA210_CLK_PLL_C4>; 1155 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; 1156 assigned-clock-rates = <200000000>, <1000000000>, <1000000000>; 1157 status = "disabled"; 1158 }; 1159 1160 sdhci@700b0200 { 1161 compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci"; 1162 reg = <0x0 0x700b0200 0x0 0x200>; 1163 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 1164 clocks = <&tegra_car TEGRA210_CLK_SDMMC2>; 1165 clock-names = "sdhci"; 1166 resets = <&tegra_car 9>; 1167 reset-names = "sdhci"; 1168 pinctrl-names = "sdmmc-1v8-drv"; 1169 pinctrl-0 = <&sdmmc2_1v8_drv>; 1170 nvidia,pad-autocal-pull-up-offset-1v8 = <0x05>; 1171 nvidia,pad-autocal-pull-down-offset-1v8 = <0x05>; 1172 nvidia,default-tap = <0x8>; 1173 nvidia,default-trim = <0x0>; 1174 status = "disabled"; 1175 }; 1176 1177 sdhci@700b0400 { 1178 compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci"; 1179 reg = <0x0 0x700b0400 0x0 0x200>; 1180 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 1181 clocks = <&tegra_car TEGRA210_CLK_SDMMC3>; 1182 clock-names = "sdhci"; 1183 resets = <&tegra_car 69>; 1184 reset-names = "sdhci"; 1185 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8", 1186 "sdmmc-3v3-drv", "sdmmc-1v8-drv"; 1187 pinctrl-0 = <&sdmmc3_3v3>; 1188 pinctrl-1 = <&sdmmc3_1v8>; 1189 pinctrl-2 = <&sdmmc3_3v3_drv>; 1190 pinctrl-3 = <&sdmmc3_1v8_drv>; 1191 nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>; 1192 nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>; 1193 nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>; 1194 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7b>; 1195 nvidia,default-tap = <0x3>; 1196 nvidia,default-trim = <0x3>; 1197 status = "disabled"; 1198 }; 1199 1200 sdhci@700b0600 { 1201 compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci"; 1202 reg = <0x0 0x700b0600 0x0 0x200>; 1203 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 1204 clocks = <&tegra_car TEGRA210_CLK_SDMMC4>; 1205 clock-names = "sdhci"; 1206 resets = <&tegra_car 15>; 1207 reset-names = "sdhci"; 1208 pinctrl-names = "sdmmc-3v3-drv", "sdmmc-1v8-drv"; 1209 pinctrl-0 = <&sdmmc4_1v8_drv>; 1210 pinctrl-1 = <&sdmmc4_1v8_drv>; 1211 nvidia,pad-autocal-pull-up-offset-1v8 = <0x05>; 1212 nvidia,pad-autocal-pull-down-offset-1v8 = <0x05>; 1213 nvidia,default-tap = <0x8>; 1214 nvidia,default-trim = <0x0>; 1215 assigned-clocks = <&tegra_car TEGRA210_CLK_SDMMC4>, 1216 <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; 1217 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; 1218 nvidia,dqs-trim = <40>; 1219 mmc-hs400-1_8v; 1220 status = "disabled"; 1221 }; 1222 1223 usb@700d0000 { 1224 compatible = "nvidia,tegra210-xudc"; 1225 reg = <0x0 0x700d0000 0x0 0x8000>, 1226 <0x0 0x700d8000 0x0 0x1000>, 1227 <0x0 0x700d9000 0x0 0x1000>; 1228 reg-names = "base", "fpci", "ipfs"; 1229 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 1230 clocks = <&tegra_car TEGRA210_CLK_XUSB_DEV>, 1231 <&tegra_car TEGRA210_CLK_XUSB_SS>, 1232 <&tegra_car TEGRA210_CLK_XUSB_SSP_SRC>, 1233 <&tegra_car TEGRA210_CLK_XUSB_FS_SRC>, 1234 <&tegra_car TEGRA210_CLK_XUSB_HS_SRC>; 1235 clock-names = "dev", "ss", "ss_src", "fs_src", "hs_src"; 1236 power-domains = <&pd_xusbdev>, <&pd_xusbss>; 1237 power-domain-names = "dev", "ss"; 1238 nvidia,xusb-padctl = <&padctl>; 1239 status = "disabled"; 1240 }; 1241 1242 mipi: mipi@700e3000 { 1243 compatible = "nvidia,tegra210-mipi"; 1244 reg = <0x0 0x700e3000 0x0 0x100>; 1245 clocks = <&tegra_car TEGRA210_CLK_MIPI_CAL>; 1246 clock-names = "mipi-cal"; 1247 power-domains = <&pd_sor>; 1248 #nvidia,mipi-calibrate-cells = <1>; 1249 }; 1250 1251 dfll: clock@70110000 { 1252 compatible = "nvidia,tegra210-dfll"; 1253 reg = <0 0x70110000 0 0x100>, /* DFLL control */ 1254 <0 0x70110000 0 0x100>, /* I2C output control */ 1255 <0 0x70110100 0 0x100>, /* Integrated I2C controller */ 1256 <0 0x70110200 0 0x100>; /* Look-up table RAM */ 1257 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 1258 clocks = <&tegra_car TEGRA210_CLK_DFLL_SOC>, 1259 <&tegra_car TEGRA210_CLK_DFLL_REF>, 1260 <&tegra_car TEGRA210_CLK_I2C5>; 1261 clock-names = "soc", "ref", "i2c"; 1262 resets = <&tegra_car TEGRA210_RST_DFLL_DVCO>; 1263 reset-names = "dvco"; 1264 #clock-cells = <0>; 1265 clock-output-names = "dfllCPU_out"; 1266 status = "disabled"; 1267 }; 1268 1269 aconnect@702c0000 { 1270 compatible = "nvidia,tegra210-aconnect"; 1271 clocks = <&tegra_car TEGRA210_CLK_APE>, 1272 <&tegra_car TEGRA210_CLK_APB2APE>; 1273 clock-names = "ape", "apb2ape"; 1274 power-domains = <&pd_audio>; 1275 #address-cells = <1>; 1276 #size-cells = <1>; 1277 ranges = <0x702c0000 0x0 0x702c0000 0x00040000>; 1278 status = "disabled"; 1279 1280 adma: dma@702e2000 { 1281 compatible = "nvidia,tegra210-adma"; 1282 reg = <0x702e2000 0x2000>; 1283 interrupt-parent = <&agic>; 1284 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 1285 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 1286 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 1287 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 1288 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 1289 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 1290 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 1291 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 1292 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 1293 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 1294 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 1295 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 1296 <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, 1297 <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, 1298 <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, 1299 <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 1300 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 1301 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 1302 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 1303 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 1304 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 1305 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 1306 #dma-cells = <1>; 1307 clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>; 1308 clock-names = "d_audio"; 1309 status = "disabled"; 1310 }; 1311 1312 agic: agic@702f9000 { 1313 compatible = "nvidia,tegra210-agic"; 1314 #interrupt-cells = <3>; 1315 interrupt-controller; 1316 reg = <0x702f9000 0x1000>, 1317 <0x702fa000 0x2000>; 1318 interrupts = <GIC_SPI 102 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 1319 clocks = <&tegra_car TEGRA210_CLK_APE>; 1320 clock-names = "clk"; 1321 status = "disabled"; 1322 }; 1323 }; 1324 1325 spi@70410000 { 1326 compatible = "nvidia,tegra210-qspi"; 1327 reg = <0x0 0x70410000 0x0 0x1000>; 1328 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 1329 #address-cells = <1>; 1330 #size-cells = <0>; 1331 clocks = <&tegra_car TEGRA210_CLK_QSPI>; 1332 clock-names = "qspi"; 1333 resets = <&tegra_car 211>; 1334 reset-names = "qspi"; 1335 dmas = <&apbdma 5>, <&apbdma 5>; 1336 dma-names = "rx", "tx"; 1337 status = "disabled"; 1338 }; 1339 1340 usb@7d000000 { 1341 compatible = "nvidia,tegra210-ehci", "nvidia,tegra30-ehci", "usb-ehci"; 1342 reg = <0x0 0x7d000000 0x0 0x4000>; 1343 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 1344 phy_type = "utmi"; 1345 clocks = <&tegra_car TEGRA210_CLK_USBD>; 1346 clock-names = "usb"; 1347 resets = <&tegra_car 22>; 1348 reset-names = "usb"; 1349 nvidia,phy = <&phy1>; 1350 status = "disabled"; 1351 }; 1352 1353 phy1: usb-phy@7d000000 { 1354 compatible = "nvidia,tegra210-usb-phy", "nvidia,tegra30-usb-phy"; 1355 reg = <0x0 0x7d000000 0x0 0x4000>, 1356 <0x0 0x7d000000 0x0 0x4000>; 1357 phy_type = "utmi"; 1358 clocks = <&tegra_car TEGRA210_CLK_USBD>, 1359 <&tegra_car TEGRA210_CLK_PLL_U>, 1360 <&tegra_car TEGRA210_CLK_USBD>; 1361 clock-names = "reg", "pll_u", "utmi-pads"; 1362 resets = <&tegra_car 22>, <&tegra_car 22>; 1363 reset-names = "usb", "utmi-pads"; 1364 nvidia,hssync-start-delay = <0>; 1365 nvidia,idle-wait-delay = <17>; 1366 nvidia,elastic-limit = <16>; 1367 nvidia,term-range-adj = <6>; 1368 nvidia,xcvr-setup = <9>; 1369 nvidia,xcvr-lsfslew = <0>; 1370 nvidia,xcvr-lsrslew = <3>; 1371 nvidia,hssquelch-level = <2>; 1372 nvidia,hsdiscon-level = <5>; 1373 nvidia,xcvr-hsslew = <12>; 1374 nvidia,has-utmi-pad-registers; 1375 status = "disabled"; 1376 }; 1377 1378 usb@7d004000 { 1379 compatible = "nvidia,tegra210-ehci", "nvidia,tegra30-ehci", "usb-ehci"; 1380 reg = <0x0 0x7d004000 0x0 0x4000>; 1381 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 1382 phy_type = "utmi"; 1383 clocks = <&tegra_car TEGRA210_CLK_USB2>; 1384 clock-names = "usb"; 1385 resets = <&tegra_car 58>; 1386 reset-names = "usb"; 1387 nvidia,phy = <&phy2>; 1388 status = "disabled"; 1389 }; 1390 1391 phy2: usb-phy@7d004000 { 1392 compatible = "nvidia,tegra210-usb-phy", "nvidia,tegra30-usb-phy"; 1393 reg = <0x0 0x7d004000 0x0 0x4000>, 1394 <0x0 0x7d000000 0x0 0x4000>; 1395 phy_type = "utmi"; 1396 clocks = <&tegra_car TEGRA210_CLK_USB2>, 1397 <&tegra_car TEGRA210_CLK_PLL_U>, 1398 <&tegra_car TEGRA210_CLK_USBD>; 1399 clock-names = "reg", "pll_u", "utmi-pads"; 1400 resets = <&tegra_car 58>, <&tegra_car 22>; 1401 reset-names = "usb", "utmi-pads"; 1402 nvidia,hssync-start-delay = <0>; 1403 nvidia,idle-wait-delay = <17>; 1404 nvidia,elastic-limit = <16>; 1405 nvidia,term-range-adj = <6>; 1406 nvidia,xcvr-setup = <9>; 1407 nvidia,xcvr-lsfslew = <0>; 1408 nvidia,xcvr-lsrslew = <3>; 1409 nvidia,hssquelch-level = <2>; 1410 nvidia,hsdiscon-level = <5>; 1411 nvidia,xcvr-hsslew = <12>; 1412 status = "disabled"; 1413 }; 1414 1415 cpus { 1416 #address-cells = <1>; 1417 #size-cells = <0>; 1418 1419 cpu@0 { 1420 device_type = "cpu"; 1421 compatible = "arm,cortex-a57"; 1422 reg = <0>; 1423 clocks = <&tegra_car TEGRA210_CLK_CCLK_G>, 1424 <&tegra_car TEGRA210_CLK_PLL_X>, 1425 <&tegra_car TEGRA210_CLK_PLL_P_OUT4>, 1426 <&dfll>; 1427 clock-names = "cpu_g", "pll_x", "pll_p", "dfll"; 1428 clock-latency = <300000>; 1429 cpu-idle-states = <&CPU_SLEEP>; 1430 next-level-cache = <&L2>; 1431 }; 1432 1433 cpu@1 { 1434 device_type = "cpu"; 1435 compatible = "arm,cortex-a57"; 1436 reg = <1>; 1437 cpu-idle-states = <&CPU_SLEEP>; 1438 next-level-cache = <&L2>; 1439 }; 1440 1441 cpu@2 { 1442 device_type = "cpu"; 1443 compatible = "arm,cortex-a57"; 1444 reg = <2>; 1445 cpu-idle-states = <&CPU_SLEEP>; 1446 next-level-cache = <&L2>; 1447 }; 1448 1449 cpu@3 { 1450 device_type = "cpu"; 1451 compatible = "arm,cortex-a57"; 1452 reg = <3>; 1453 cpu-idle-states = <&CPU_SLEEP>; 1454 next-level-cache = <&L2>; 1455 }; 1456 1457 idle-states { 1458 entry-method = "psci"; 1459 1460 CPU_SLEEP: cpu-sleep { 1461 compatible = "arm,idle-state"; 1462 arm,psci-suspend-param = <0x40000007>; 1463 entry-latency-us = <100>; 1464 exit-latency-us = <30>; 1465 min-residency-us = <1000>; 1466 wakeup-latency-us = <130>; 1467 idle-state-name = "cpu-sleep"; 1468 status = "disabled"; 1469 }; 1470 }; 1471 1472 L2: l2-cache { 1473 compatible = "cache"; 1474 }; 1475 }; 1476 1477 pmu { 1478 compatible = "arm,armv8-pmuv3"; 1479 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 1480 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 1481 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 1482 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; 1483 interrupt-affinity = <&{/cpus/cpu@0} &{/cpus/cpu@1} 1484 &{/cpus/cpu@2} &{/cpus/cpu@3}>; 1485 }; 1486 1487 timer { 1488 compatible = "arm,armv8-timer"; 1489 interrupts = <GIC_PPI 13 1490 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1491 <GIC_PPI 14 1492 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1493 <GIC_PPI 11 1494 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1495 <GIC_PPI 10 1496 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 1497 interrupt-parent = <&gic>; 1498 arm,no-tick-in-suspend; 1499 }; 1500 1501 soctherm: thermal-sensor@700e2000 { 1502 compatible = "nvidia,tegra210-soctherm"; 1503 reg = <0x0 0x700e2000 0x0 0x600 /* SOC_THERM reg_base */ 1504 0x0 0x60006000 0x0 0x400>; /* CAR reg_base */ 1505 reg-names = "soctherm-reg", "car-reg"; 1506 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, 1507 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 1508 interrupt-names = "thermal", "edp"; 1509 clocks = <&tegra_car TEGRA210_CLK_TSENSOR>, 1510 <&tegra_car TEGRA210_CLK_SOC_THERM>; 1511 clock-names = "tsensor", "soctherm"; 1512 resets = <&tegra_car 78>; 1513 reset-names = "soctherm"; 1514 #thermal-sensor-cells = <1>; 1515 1516 throttle-cfgs { 1517 throttle_heavy: heavy { 1518 nvidia,priority = <100>; 1519 nvidia,cpu-throt-percent = <85>; 1520 1521 #cooling-cells = <2>; 1522 }; 1523 }; 1524 }; 1525 1526 thermal-zones { 1527 cpu { 1528 polling-delay-passive = <1000>; 1529 polling-delay = <0>; 1530 1531 thermal-sensors = 1532 <&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>; 1533 1534 trips { 1535 cpu-shutdown-trip { 1536 temperature = <102500>; 1537 hysteresis = <0>; 1538 type = "critical"; 1539 }; 1540 1541 cpu_throttle_trip: throttle-trip { 1542 temperature = <98500>; 1543 hysteresis = <1000>; 1544 type = "hot"; 1545 }; 1546 }; 1547 1548 cooling-maps { 1549 map0 { 1550 trip = <&cpu_throttle_trip>; 1551 cooling-device = <&throttle_heavy 1 1>; 1552 }; 1553 }; 1554 }; 1555 1556 mem { 1557 polling-delay-passive = <0>; 1558 polling-delay = <0>; 1559 1560 thermal-sensors = 1561 <&soctherm TEGRA124_SOCTHERM_SENSOR_MEM>; 1562 1563 trips { 1564 mem-shutdown-trip { 1565 temperature = <103000>; 1566 hysteresis = <0>; 1567 type = "critical"; 1568 }; 1569 }; 1570 1571 cooling-maps { 1572 /* 1573 * There are currently no cooling maps, 1574 * because there are no cooling devices. 1575 */ 1576 }; 1577 }; 1578 1579 gpu { 1580 polling-delay-passive = <1000>; 1581 polling-delay = <0>; 1582 1583 thermal-sensors = 1584 <&soctherm TEGRA124_SOCTHERM_SENSOR_GPU>; 1585 1586 trips { 1587 gpu-shutdown-trip { 1588 temperature = <103000>; 1589 hysteresis = <0>; 1590 type = "critical"; 1591 }; 1592 1593 gpu_throttle_trip: throttle-trip { 1594 temperature = <100000>; 1595 hysteresis = <1000>; 1596 type = "hot"; 1597 }; 1598 }; 1599 1600 cooling-maps { 1601 map0 { 1602 trip = <&gpu_throttle_trip>; 1603 cooling-device = <&throttle_heavy 1 1>; 1604 }; 1605 }; 1606 }; 1607 1608 pllx { 1609 polling-delay-passive = <0>; 1610 polling-delay = <0>; 1611 1612 thermal-sensors = 1613 <&soctherm TEGRA124_SOCTHERM_SENSOR_PLLX>; 1614 1615 trips { 1616 pllx-shutdown-trip { 1617 temperature = <103000>; 1618 hysteresis = <0>; 1619 type = "critical"; 1620 }; 1621 }; 1622 1623 cooling-maps { 1624 /* 1625 * There are currently no cooling maps, 1626 * because there are no cooling devices. 1627 */ 1628 }; 1629 }; 1630 }; 1631}; 1632