Revision tags: v6.6.25, v6.6.24, v6.6.23, v6.6.16, v6.6.15, v6.6.14, v6.6.13, v6.6.12, v6.6.11, v6.6.10, v6.6.9, v6.6.8, v6.6.7, v6.6.6, v6.6.5, v6.6.4, v6.6.3, v6.6.2, v6.5.11, v6.6.1, v6.5.10, v6.6, v6.5.9, v6.5.8, v6.5.7, v6.5.6, v6.5.5, v6.5.4, v6.5.3, v6.5.2, v6.1.51, v6.5.1, v6.1.50, v6.5, v6.1.49, v6.1.48, v6.1.46, v6.1.45, v6.1.44, v6.1.43, v6.1.42, v6.1.41, v6.1.40, v6.1.39, v6.1.38, v6.1.37, v6.1.36 |
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#
331085a4 |
| 27-Jun-2023 |
Dinh Nguyen <dinguyen@kernel.org> |
arm64: dts: socfpga: change the reset-name of "stmmaceth-ocp" to "ahb"
The "stmmaceth-ocp" reset line on the SoCFPGA stmmac ethernet driver is the same as the "ahb" reset on a standard stmmac ethern
arm64: dts: socfpga: change the reset-name of "stmmaceth-ocp" to "ahb"
The "stmmaceth-ocp" reset line on the SoCFPGA stmmac ethernet driver is the same as the "ahb" reset on a standard stmmac ethernet.
commit ("843f603762a5 dt-bindings: net: snps,dwmac: Add 'ahb' reset/reset-name") documented the second reset signal as 'ahb' instead of 'stmmaceth-ocp'. Change the reset-names of the SoCFPGA DWMAC driver to 'ahb'. In order not to break ABI, we will keep support in thedwmac-socfpga driver to still make use of "stmmaceth-ocp".
This also fixes the dtbs_check warning: ethernet@ff802000: reset-names:1: 'ahb' was expected
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> --- v2: update commit message to further describe the reason for the change
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Revision tags: v6.4 |
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#
c91e8f33 |
| 25-Jun-2023 |
Dinh Nguyen <dinguyen@kernel.org> |
arm64: dts: agilex/stratix10/n5x: fix dtbs_check for rstmgr
The bindings expect "altr,rst-mgr" as a fallback in the rstmgr compatible:
rstmgr@ffd11000: compatible: 'oneOf' conditional failed, one m
arm64: dts: agilex/stratix10/n5x: fix dtbs_check for rstmgr
The bindings expect "altr,rst-mgr" as a fallback in the rstmgr compatible:
rstmgr@ffd11000: compatible: 'oneOf' conditional failed, one must be fixed: ['altr,stratix10-rst-mgr'] is too short 'altr,rst-mgr' was expected
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
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#
6de298ff |
| 23-Jun-2023 |
Dinh Nguyen <dinguyen@kernel.org> |
arm64: dts: socfpga: agilex/stratix10: fix dtbs_check warnings for sram
sram@ffe00000: 'ranges' is a required property sram@ffe00000: '#size-cells' is a required property sram@ffe00000: '#address-ce
arm64: dts: socfpga: agilex/stratix10: fix dtbs_check warnings for sram
sram@ffe00000: 'ranges' is a required property sram@ffe00000: '#size-cells' is a required property sram@ffe00000: '#address-cells' is a required property
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
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Revision tags: v6.1.35, v6.1.34, v6.1.33, v6.1.32, v6.1.31, v6.1.30, v6.1.29, v6.1.28, v6.1.27, v6.1.26, v6.3, v6.1.25, v6.1.24, v6.1.23, v6.1.22, v6.1.21, v6.1.20, v6.1.19, v6.1.18, v6.1.17, v6.1.16, v6.1.15, v6.1.14, v6.1.13, v6.2, v6.1.12, v6.1.11, v6.1.10, v6.1.9 |
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#
2f8ba037 |
| 25-Jan-2023 |
Dinh Nguyen <dinguyen@kernel.org> |
arm64: dts: socfpga: change address-cells to support 64-bit addressing
Update the address-cells and size-cells to 2 in order to support 64-bit addressing.
Signed-off-by: Dinh Nguyen <dinguyen@kerne
arm64: dts: socfpga: change address-cells to support 64-bit addressing
Update the address-cells and size-cells to 2 in order to support 64-bit addressing.
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
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Revision tags: v6.1.8 |
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#
21ab7031 |
| 23-Jan-2023 |
Dinh Nguyen <dinguyen@kernel.org> |
arm64: dts: add pinctrl-single property for Stratix10/Agilex
The Stratix10/Agilex has a pin control IP that can make use of the pinctrl-single driver.
Add the pinctrl-single dts property for the St
arm64: dts: add pinctrl-single property for Stratix10/Agilex
The Stratix10/Agilex has a pin control IP that can make use of the pinctrl-single driver.
Add the pinctrl-single dts property for the Stratix10/Agilex platforms.
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> --- v2: no changes
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Revision tags: v6.1.7, v6.1.6, v6.1.5, v6.0.19, v6.0.18, v6.1.4, v6.1.3, v6.0.17, v6.1.2, v6.0.16, v6.1.1, v6.0.15, v6.0.14, v6.0.13, v6.1, v6.0.12, v6.0.11, v6.0.10, v5.15.80, v6.0.9, v5.15.79, v6.0.8, v5.15.78, v6.0.7, v5.15.77, v5.15.76, v6.0.6, v6.0.5, v5.15.75, v6.0.4, v6.0.3, v6.0.2, v5.15.74, v5.15.73, v6.0.1, v5.15.72, v6.0, v5.15.71, v5.15.70, v5.15.69 |
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#
31354121 |
| 15-Sep-2022 |
Dinh Nguyen <dinguyen@kernel.org> |
arm64: dts: socfpga: Add clk-phase-sd-hs property to the sdmmc node
The sdmmc controller's CIU(Card Interface Unit) clock's phase can be adjusted through the register in the system manager. Add the
arm64: dts: socfpga: Add clk-phase-sd-hs property to the sdmmc node
The sdmmc controller's CIU(Card Interface Unit) clock's phase can be adjusted through the register in the system manager. Add the binding "altr,sysmgr-syscon" to the SDMMC node for the driver to access the system manager. Add the "clk-phase-sd-hs" property in the SDMMC node to designate the smpsel and drvsel properties for the CIU clock.
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
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Revision tags: v5.15.68, v5.15.67, v5.15.66, v5.15.65, v5.15.64, v5.15.63, v5.15.62, v5.15.61, v5.15.60, v5.15.59, v5.19, v5.15.58, v5.15.57, v5.15.56, v5.15.55, v5.15.54, v5.15.53, v5.15.52, v5.15.51, v5.15.50, v5.15.49, v5.15.48, v5.15.47, v5.15.46, v5.15.45, v5.15.44 |
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#
a2a4ee55 |
| 30-May-2022 |
Niravkumar L Rabara <niravkumar.l.rabara@intel.com> |
arm64: dts: intel: socfpga_agilex: use defined GIC interrupt type for ECC
Use defined GIC interrupt type instead of hard-coded numbers for ECC (Error Correction Code) memory, which creates edac sysf
arm64: dts: intel: socfpga_agilex: use defined GIC interrupt type for ECC
Use defined GIC interrupt type instead of hard-coded numbers for ECC (Error Correction Code) memory, which creates edac sysfs interface.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Niravkumar L Rabara <niravkumar.l.rabara@intel.com> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
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Revision tags: v5.15.43, v5.15.42, v5.18, v5.15.41, v5.15.40, v5.15.39, v5.15.38, v5.15.37 |
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#
a93fbb00 |
| 30-Apr-2022 |
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> |
arm64: dts: stratix10/agilex: drop useless 'dma-channels/requests' properties
The pl330 DMA controller provides number of DMA channels and requests through its registers, so duplicating this informa
arm64: dts: stratix10/agilex: drop useless 'dma-channels/requests' properties
The pl330 DMA controller provides number of DMA channels and requests through its registers, so duplicating this information (with a chance of mistakes) in DTS is pointless. Additionally the DTS used always wrong property names which causes DT schema check failures - the bindings documented 'dma-channels' and 'dma-requests' properties without leading hash sign.
Reported-by: Rob Herring <robh@kernel.org> Suggested-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220430121902.59895-4-krzysztof.kozlowski@linaro.org
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Revision tags: v5.15.36, v5.15.35, v5.15.34, v5.15.33, v5.15.32, v5.15.31, v5.17, v5.15.30, v5.15.29, v5.15.28, v5.15.27, v5.15.26, v5.15.25 |
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#
4b557e17 |
| 18-Feb-2022 |
Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> |
arm64: dts: agilex/stratix10: add clock-names to USB DWC2 node
USB DWC2 requires clock-names:
arm64/boot/dts/altera/socfpga_stratix10_socdk_nand.dt.yaml: usb@ffb00000: 'clock-names' is a requ
arm64: dts: agilex/stratix10: add clock-names to USB DWC2 node
USB DWC2 requires clock-names:
arm64/boot/dts/altera/socfpga_stratix10_socdk_nand.dt.yaml: usb@ffb00000: 'clock-names' is a required property
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
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Revision tags: v5.15.24, v5.15.23, v5.15.22, v5.15.21, v5.15.20, v5.15.19, v5.15.18, v5.15.17 |
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#
325b820f |
| 25-Jan-2022 |
Dinh Nguyen <dinguyen@kernel.org> |
arm64: dts: agilex: use the compatible "intel,socfpga-agilex-hsotg"
The DWC2 USB controller on the Agilex platform does not support clock gating, so use the chip specific "intel,socfpga-agilex-hsotg
arm64: dts: agilex: use the compatible "intel,socfpga-agilex-hsotg"
The DWC2 USB controller on the Agilex platform does not support clock gating, so use the chip specific "intel,socfpga-agilex-hsotg" compatible.
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> Link: https://lore.kernel.org/r/20220125161821.1951906-3-dinguyen@kernel.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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#
e3e4ffe1 |
| 29-Jan-2022 |
Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> |
arm64: dts: agilex: align pl330 node name with dtschema
Fixes dtbs_check warnings like:
pdma@ffda0000: $nodename:0: 'pdma@ffda0000' does not match '^dma-controller(@.*)?$'
Signed-off-by: Krzyszt
arm64: dts: agilex: align pl330 node name with dtschema
Fixes dtbs_check warnings like:
pdma@ffda0000: $nodename:0: 'pdma@ffda0000' does not match '^dma-controller(@.*)?$'
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
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Revision tags: v5.4.173, v5.15.16, v5.15.15, v5.16 |
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#
268a491a |
| 06-Jan-2022 |
Dinh Nguyen <dinguyen@kernel.org> |
arm64: dts: agilex: use the compatible "intel,socfpga-agilex-hsotg"
The DWC2 USB controller on the Agilex platform does not support clock gating, so use the chip specific "intel,socfpga-agilex-hsotg
arm64: dts: agilex: use the compatible "intel,socfpga-agilex-hsotg"
The DWC2 USB controller on the Agilex platform does not support clock gating, so use the chip specific "intel,socfpga-agilex-hsotg" compatible.
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
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#
9ffc4e03 |
| 27-Dec-2021 |
Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> |
arm64: dts: agilex: align mmc node names with dtschema
The Synopsys DW MSHC bindings require node name to be 'mmc':
dwmmc0@ff808000: $nodename:0: 'dwmmc0@ff808000' does not match '^mmc(@.*)?$'
S
arm64: dts: agilex: align mmc node names with dtschema
The Synopsys DW MSHC bindings require node name to be 'mmc':
dwmmc0@ff808000: $nodename:0: 'dwmmc0@ff808000' does not match '^mmc(@.*)?$'
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
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Revision tags: v5.15.10, v5.15.9, v5.15.8, v5.15.7, v5.15.6, v5.15.5 |
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#
36de991e |
| 22-Nov-2021 |
Dinh Nguyen <dinguyen@kernel.org> |
ARM: dts: socfpga: change qspi to "intel,socfpga-qspi"
Because of commit 9cb2ff111712 ("spi: cadence-quadspi: Disable Auto-HW polling"), which does a write to the CQSPI_REG_WR_COMPLETION_CTRL regist
ARM: dts: socfpga: change qspi to "intel,socfpga-qspi"
Because of commit 9cb2ff111712 ("spi: cadence-quadspi: Disable Auto-HW polling"), which does a write to the CQSPI_REG_WR_COMPLETION_CTRL register regardless of any condition. Well, the Cadence QuadSPI controller on Intel's SoCFPGA platforms does not implement the CQSPI_REG_WR_COMPLETION_CTRL register, thus a write to this register results in a crash!
So starting with v5.16, I introduced the patch 98d948eb833 ("spi: cadence-quadspi: fix write completion support"), which adds the dts compatible "intel,socfpga-qspi" that is specific for versions that doesn't have the CQSPI_REG_WR_COMPLETION_CTRL register implemented.
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> --- v3: revert back to "intel,socfpga-qspi" v2: use both "cdns,qspi-nor" and "cdns,qspi-nor-0010"
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#
10033fa7 |
| 22-Nov-2021 |
Dinh Nguyen <dinguyen@kernel.org> |
ARM: dts: socfpga: change qspi to "intel,socfpga-qspi"
commit 36de991e93908f7ad5c2a0eac9c4ecf8b723fa4a upstream.
Because of commit 9cb2ff111712 ("spi: cadence-quadspi: Disable Auto-HW polling"), wh
ARM: dts: socfpga: change qspi to "intel,socfpga-qspi"
commit 36de991e93908f7ad5c2a0eac9c4ecf8b723fa4a upstream.
Because of commit 9cb2ff111712 ("spi: cadence-quadspi: Disable Auto-HW polling"), which does a write to the CQSPI_REG_WR_COMPLETION_CTRL register regardless of any condition. Well, the Cadence QuadSPI controller on Intel's SoCFPGA platforms does not implement the CQSPI_REG_WR_COMPLETION_CTRL register, thus a write to this register results in a crash!
So starting with v5.16, I introduced the patch 98d948eb833 ("spi: cadence-quadspi: fix write completion support"), which adds the dts compatible "intel,socfpga-qspi" that is specific for versions that doesn't have the CQSPI_REG_WR_COMPLETION_CTRL register implemented.
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> [IA: submitted for linux-5.15.y] Signed-off-by: Ian Abbott <abbotti@mev.co.uk> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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#
4744e1df |
| 06-Jan-2022 |
Dinh Nguyen <dinguyen@kernel.org> |
arm64: dts: agilex: use the compatible "intel,socfpga-agilex-hsotg"
[ Upstream commit 268a491aebc25e6dc7c618903b09ac3a2e8af530 ]
The DWC2 USB controller on the Agilex platform does not support cloc
arm64: dts: agilex: use the compatible "intel,socfpga-agilex-hsotg"
[ Upstream commit 268a491aebc25e6dc7c618903b09ac3a2e8af530 ]
The DWC2 USB controller on the Agilex platform does not support clock gating, so use the chip specific "intel,socfpga-agilex-hsotg" compatible.
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> Signed-off-by: Sasha Levin <sashal@kernel.org>
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Revision tags: v5.15.4, v5.15.3, v5.15.2, v5.15.1, v5.15, v5.14.14, v5.14.13, v5.14.12, v5.14.11, v5.14.10, v5.14.9, v5.14.8, v5.14.7, v5.14.6, v5.10.67, v5.10.66, v5.14.5, v5.14.4, v5.10.65, v5.14.3, v5.10.64, v5.14.2, v5.10.63, v5.14.1, v5.10.62, v5.14, v5.10.61, v5.10.60, v5.10.53, v5.10.52, v5.10.51, v5.10.50, v5.10.49, v5.13, v5.10.46, v5.10.43, v5.10.42, v5.10.41, v5.10.40, v5.10.39, v5.4.119, v5.10.36, v5.10.35, v5.10.34, v5.4.116, v5.10.33, v5.12, v5.10.32, v5.10.31, v5.10.30, v5.10.27, v5.10.26, v5.10.25, v5.10.24, v5.10.23, v5.10.22 |
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#
ae68efe9 |
| 08-Mar-2021 |
Krzysztof Kozlowski <krzk@kernel.org> |
arm64: dts: intel: socfpga_agilex: align node names with dtschema
Align the NAND, GIC and UART node names with dtschema to silence dtbs_check warnings like:
arch/arm64/boot/dts/intel/socfpga_ag
arm64: dts: intel: socfpga_agilex: align node names with dtschema
Align the NAND, GIC and UART node names with dtschema to silence dtbs_check warnings like:
arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dt.yaml: intc@fffc1000: $nodename:0: 'intc@fffc1000' does not match '^interrupt-controller(@[0-9a-f,]+)*$' arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dt.yaml: serial0@ffc02000: $nodename:0: 'serial0@ffc02000' does not match '^serial(@[0-9a-f,]+)*$'
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
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#
f10ffbf5 |
| 08-Mar-2021 |
Krzysztof Kozlowski <krzk@kernel.org> |
arm64: dts: intel: socfpga_agilex: use defined for GIC interrupts
Use human-readable defines for GIC interrupt type and flag, instead of hard-coding the numbers. It makes review easier. No functio
arm64: dts: intel: socfpga_agilex: use defined for GIC interrupts
Use human-readable defines for GIC interrupt type and flag, instead of hard-coding the numbers. It makes review easier. No functional change.
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
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#
9e474427 |
| 08-Mar-2021 |
Krzysztof Kozlowski <krzk@kernel.org> |
arm64: dts: intel: socfpga_agilex: move usbphy out of soc node
The usual usb-nop-xceiv USB phy node should be under root node, to fix dtc warning:
arch/arm64/boot/dts/intel/socfpga_agilex.dtsi:
arm64: dts: intel: socfpga_agilex: move usbphy out of soc node
The usual usb-nop-xceiv USB phy node should be under root node, to fix dtc warning:
arch/arm64/boot/dts/intel/socfpga_agilex.dtsi:472.21-476.5: Warning (simple_bus_reg): /soc/usbphy@0: missing or empty reg/ranges property
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
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#
cce24712 |
| 08-Mar-2021 |
Krzysztof Kozlowski <krzk@kernel.org> |
arm64: dts: intel: socfpga_agilex: remove default status=okay
New nodes are okay by default.
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
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#
9f1f6273 |
| 08-Mar-2021 |
Krzysztof Kozlowski <krzk@kernel.org> |
arm64: dts: intel: socfpga_agilex: move timer out of soc node
The ARM architected timer is part of ARM CPU design therefore by convention it should not be inside the soc node. This also fixes dtc w
arm64: dts: intel: socfpga_agilex: move timer out of soc node
The ARM architected timer is part of ARM CPU design therefore by convention it should not be inside the soc node. This also fixes dtc warning like:
arch/arm64/boot/dts/intel/socfpga_agilex.dtsi:410.9-416.5: Warning (simple_bus_reg): /soc/timer: missing or empty reg/ranges property
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
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#
d2e59308 |
| 08-Mar-2021 |
Krzysztof Kozlowski <krzk@kernel.org> |
arm64: dts: intel: socfpga_agilex: move clocks out of soc node
The clocks are usually not part of the SoC but provided on the board (external oscillators). Moving them out of soc node fixes dtc war
arm64: dts: intel: socfpga_agilex: move clocks out of soc node
The clocks are usually not part of the SoC but provided on the board (external oscillators). Moving them out of soc node fixes dtc warning:
arch/arm64/boot/dts/intel/socfpga_agilex.dtsi:111.10-137.5: Warning (simple_bus_reg): /soc/clocks: missing or empty reg/ranges property
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
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Revision tags: v5.10.21, v5.10.20, v5.10.19, v5.4.101, v5.10.18, v5.10.17, v5.11, v5.10.16, v5.10.15, v5.10.14 |
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#
b7ff3a44 |
| 04-Feb-2021 |
Dinh Nguyen <dinguyen@kernel.org> |
arm64: dts: agilex: fix phy interface bit shift for gmac1 and gmac2
The shift for the phy_intf_sel bit in the system manager for gmac1 and gmac2 should be 0.
Fixes: 2f804ba7aa9ee ("arm64: dts: agil
arm64: dts: agilex: fix phy interface bit shift for gmac1 and gmac2
The shift for the phy_intf_sel bit in the system manager for gmac1 and gmac2 should be 0.
Fixes: 2f804ba7aa9ee ("arm64: dts: agilex: Add SysMgr to Ethernet nodes") Cc: stable@vger.kernel.org Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
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#
7e00b4c8 |
| 04-Feb-2021 |
Dinh Nguyen <dinguyen@kernel.org> |
arm64: dts: agilex: fix phy interface bit shift for gmac1 and gmac2
commit b7ff3a447d100c999d9848353ef8a4046831d893 upstream.
The shift for the phy_intf_sel bit in the system manager for gmac1 and
arm64: dts: agilex: fix phy interface bit shift for gmac1 and gmac2
commit b7ff3a447d100c999d9848353ef8a4046831d893 upstream.
The shift for the phy_intf_sel bit in the system manager for gmac1 and gmac2 should be 0.
Fixes: 2f804ba7aa9ee ("arm64: dts: agilex: Add SysMgr to Ethernet nodes") Cc: stable@vger.kernel.org Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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Revision tags: v5.10, v5.8.17, v5.8.16, v5.8.15, v5.9, v5.8.14, v5.8.13, v5.8.12, v5.8.11, v5.8.10, v5.8.9, v5.8.8, v5.8.7, v5.8.6, v5.4.62 |
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6e043c65 |
| 31-Aug-2020 |
Dinh Nguyen <dinguyen@kernel.org> |
arm64: dts: stratix10/agilex: add the ptp_ref clock
Add the ptp_ref clock for the GMACs.
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
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