1// SPDX-License-Identifier:     GPL-2.0
2/*
3 * Copyright (C) 2019, Intel Corporation
4 */
5
6/dts-v1/;
7#include <dt-bindings/reset/altr,rst-mgr-s10.h>
8#include <dt-bindings/gpio/gpio.h>
9#include <dt-bindings/interrupt-controller/arm-gic.h>
10#include <dt-bindings/clock/agilex-clock.h>
11
12/ {
13	compatible = "intel,socfpga-agilex";
14	#address-cells = <2>;
15	#size-cells = <2>;
16
17	reserved-memory {
18		#address-cells = <2>;
19		#size-cells = <2>;
20		ranges;
21
22		service_reserved: svcbuffer@0 {
23			compatible = "shared-dma-pool";
24			reg = <0x0 0x0 0x0 0x2000000>;
25			alignment = <0x1000>;
26			no-map;
27		};
28	};
29
30	cpus {
31		#address-cells = <1>;
32		#size-cells = <0>;
33
34		cpu0: cpu@0 {
35			compatible = "arm,cortex-a53";
36			device_type = "cpu";
37			enable-method = "psci";
38			reg = <0x0>;
39		};
40
41		cpu1: cpu@1 {
42			compatible = "arm,cortex-a53";
43			device_type = "cpu";
44			enable-method = "psci";
45			reg = <0x1>;
46		};
47
48		cpu2: cpu@2 {
49			compatible = "arm,cortex-a53";
50			device_type = "cpu";
51			enable-method = "psci";
52			reg = <0x2>;
53		};
54
55		cpu3: cpu@3 {
56			compatible = "arm,cortex-a53";
57			device_type = "cpu";
58			enable-method = "psci";
59			reg = <0x3>;
60		};
61	};
62
63	pmu {
64		compatible = "arm,armv8-pmuv3";
65		interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
66			     <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,
67			     <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>,
68			     <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
69		interrupt-affinity = <&cpu0>,
70				     <&cpu1>,
71				     <&cpu2>,
72				     <&cpu3>;
73		interrupt-parent = <&intc>;
74	};
75
76	psci {
77		compatible = "arm,psci-0.2";
78		method = "smc";
79	};
80
81	intc: interrupt-controller@fffc1000 {
82		compatible = "arm,gic-400", "arm,cortex-a15-gic";
83		#interrupt-cells = <3>;
84		interrupt-controller;
85		reg = <0x0 0xfffc1000 0x0 0x1000>,
86		      <0x0 0xfffc2000 0x0 0x2000>,
87		      <0x0 0xfffc4000 0x0 0x2000>,
88		      <0x0 0xfffc6000 0x0 0x2000>;
89	};
90
91	clocks {
92		cb_intosc_hs_div2_clk: cb-intosc-hs-div2-clk {
93			#clock-cells = <0>;
94			compatible = "fixed-clock";
95		};
96
97		cb_intosc_ls_clk: cb-intosc-ls-clk {
98			#clock-cells = <0>;
99			compatible = "fixed-clock";
100		};
101
102		f2s_free_clk: f2s-free-clk {
103			#clock-cells = <0>;
104			compatible = "fixed-clock";
105		};
106
107		osc1: osc1 {
108			#clock-cells = <0>;
109			compatible = "fixed-clock";
110		};
111
112		qspi_clk: qspi-clk {
113			#clock-cells = <0>;
114			compatible = "fixed-clock";
115			clock-frequency = <200000000>;
116		};
117	};
118
119	timer {
120		compatible = "arm,armv8-timer";
121		interrupt-parent = <&intc>;
122		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
123			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
124			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
125			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
126	};
127
128	usbphy0: usbphy {
129		#phy-cells = <0>;
130		compatible = "usb-nop-xceiv";
131	};
132
133	soc {
134		#address-cells = <1>;
135		#size-cells = <1>;
136		compatible = "simple-bus";
137		device_type = "soc";
138		interrupt-parent = <&intc>;
139		ranges = <0 0 0 0xffffffff>;
140
141		base_fpga_region {
142			#address-cells = <0x1>;
143			#size-cells = <0x1>;
144			compatible = "fpga-region";
145			fpga-mgr = <&fpga_mgr>;
146		};
147
148		clkmgr: clock-controller@ffd10000 {
149			compatible = "intel,agilex-clkmgr";
150			reg = <0xffd10000 0x1000>;
151			#clock-cells = <1>;
152		};
153
154		gmac0: ethernet@ff800000 {
155			compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac";
156			reg = <0xff800000 0x2000>;
157			interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
158			interrupt-names = "macirq";
159			mac-address = [00 00 00 00 00 00];
160			resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>;
161			reset-names = "stmmaceth", "stmmaceth-ocp";
162			tx-fifo-depth = <16384>;
163			rx-fifo-depth = <16384>;
164			snps,multicast-filter-bins = <256>;
165			iommus = <&smmu 1>;
166			altr,sysmgr-syscon = <&sysmgr 0x44 0>;
167			clocks = <&clkmgr AGILEX_EMAC0_CLK>, <&clkmgr AGILEX_EMAC_PTP_CLK>;
168			clock-names = "stmmaceth", "ptp_ref";
169			status = "disabled";
170		};
171
172		gmac1: ethernet@ff802000 {
173			compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac";
174			reg = <0xff802000 0x2000>;
175			interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
176			interrupt-names = "macirq";
177			mac-address = [00 00 00 00 00 00];
178			resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>;
179			reset-names = "stmmaceth", "stmmaceth-ocp";
180			tx-fifo-depth = <16384>;
181			rx-fifo-depth = <16384>;
182			snps,multicast-filter-bins = <256>;
183			iommus = <&smmu 2>;
184			altr,sysmgr-syscon = <&sysmgr 0x48 0>;
185			clocks = <&clkmgr AGILEX_EMAC1_CLK>, <&clkmgr AGILEX_EMAC_PTP_CLK>;
186			clock-names = "stmmaceth", "ptp_ref";
187			status = "disabled";
188		};
189
190		gmac2: ethernet@ff804000 {
191			compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac";
192			reg = <0xff804000 0x2000>;
193			interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
194			interrupt-names = "macirq";
195			mac-address = [00 00 00 00 00 00];
196			resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>;
197			reset-names = "stmmaceth", "stmmaceth-ocp";
198			tx-fifo-depth = <16384>;
199			rx-fifo-depth = <16384>;
200			snps,multicast-filter-bins = <256>;
201			iommus = <&smmu 3>;
202			altr,sysmgr-syscon = <&sysmgr 0x4c 0>;
203			clocks = <&clkmgr AGILEX_EMAC2_CLK>, <&clkmgr AGILEX_EMAC_PTP_CLK>;
204			clock-names = "stmmaceth", "ptp_ref";
205			status = "disabled";
206		};
207
208		gpio0: gpio@ffc03200 {
209			#address-cells = <1>;
210			#size-cells = <0>;
211			compatible = "snps,dw-apb-gpio";
212			reg = <0xffc03200 0x100>;
213			resets = <&rst GPIO0_RESET>;
214			status = "disabled";
215
216			porta: gpio-controller@0 {
217				compatible = "snps,dw-apb-gpio-port";
218				gpio-controller;
219				#gpio-cells = <2>;
220				snps,nr-gpios = <24>;
221				reg = <0>;
222				interrupt-controller;
223				#interrupt-cells = <2>;
224				interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
225			};
226		};
227
228		gpio1: gpio@ffc03300 {
229			#address-cells = <1>;
230			#size-cells = <0>;
231			compatible = "snps,dw-apb-gpio";
232			reg = <0xffc03300 0x100>;
233			resets = <&rst GPIO1_RESET>;
234			status = "disabled";
235
236			portb: gpio-controller@0 {
237				compatible = "snps,dw-apb-gpio-port";
238				gpio-controller;
239				#gpio-cells = <2>;
240				snps,nr-gpios = <24>;
241				reg = <0>;
242				interrupt-controller;
243				#interrupt-cells = <2>;
244				interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
245			};
246		};
247
248		i2c0: i2c@ffc02800 {
249			#address-cells = <1>;
250			#size-cells = <0>;
251			compatible = "snps,designware-i2c";
252			reg = <0xffc02800 0x100>;
253			interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
254			resets = <&rst I2C0_RESET>;
255			clocks = <&clkmgr AGILEX_L4_SP_CLK>;
256			status = "disabled";
257		};
258
259		i2c1: i2c@ffc02900 {
260			#address-cells = <1>;
261			#size-cells = <0>;
262			compatible = "snps,designware-i2c";
263			reg = <0xffc02900 0x100>;
264			interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
265			resets = <&rst I2C1_RESET>;
266			clocks = <&clkmgr AGILEX_L4_SP_CLK>;
267			status = "disabled";
268		};
269
270		i2c2: i2c@ffc02a00 {
271			#address-cells = <1>;
272			#size-cells = <0>;
273			compatible = "snps,designware-i2c";
274			reg = <0xffc02a00 0x100>;
275			interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
276			resets = <&rst I2C2_RESET>;
277			clocks = <&clkmgr AGILEX_L4_SP_CLK>;
278			status = "disabled";
279		};
280
281		i2c3: i2c@ffc02b00 {
282			#address-cells = <1>;
283			#size-cells = <0>;
284			compatible = "snps,designware-i2c";
285			reg = <0xffc02b00 0x100>;
286			interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
287			resets = <&rst I2C3_RESET>;
288			clocks = <&clkmgr AGILEX_L4_SP_CLK>;
289			status = "disabled";
290		};
291
292		i2c4: i2c@ffc02c00 {
293			#address-cells = <1>;
294			#size-cells = <0>;
295			compatible = "snps,designware-i2c";
296			reg = <0xffc02c00 0x100>;
297			interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
298			resets = <&rst I2C4_RESET>;
299			clocks = <&clkmgr AGILEX_L4_SP_CLK>;
300			status = "disabled";
301		};
302
303		mmc: mmc@ff808000 {
304			#address-cells = <1>;
305			#size-cells = <0>;
306			compatible = "altr,socfpga-dw-mshc";
307			reg = <0xff808000 0x1000>;
308			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
309			fifo-depth = <0x400>;
310			resets = <&rst SDMMC_RESET>;
311			reset-names = "reset";
312			clocks = <&clkmgr AGILEX_L4_MP_CLK>,
313				 <&clkmgr AGILEX_SDMMC_CLK>;
314			clock-names = "biu", "ciu";
315			iommus = <&smmu 5>;
316			status = "disabled";
317		};
318
319		nand: nand-controller@ffb90000 {
320			#address-cells = <1>;
321			#size-cells = <0>;
322			compatible = "altr,socfpga-denali-nand";
323			reg = <0xffb90000 0x10000>,
324			      <0xffb80000 0x1000>;
325			reg-names = "nand_data", "denali_reg";
326			interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
327			clocks = <&clkmgr AGILEX_NAND_CLK>,
328				 <&clkmgr AGILEX_NAND_X_CLK>,
329				 <&clkmgr AGILEX_NAND_ECC_CLK>;
330			clock-names = "nand", "nand_x", "ecc";
331			resets = <&rst NAND_RESET>, <&rst NAND_OCP_RESET>;
332			status = "disabled";
333		};
334
335		ocram: sram@ffe00000 {
336			compatible = "mmio-sram";
337			reg = <0xffe00000 0x40000>;
338		};
339
340		pdma: dma-controller@ffda0000 {
341			compatible = "arm,pl330", "arm,primecell";
342			reg = <0xffda0000 0x1000>;
343			interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
344				     <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
345				     <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
346				     <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
347				     <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
348				     <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
349				     <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
350				     <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
351				     <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
352			#dma-cells = <1>;
353			resets = <&rst DMA_RESET>, <&rst DMA_OCP_RESET>;
354			reset-names = "dma", "dma-ocp";
355			clocks = <&clkmgr AGILEX_L4_MAIN_CLK>;
356			clock-names = "apb_pclk";
357		};
358
359		rst: rstmgr@ffd11000 {
360			#reset-cells = <1>;
361			compatible = "altr,stratix10-rst-mgr";
362			reg = <0xffd11000 0x100>;
363		};
364
365		smmu: iommu@fa000000 {
366			compatible = "arm,mmu-500", "arm,smmu-v2";
367			reg = <0xfa000000 0x40000>;
368			#global-interrupts = <2>;
369			#iommu-cells = <1>;
370			interrupt-parent = <&intc>;
371			/* Global Secure Fault */
372			interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
373				/* Global Non-secure Fault */
374				<GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
375				/* Non-secure Context Interrupts (32) */
376				<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
377				<GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
378				<GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
379				<GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
380				<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
381				<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
382				<GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
383				<GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
384				<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
385				<GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
386				<GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
387				<GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
388				<GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
389				<GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
390				<GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
391				<GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
392				<GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
393				<GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
394				<GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
395				<GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
396				<GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
397				<GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
398				<GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
399				<GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
400				<GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
401				<GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
402				<GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
403				<GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
404				<GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
405				<GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
406				<GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
407				<GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
408			stream-match-mask = <0x7ff0>;
409			clocks = <&clkmgr AGILEX_MPU_CCU_CLK>,
410				 <&clkmgr AGILEX_L3_MAIN_FREE_CLK>,
411				 <&clkmgr AGILEX_L4_MAIN_CLK>;
412			status = "disabled";
413		};
414
415		spi0: spi@ffda4000 {
416			compatible = "snps,dw-apb-ssi";
417			#address-cells = <1>;
418			#size-cells = <0>;
419			reg = <0xffda4000 0x1000>;
420			interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
421			resets = <&rst SPIM0_RESET>;
422			reset-names = "spi";
423			reg-io-width = <4>;
424			num-cs = <4>;
425			clocks = <&clkmgr AGILEX_L4_MAIN_CLK>;
426			status = "disabled";
427		};
428
429		spi1: spi@ffda5000 {
430			compatible = "snps,dw-apb-ssi";
431			#address-cells = <1>;
432			#size-cells = <0>;
433			reg = <0xffda5000 0x1000>;
434			interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
435			resets = <&rst SPIM1_RESET>;
436			reset-names = "spi";
437			reg-io-width = <4>;
438			num-cs = <4>;
439			clocks = <&clkmgr AGILEX_L4_MAIN_CLK>;
440			status = "disabled";
441		};
442
443		sysmgr: sysmgr@ffd12000 {
444			compatible = "altr,sys-mgr-s10","altr,sys-mgr";
445			reg = <0xffd12000 0x500>;
446		};
447
448		timer0: timer0@ffc03000 {
449			compatible = "snps,dw-apb-timer";
450			interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
451			reg = <0xffc03000 0x100>;
452			clocks = <&clkmgr AGILEX_L4_SP_CLK>;
453			clock-names = "timer";
454		};
455
456		timer1: timer1@ffc03100 {
457			compatible = "snps,dw-apb-timer";
458			interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
459			reg = <0xffc03100 0x100>;
460			clocks = <&clkmgr AGILEX_L4_SP_CLK>;
461			clock-names = "timer";
462		};
463
464		timer2: timer2@ffd00000 {
465			compatible = "snps,dw-apb-timer";
466			interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
467			reg = <0xffd00000 0x100>;
468			clocks = <&clkmgr AGILEX_L4_SP_CLK>;
469			clock-names = "timer";
470		};
471
472		timer3: timer3@ffd00100 {
473			compatible = "snps,dw-apb-timer";
474			interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
475			reg = <0xffd00100 0x100>;
476			clocks = <&clkmgr AGILEX_L4_SP_CLK>;
477			clock-names = "timer";
478		};
479
480		uart0: serial@ffc02000 {
481			compatible = "snps,dw-apb-uart";
482			reg = <0xffc02000 0x100>;
483			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
484			reg-shift = <2>;
485			reg-io-width = <4>;
486			resets = <&rst UART0_RESET>;
487			status = "disabled";
488			clocks = <&clkmgr AGILEX_L4_SP_CLK>;
489		};
490
491		uart1: serial@ffc02100 {
492			compatible = "snps,dw-apb-uart";
493			reg = <0xffc02100 0x100>;
494			interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
495			reg-shift = <2>;
496			reg-io-width = <4>;
497			resets = <&rst UART1_RESET>;
498			clocks = <&clkmgr AGILEX_L4_SP_CLK>;
499			status = "disabled";
500		};
501
502		usb0: usb@ffb00000 {
503			compatible = "intel,socfpga-agilex-hsotg", "snps,dwc2";
504			reg = <0xffb00000 0x40000>;
505			interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
506			phys = <&usbphy0>;
507			phy-names = "usb2-phy";
508			resets = <&rst USB0_RESET>, <&rst USB0_OCP_RESET>;
509			reset-names = "dwc2", "dwc2-ecc";
510			clocks = <&clkmgr AGILEX_USB_CLK>;
511			clock-names = "otg";
512			iommus = <&smmu 6>;
513			status = "disabled";
514		};
515
516		usb1: usb@ffb40000 {
517			compatible = "intel,socfpga-agilex-hsotg", "snps,dwc2";
518			reg = <0xffb40000 0x40000>;
519			interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
520			phys = <&usbphy0>;
521			phy-names = "usb2-phy";
522			resets = <&rst USB1_RESET>, <&rst USB1_OCP_RESET>;
523			reset-names = "dwc2", "dwc2-ecc";
524			iommus = <&smmu 7>;
525			clocks = <&clkmgr AGILEX_USB_CLK>;
526			status = "disabled";
527		};
528
529		watchdog0: watchdog@ffd00200 {
530			compatible = "snps,dw-wdt";
531			reg = <0xffd00200 0x100>;
532			interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
533			resets = <&rst WATCHDOG0_RESET>;
534			clocks = <&clkmgr AGILEX_L4_SYS_FREE_CLK>;
535			status = "disabled";
536		};
537
538		watchdog1: watchdog@ffd00300 {
539			compatible = "snps,dw-wdt";
540			reg = <0xffd00300 0x100>;
541			interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
542			resets = <&rst WATCHDOG1_RESET>;
543			clocks = <&clkmgr AGILEX_L4_SYS_FREE_CLK>;
544			status = "disabled";
545		};
546
547		watchdog2: watchdog@ffd00400 {
548			compatible = "snps,dw-wdt";
549			reg = <0xffd00400 0x100>;
550			interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
551			resets = <&rst WATCHDOG2_RESET>;
552			clocks = <&clkmgr AGILEX_L4_SYS_FREE_CLK>;
553			status = "disabled";
554		};
555
556		watchdog3: watchdog@ffd00500 {
557			compatible = "snps,dw-wdt";
558			reg = <0xffd00500 0x100>;
559			interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
560			resets = <&rst WATCHDOG3_RESET>;
561			clocks = <&clkmgr AGILEX_L4_SYS_FREE_CLK>;
562			status = "disabled";
563		};
564
565		sdr: sdr@f8011100 {
566			compatible = "altr,sdr-ctl", "syscon";
567			reg = <0xf8011100 0xc0>;
568		};
569
570		eccmgr {
571			compatible = "altr,socfpga-s10-ecc-manager",
572				     "altr,socfpga-a10-ecc-manager";
573			altr,sysmgr-syscon = <&sysmgr>;
574			#address-cells = <1>;
575			#size-cells = <1>;
576			interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
577			interrupt-controller;
578			#interrupt-cells = <2>;
579			ranges;
580
581			sdramedac {
582				compatible = "altr,sdram-edac-s10";
583				altr,sdr-syscon = <&sdr>;
584				interrupts = <16 4>;
585			};
586
587			ocram-ecc@ff8cc000 {
588				compatible = "altr,socfpga-s10-ocram-ecc",
589					     "altr,socfpga-a10-ocram-ecc";
590				reg = <0xff8cc000 0x100>;
591				altr,ecc-parent = <&ocram>;
592				interrupts = <1 4>;
593			};
594
595			usb0-ecc@ff8c4000 {
596				compatible = "altr,socfpga-s10-usb-ecc",
597					     "altr,socfpga-usb-ecc";
598				reg = <0xff8c4000 0x100>;
599				altr,ecc-parent = <&usb0>;
600				interrupts = <2 4>;
601			};
602
603			emac0-rx-ecc@ff8c0000 {
604				compatible = "altr,socfpga-s10-eth-mac-ecc",
605					     "altr,socfpga-eth-mac-ecc";
606				reg = <0xff8c0000 0x100>;
607				altr,ecc-parent = <&gmac0>;
608				interrupts = <4 4>;
609			};
610
611			emac0-tx-ecc@ff8c0400 {
612				compatible = "altr,socfpga-s10-eth-mac-ecc",
613					     "altr,socfpga-eth-mac-ecc";
614				reg = <0xff8c0400 0x100>;
615				altr,ecc-parent = <&gmac0>;
616				interrupts = <5 4>;
617			};
618
619			sdmmca-ecc@ff8c8c00 {
620				compatible = "altr,socfpga-s10-sdmmc-ecc",
621					     "altr,socfpga-sdmmc-ecc";
622				reg = <0xff8c8c00 0x100>;
623				altr,ecc-parent = <&mmc>;
624				interrupts = <14 4>,
625					     <15 4>;
626			};
627		};
628
629		qspi: spi@ff8d2000 {
630			compatible = "intel,socfpga-qspi", "cdns,qspi-nor";
631			#address-cells = <1>;
632			#size-cells = <0>;
633			reg = <0xff8d2000 0x100>,
634			      <0xff900000 0x100000>;
635			interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
636			cdns,fifo-depth = <128>;
637			cdns,fifo-width = <4>;
638			cdns,trigger-address = <0x00000000>;
639			clocks = <&qspi_clk>;
640
641			status = "disabled";
642		};
643
644		firmware {
645			svc {
646				compatible = "intel,agilex-svc";
647				method = "smc";
648				memory-region = <&service_reserved>;
649
650				fpga_mgr: fpga-mgr {
651					compatible = "intel,agilex-soc-fpga-mgr";
652				};
653			};
654		};
655	};
656};
657