arm64: dts: socfpga: change the reset-name of "stmmaceth-ocp" to "ahb"

The "stmmaceth-ocp" reset line on the SoCFPGA stmmac ethernet driver is
the same as the "ahb" reset on a standard stmmac ethern

arm64: dts: socfpga: change the reset-name of "stmmaceth-ocp" to "ahb"

The "stmmaceth-ocp" reset line on the SoCFPGA stmmac ethernet driver is
the same as the "ahb" reset on a standard stmmac ethernet.

commit ("843f603762a5 dt-bindings: net: snps,dwmac: Add 'ahb'
reset/reset-name") documented the second reset signal as 'ahb' instead
of 'stmmaceth-ocp'. Change the reset-names of the SoCFPGA DWMAC driver to
'ahb'. In order not to break ABI, we will keep support in thedwmac-socfpga
driver to still make use of "stmmaceth-ocp".

This also fixes the dtbs_check warning:
ethernet@ff802000: reset-names:1: 'ahb' was expected

Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
---
v2: update commit message to further describe the reason for the change

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arm64: dts: agilex/stratix10/n5x: fix dtbs_check for rstmgr

The bindings expect "altr,rst-mgr" as a fallback in the rstmgr
compatible:

rstmgr@ffd11000: compatible: 'oneOf' conditional failed, one m

arm64: dts: agilex/stratix10/n5x: fix dtbs_check for rstmgr

The bindings expect "altr,rst-mgr" as a fallback in the rstmgr
compatible:

rstmgr@ffd11000: compatible: 'oneOf' conditional failed, one must be fixed:
['altr,stratix10-rst-mgr'] is too short
'altr,rst-mgr' was expected

Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>

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arm64: dts: socfpga: agilex/stratix10: fix dtbs_check warnings for sram

sram@ffe00000: 'ranges' is a required property
sram@ffe00000: '#size-cells' is a required property
sram@ffe00000: '#address-ce

arm64: dts: socfpga: agilex/stratix10: fix dtbs_check warnings for sram

sram@ffe00000: 'ranges' is a required property
sram@ffe00000: '#size-cells' is a required property
sram@ffe00000: '#address-cells' is a required property

Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>

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arm64: dts: socfpga: change address-cells to support 64-bit addressing

Update the address-cells and size-cells to 2 in order to support 64-bit
addressing.

Signed-off-by: Dinh Nguyen <dinguyen@kerne

arm64: dts: socfpga: change address-cells to support 64-bit addressing

Update the address-cells and size-cells to 2 in order to support 64-bit
addressing.

Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>

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arm64: dts: add pinctrl-single property for Stratix10/Agilex

The Stratix10/Agilex has a pin control IP that can make use of the
pinctrl-single driver.

Add the pinctrl-single dts property for the St

arm64: dts: add pinctrl-single property for Stratix10/Agilex

The Stratix10/Agilex has a pin control IP that can make use of the
pinctrl-single driver.

Add the pinctrl-single dts property for the Stratix10/Agilex
platforms.

Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
---
v2: no changes

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arm64: dts: socfpga: Add clk-phase-sd-hs property to the sdmmc node

The sdmmc controller's CIU(Card Interface Unit) clock's phase can be
adjusted through the register in the system manager. Add the

arm64: dts: socfpga: Add clk-phase-sd-hs property to the sdmmc node

The sdmmc controller's CIU(Card Interface Unit) clock's phase can be
adjusted through the register in the system manager. Add the binding
"altr,sysmgr-syscon" to the SDMMC node for the driver to access the
system manager. Add the "clk-phase-sd-hs" property in the SDMMC node to
designate the smpsel and drvsel properties for the CIU clock.

Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>

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arm64: dts: intel: socfpga_agilex: use defined GIC interrupt type for ECC

Use defined GIC interrupt type instead of hard-coded numbers for ECC
(Error Correction Code) memory, which creates edac sysf

arm64: dts: intel: socfpga_agilex: use defined GIC interrupt type for ECC

Use defined GIC interrupt type instead of hard-coded numbers for ECC
(Error Correction Code) memory, which creates edac sysfs interface.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Niravkumar L Rabara <niravkumar.l.rabara@intel.com>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>

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arm64: dts: stratix10/agilex: drop useless 'dma-channels/requests' properties

The pl330 DMA controller provides number of DMA channels and requests
through its registers, so duplicating this informa

arm64: dts: stratix10/agilex: drop useless 'dma-channels/requests' properties

The pl330 DMA controller provides number of DMA channels and requests
through its registers, so duplicating this information (with a chance of
mistakes) in DTS is pointless. Additionally the DTS used always wrong
property names which causes DT schema check failures - the bindings
documented 'dma-channels' and 'dma-requests' properties without leading
hash sign.

Reported-by: Rob Herring <robh@kernel.org>
Suggested-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20220430121902.59895-4-krzysztof.kozlowski@linaro.org

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arm64: dts: agilex/stratix10: add clock-names to USB DWC2 node

USB DWC2 requires clock-names:

arm64/boot/dts/altera/socfpga_stratix10_socdk_nand.dt.yaml:
usb@ffb00000: 'clock-names' is a requ

arm64: dts: agilex/stratix10: add clock-names to USB DWC2 node

USB DWC2 requires clock-names:

arm64/boot/dts/altera/socfpga_stratix10_socdk_nand.dt.yaml:
usb@ffb00000: 'clock-names' is a required property

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>

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arm64: dts: agilex: use the compatible "intel,socfpga-agilex-hsotg"

The DWC2 USB controller on the Agilex platform does not support clock
gating, so use the chip specific "intel,socfpga-agilex-hsotg

arm64: dts: agilex: use the compatible "intel,socfpga-agilex-hsotg"

The DWC2 USB controller on the Agilex platform does not support clock
gating, so use the chip specific "intel,socfpga-agilex-hsotg"
compatible.

Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Link: https://lore.kernel.org/r/20220125161821.1951906-3-dinguyen@kernel.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

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arm64: dts: agilex: align pl330 node name with dtschema

Fixes dtbs_check warnings like:

pdma@ffda0000: $nodename:0: 'pdma@ffda0000' does not match '^dma-controller(@.*)?$'

Signed-off-by: Krzyszt

arm64: dts: agilex: align pl330 node name with dtschema

Fixes dtbs_check warnings like:

pdma@ffda0000: $nodename:0: 'pdma@ffda0000' does not match '^dma-controller(@.*)?$'

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>

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arm64: dts: agilex: use the compatible "intel,socfpga-agilex-hsotg"

The DWC2 USB controller on the Agilex platform does not support clock
gating, so use the chip specific "intel,socfpga-agilex-hsotg

arm64: dts: agilex: use the compatible "intel,socfpga-agilex-hsotg"

The DWC2 USB controller on the Agilex platform does not support clock
gating, so use the chip specific "intel,socfpga-agilex-hsotg"
compatible.

Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>

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arm64: dts: agilex: align mmc node names with dtschema

The Synopsys DW MSHC bindings require node name to be 'mmc':

dwmmc0@ff808000: $nodename:0: 'dwmmc0@ff808000' does not match '^mmc(@.*)?$'

S

arm64: dts: agilex: align mmc node names with dtschema

The Synopsys DW MSHC bindings require node name to be 'mmc':

dwmmc0@ff808000: $nodename:0: 'dwmmc0@ff808000' does not match '^mmc(@.*)?$'

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>

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ARM: dts: socfpga: change qspi to "intel,socfpga-qspi"

Because of commit 9cb2ff111712 ("spi: cadence-quadspi: Disable Auto-HW polling"),
which does a write to the CQSPI_REG_WR_COMPLETION_CTRL regist

ARM: dts: socfpga: change qspi to "intel,socfpga-qspi"

Because of commit 9cb2ff111712 ("spi: cadence-quadspi: Disable Auto-HW polling"),
which does a write to the CQSPI_REG_WR_COMPLETION_CTRL register
regardless of any condition. Well, the Cadence QuadSPI controller on
Intel's SoCFPGA platforms does not implement the
CQSPI_REG_WR_COMPLETION_CTRL register, thus a write to this register
results in a crash!

So starting with v5.16, I introduced the patch
98d948eb833 ("spi: cadence-quadspi: fix write completion support"),
which adds the dts compatible "intel,socfpga-qspi" that is specific for
versions that doesn't have the CQSPI_REG_WR_COMPLETION_CTRL register implemented.

Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
---
v3: revert back to "intel,socfpga-qspi"
v2: use both "cdns,qspi-nor" and "cdns,qspi-nor-0010"

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ARM: dts: socfpga: change qspi to "intel,socfpga-qspi"

commit 36de991e93908f7ad5c2a0eac9c4ecf8b723fa4a upstream.

Because of commit 9cb2ff111712 ("spi: cadence-quadspi: Disable Auto-HW polling"),
wh

ARM: dts: socfpga: change qspi to "intel,socfpga-qspi"

commit 36de991e93908f7ad5c2a0eac9c4ecf8b723fa4a upstream.

Because of commit 9cb2ff111712 ("spi: cadence-quadspi: Disable Auto-HW polling"),
which does a write to the CQSPI_REG_WR_COMPLETION_CTRL register
regardless of any condition. Well, the Cadence QuadSPI controller on
Intel's SoCFPGA platforms does not implement the
CQSPI_REG_WR_COMPLETION_CTRL register, thus a write to this register
results in a crash!

So starting with v5.16, I introduced the patch
98d948eb833 ("spi: cadence-quadspi: fix write completion support"),
which adds the dts compatible "intel,socfpga-qspi" that is specific for
versions that doesn't have the CQSPI_REG_WR_COMPLETION_CTRL register implemented.

Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
[IA: submitted for linux-5.15.y]
Signed-off-by: Ian Abbott <abbotti@mev.co.uk>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

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arm64: dts: agilex: use the compatible "intel,socfpga-agilex-hsotg"

[ Upstream commit 268a491aebc25e6dc7c618903b09ac3a2e8af530 ]

The DWC2 USB controller on the Agilex platform does not support cloc

arm64: dts: agilex: use the compatible "intel,socfpga-agilex-hsotg"

[ Upstream commit 268a491aebc25e6dc7c618903b09ac3a2e8af530 ]

The DWC2 USB controller on the Agilex platform does not support clock
gating, so use the chip specific "intel,socfpga-agilex-hsotg"
compatible.

Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>

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arm64: dts: intel: socfpga_agilex: align node names with dtschema

Align the NAND, GIC and UART node names with dtschema to silence
dtbs_check warnings like:

arch/arm64/boot/dts/intel/socfpga_ag

arm64: dts: intel: socfpga_agilex: align node names with dtschema

Align the NAND, GIC and UART node names with dtschema to silence
dtbs_check warnings like:

arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dt.yaml:
intc@fffc1000: $nodename:0: 'intc@fffc1000' does not match '^interrupt-controller(@[0-9a-f,]+)*$'
arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dt.yaml:
serial0@ffc02000: $nodename:0: 'serial0@ffc02000' does not match '^serial(@[0-9a-f,]+)*$'

Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>

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arm64: dts: intel: socfpga_agilex: use defined for GIC interrupts

Use human-readable defines for GIC interrupt type and flag, instead of
hard-coding the numbers. It makes review easier. No functio

arm64: dts: intel: socfpga_agilex: use defined for GIC interrupts

Use human-readable defines for GIC interrupt type and flag, instead of
hard-coding the numbers. It makes review easier. No functional change.

Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>

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arm64: dts: intel: socfpga_agilex: move usbphy out of soc node

The usual usb-nop-xceiv USB phy node should be under root node, to fix
dtc warning:

arch/arm64/boot/dts/intel/socfpga_agilex.dtsi:

arm64: dts: intel: socfpga_agilex: move usbphy out of soc node

The usual usb-nop-xceiv USB phy node should be under root node, to fix
dtc warning:

arch/arm64/boot/dts/intel/socfpga_agilex.dtsi:472.21-476.5:
Warning (simple_bus_reg): /soc/usbphy@0: missing or empty reg/ranges property

Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>

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arm64: dts: intel: socfpga_agilex: remove default status=okay

New nodes are okay by default.

Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>

arm64: dts: intel: socfpga_agilex: move timer out of soc node

The ARM architected timer is part of ARM CPU design therefore by
convention it should not be inside the soc node. This also fixes dtc
w

arm64: dts: intel: socfpga_agilex: move timer out of soc node

The ARM architected timer is part of ARM CPU design therefore by
convention it should not be inside the soc node. This also fixes dtc
warning like:

arch/arm64/boot/dts/intel/socfpga_agilex.dtsi:410.9-416.5:
Warning (simple_bus_reg): /soc/timer: missing or empty reg/ranges property

Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>

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arm64: dts: intel: socfpga_agilex: move clocks out of soc node

The clocks are usually not part of the SoC but provided on the board
(external oscillators). Moving them out of soc node fixes dtc war

arm64: dts: intel: socfpga_agilex: move clocks out of soc node

The clocks are usually not part of the SoC but provided on the board
(external oscillators). Moving them out of soc node fixes dtc warning:

arch/arm64/boot/dts/intel/socfpga_agilex.dtsi:111.10-137.5:
Warning (simple_bus_reg): /soc/clocks: missing or empty reg/ranges property

Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>

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arm64: dts: agilex: fix phy interface bit shift for gmac1 and gmac2

The shift for the phy_intf_sel bit in the system manager for gmac1 and
gmac2 should be 0.

Fixes: 2f804ba7aa9ee ("arm64: dts: agil

arm64: dts: agilex: fix phy interface bit shift for gmac1 and gmac2

The shift for the phy_intf_sel bit in the system manager for gmac1 and
gmac2 should be 0.

Fixes: 2f804ba7aa9ee ("arm64: dts: agilex: Add SysMgr to Ethernet nodes")
Cc: stable@vger.kernel.org
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>

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arm64: dts: agilex: fix phy interface bit shift for gmac1 and gmac2

commit b7ff3a447d100c999d9848353ef8a4046831d893 upstream.

The shift for the phy_intf_sel bit in the system manager for gmac1 and

arm64: dts: agilex: fix phy interface bit shift for gmac1 and gmac2

commit b7ff3a447d100c999d9848353ef8a4046831d893 upstream.

The shift for the phy_intf_sel bit in the system manager for gmac1 and
gmac2 should be 0.

Fixes: 2f804ba7aa9ee ("arm64: dts: agilex: Add SysMgr to Ethernet nodes")
Cc: stable@vger.kernel.org
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

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arm64: dts: stratix10/agilex: add the ptp_ref clock

Add the ptp_ref clock for the GMACs.

Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>