1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (C) 2019, Intel Corporation 4 */ 5 6/dts-v1/; 7#include <dt-bindings/reset/altr,rst-mgr-s10.h> 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/clock/agilex-clock.h> 10 11/ { 12 compatible = "intel,socfpga-agilex"; 13 #address-cells = <2>; 14 #size-cells = <2>; 15 16 reserved-memory { 17 #address-cells = <2>; 18 #size-cells = <2>; 19 ranges; 20 21 service_reserved: svcbuffer@0 { 22 compatible = "shared-dma-pool"; 23 reg = <0x0 0x0 0x0 0x2000000>; 24 alignment = <0x1000>; 25 no-map; 26 }; 27 }; 28 29 cpus { 30 #address-cells = <1>; 31 #size-cells = <0>; 32 33 cpu0: cpu@0 { 34 compatible = "arm,cortex-a53"; 35 device_type = "cpu"; 36 enable-method = "psci"; 37 reg = <0x0>; 38 }; 39 40 cpu1: cpu@1 { 41 compatible = "arm,cortex-a53"; 42 device_type = "cpu"; 43 enable-method = "psci"; 44 reg = <0x1>; 45 }; 46 47 cpu2: cpu@2 { 48 compatible = "arm,cortex-a53"; 49 device_type = "cpu"; 50 enable-method = "psci"; 51 reg = <0x2>; 52 }; 53 54 cpu3: cpu@3 { 55 compatible = "arm,cortex-a53"; 56 device_type = "cpu"; 57 enable-method = "psci"; 58 reg = <0x3>; 59 }; 60 }; 61 62 pmu { 63 compatible = "arm,armv8-pmuv3"; 64 interrupts = <0 170 4>, 65 <0 171 4>, 66 <0 172 4>, 67 <0 173 4>; 68 interrupt-affinity = <&cpu0>, 69 <&cpu1>, 70 <&cpu2>, 71 <&cpu3>; 72 interrupt-parent = <&intc>; 73 }; 74 75 psci { 76 compatible = "arm,psci-0.2"; 77 method = "smc"; 78 }; 79 80 intc: intc@fffc1000 { 81 compatible = "arm,gic-400", "arm,cortex-a15-gic"; 82 #interrupt-cells = <3>; 83 interrupt-controller; 84 reg = <0x0 0xfffc1000 0x0 0x1000>, 85 <0x0 0xfffc2000 0x0 0x2000>, 86 <0x0 0xfffc4000 0x0 0x2000>, 87 <0x0 0xfffc6000 0x0 0x2000>; 88 }; 89 90 clocks { 91 cb_intosc_hs_div2_clk: cb-intosc-hs-div2-clk { 92 #clock-cells = <0>; 93 compatible = "fixed-clock"; 94 }; 95 96 cb_intosc_ls_clk: cb-intosc-ls-clk { 97 #clock-cells = <0>; 98 compatible = "fixed-clock"; 99 }; 100 101 f2s_free_clk: f2s-free-clk { 102 #clock-cells = <0>; 103 compatible = "fixed-clock"; 104 }; 105 106 osc1: osc1 { 107 #clock-cells = <0>; 108 compatible = "fixed-clock"; 109 }; 110 111 qspi_clk: qspi-clk { 112 #clock-cells = <0>; 113 compatible = "fixed-clock"; 114 clock-frequency = <200000000>; 115 }; 116 }; 117 118 timer { 119 compatible = "arm,armv8-timer"; 120 interrupt-parent = <&intc>; 121 interrupts = <1 13 0xf08>, 122 <1 14 0xf08>, 123 <1 11 0xf08>, 124 <1 10 0xf08>; 125 }; 126 127 soc { 128 #address-cells = <1>; 129 #size-cells = <1>; 130 compatible = "simple-bus"; 131 device_type = "soc"; 132 interrupt-parent = <&intc>; 133 ranges = <0 0 0 0xffffffff>; 134 135 base_fpga_region { 136 #address-cells = <0x1>; 137 #size-cells = <0x1>; 138 compatible = "fpga-region"; 139 fpga-mgr = <&fpga_mgr>; 140 }; 141 142 clkmgr: clock-controller@ffd10000 { 143 compatible = "intel,agilex-clkmgr"; 144 reg = <0xffd10000 0x1000>; 145 #clock-cells = <1>; 146 }; 147 148 gmac0: ethernet@ff800000 { 149 compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac"; 150 reg = <0xff800000 0x2000>; 151 interrupts = <0 90 4>; 152 interrupt-names = "macirq"; 153 mac-address = [00 00 00 00 00 00]; 154 resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>; 155 reset-names = "stmmaceth", "stmmaceth-ocp"; 156 tx-fifo-depth = <16384>; 157 rx-fifo-depth = <16384>; 158 snps,multicast-filter-bins = <256>; 159 iommus = <&smmu 1>; 160 altr,sysmgr-syscon = <&sysmgr 0x44 0>; 161 clocks = <&clkmgr AGILEX_EMAC0_CLK>, <&clkmgr AGILEX_EMAC_PTP_CLK>; 162 clock-names = "stmmaceth", "ptp_ref"; 163 status = "disabled"; 164 }; 165 166 gmac1: ethernet@ff802000 { 167 compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac"; 168 reg = <0xff802000 0x2000>; 169 interrupts = <0 91 4>; 170 interrupt-names = "macirq"; 171 mac-address = [00 00 00 00 00 00]; 172 resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>; 173 reset-names = "stmmaceth", "stmmaceth-ocp"; 174 tx-fifo-depth = <16384>; 175 rx-fifo-depth = <16384>; 176 snps,multicast-filter-bins = <256>; 177 iommus = <&smmu 2>; 178 altr,sysmgr-syscon = <&sysmgr 0x48 0>; 179 clocks = <&clkmgr AGILEX_EMAC1_CLK>, <&clkmgr AGILEX_EMAC_PTP_CLK>; 180 clock-names = "stmmaceth", "ptp_ref"; 181 status = "disabled"; 182 }; 183 184 gmac2: ethernet@ff804000 { 185 compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac"; 186 reg = <0xff804000 0x2000>; 187 interrupts = <0 92 4>; 188 interrupt-names = "macirq"; 189 mac-address = [00 00 00 00 00 00]; 190 resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>; 191 reset-names = "stmmaceth", "stmmaceth-ocp"; 192 tx-fifo-depth = <16384>; 193 rx-fifo-depth = <16384>; 194 snps,multicast-filter-bins = <256>; 195 iommus = <&smmu 3>; 196 altr,sysmgr-syscon = <&sysmgr 0x4c 0>; 197 clocks = <&clkmgr AGILEX_EMAC2_CLK>, <&clkmgr AGILEX_EMAC_PTP_CLK>; 198 clock-names = "stmmaceth", "ptp_ref"; 199 status = "disabled"; 200 }; 201 202 gpio0: gpio@ffc03200 { 203 #address-cells = <1>; 204 #size-cells = <0>; 205 compatible = "snps,dw-apb-gpio"; 206 reg = <0xffc03200 0x100>; 207 resets = <&rst GPIO0_RESET>; 208 status = "disabled"; 209 210 porta: gpio-controller@0 { 211 compatible = "snps,dw-apb-gpio-port"; 212 gpio-controller; 213 #gpio-cells = <2>; 214 snps,nr-gpios = <24>; 215 reg = <0>; 216 interrupt-controller; 217 #interrupt-cells = <2>; 218 interrupts = <0 110 4>; 219 }; 220 }; 221 222 gpio1: gpio@ffc03300 { 223 #address-cells = <1>; 224 #size-cells = <0>; 225 compatible = "snps,dw-apb-gpio"; 226 reg = <0xffc03300 0x100>; 227 resets = <&rst GPIO1_RESET>; 228 status = "disabled"; 229 230 portb: gpio-controller@0 { 231 compatible = "snps,dw-apb-gpio-port"; 232 gpio-controller; 233 #gpio-cells = <2>; 234 snps,nr-gpios = <24>; 235 reg = <0>; 236 interrupt-controller; 237 #interrupt-cells = <2>; 238 interrupts = <0 111 4>; 239 }; 240 }; 241 242 i2c0: i2c@ffc02800 { 243 #address-cells = <1>; 244 #size-cells = <0>; 245 compatible = "snps,designware-i2c"; 246 reg = <0xffc02800 0x100>; 247 interrupts = <0 103 4>; 248 resets = <&rst I2C0_RESET>; 249 clocks = <&clkmgr AGILEX_L4_SP_CLK>; 250 status = "disabled"; 251 }; 252 253 i2c1: i2c@ffc02900 { 254 #address-cells = <1>; 255 #size-cells = <0>; 256 compatible = "snps,designware-i2c"; 257 reg = <0xffc02900 0x100>; 258 interrupts = <0 104 4>; 259 resets = <&rst I2C1_RESET>; 260 clocks = <&clkmgr AGILEX_L4_SP_CLK>; 261 status = "disabled"; 262 }; 263 264 i2c2: i2c@ffc02a00 { 265 #address-cells = <1>; 266 #size-cells = <0>; 267 compatible = "snps,designware-i2c"; 268 reg = <0xffc02a00 0x100>; 269 interrupts = <0 105 4>; 270 resets = <&rst I2C2_RESET>; 271 clocks = <&clkmgr AGILEX_L4_SP_CLK>; 272 status = "disabled"; 273 }; 274 275 i2c3: i2c@ffc02b00 { 276 #address-cells = <1>; 277 #size-cells = <0>; 278 compatible = "snps,designware-i2c"; 279 reg = <0xffc02b00 0x100>; 280 interrupts = <0 106 4>; 281 resets = <&rst I2C3_RESET>; 282 clocks = <&clkmgr AGILEX_L4_SP_CLK>; 283 status = "disabled"; 284 }; 285 286 i2c4: i2c@ffc02c00 { 287 #address-cells = <1>; 288 #size-cells = <0>; 289 compatible = "snps,designware-i2c"; 290 reg = <0xffc02c00 0x100>; 291 interrupts = <0 107 4>; 292 resets = <&rst I2C4_RESET>; 293 clocks = <&clkmgr AGILEX_L4_SP_CLK>; 294 status = "disabled"; 295 }; 296 297 mmc: dwmmc0@ff808000 { 298 #address-cells = <1>; 299 #size-cells = <0>; 300 compatible = "altr,socfpga-dw-mshc"; 301 reg = <0xff808000 0x1000>; 302 interrupts = <0 96 4>; 303 fifo-depth = <0x400>; 304 resets = <&rst SDMMC_RESET>; 305 reset-names = "reset"; 306 clocks = <&clkmgr AGILEX_L4_MP_CLK>, 307 <&clkmgr AGILEX_SDMMC_CLK>; 308 clock-names = "biu", "ciu"; 309 iommus = <&smmu 5>; 310 status = "disabled"; 311 }; 312 313 nand: nand@ffb90000 { 314 #address-cells = <1>; 315 #size-cells = <0>; 316 compatible = "altr,socfpga-denali-nand"; 317 reg = <0xffb90000 0x10000>, 318 <0xffb80000 0x1000>; 319 reg-names = "nand_data", "denali_reg"; 320 interrupts = <0 97 4>; 321 clocks = <&clkmgr AGILEX_NAND_CLK>, 322 <&clkmgr AGILEX_NAND_X_CLK>, 323 <&clkmgr AGILEX_NAND_ECC_CLK>; 324 clock-names = "nand", "nand_x", "ecc"; 325 resets = <&rst NAND_RESET>, <&rst NAND_OCP_RESET>; 326 status = "disabled"; 327 }; 328 329 ocram: sram@ffe00000 { 330 compatible = "mmio-sram"; 331 reg = <0xffe00000 0x40000>; 332 }; 333 334 pdma: pdma@ffda0000 { 335 compatible = "arm,pl330", "arm,primecell"; 336 reg = <0xffda0000 0x1000>; 337 interrupts = <0 81 4>, 338 <0 82 4>, 339 <0 83 4>, 340 <0 84 4>, 341 <0 85 4>, 342 <0 86 4>, 343 <0 87 4>, 344 <0 88 4>, 345 <0 89 4>; 346 #dma-cells = <1>; 347 #dma-channels = <8>; 348 #dma-requests = <32>; 349 resets = <&rst DMA_RESET>, <&rst DMA_OCP_RESET>; 350 reset-names = "dma", "dma-ocp"; 351 clocks = <&clkmgr AGILEX_L4_MAIN_CLK>; 352 clock-names = "apb_pclk"; 353 }; 354 355 rst: rstmgr@ffd11000 { 356 #reset-cells = <1>; 357 compatible = "altr,stratix10-rst-mgr"; 358 reg = <0xffd11000 0x100>; 359 }; 360 361 smmu: iommu@fa000000 { 362 compatible = "arm,mmu-500", "arm,smmu-v2"; 363 reg = <0xfa000000 0x40000>; 364 #global-interrupts = <2>; 365 #iommu-cells = <1>; 366 interrupt-parent = <&intc>; 367 interrupts = <0 128 4>, /* Global Secure Fault */ 368 <0 129 4>, /* Global Non-secure Fault */ 369 /* Non-secure Context Interrupts (32) */ 370 <0 138 4>, <0 139 4>, <0 140 4>, <0 141 4>, 371 <0 142 4>, <0 143 4>, <0 144 4>, <0 145 4>, 372 <0 146 4>, <0 147 4>, <0 148 4>, <0 149 4>, 373 <0 150 4>, <0 151 4>, <0 152 4>, <0 153 4>, 374 <0 154 4>, <0 155 4>, <0 156 4>, <0 157 4>, 375 <0 158 4>, <0 159 4>, <0 160 4>, <0 161 4>, 376 <0 162 4>, <0 163 4>, <0 164 4>, <0 165 4>, 377 <0 166 4>, <0 167 4>, <0 168 4>, <0 169 4>; 378 stream-match-mask = <0x7ff0>; 379 clocks = <&clkmgr AGILEX_MPU_CCU_CLK>, 380 <&clkmgr AGILEX_L3_MAIN_FREE_CLK>, 381 <&clkmgr AGILEX_L4_MAIN_CLK>; 382 status = "disabled"; 383 }; 384 385 spi0: spi@ffda4000 { 386 compatible = "snps,dw-apb-ssi"; 387 #address-cells = <1>; 388 #size-cells = <0>; 389 reg = <0xffda4000 0x1000>; 390 interrupts = <0 99 4>; 391 resets = <&rst SPIM0_RESET>; 392 reset-names = "spi"; 393 reg-io-width = <4>; 394 num-cs = <4>; 395 clocks = <&clkmgr AGILEX_L4_MAIN_CLK>; 396 status = "disabled"; 397 }; 398 399 spi1: spi@ffda5000 { 400 compatible = "snps,dw-apb-ssi"; 401 #address-cells = <1>; 402 #size-cells = <0>; 403 reg = <0xffda5000 0x1000>; 404 interrupts = <0 100 4>; 405 resets = <&rst SPIM1_RESET>; 406 reset-names = "spi"; 407 reg-io-width = <4>; 408 num-cs = <4>; 409 clocks = <&clkmgr AGILEX_L4_MAIN_CLK>; 410 status = "disabled"; 411 }; 412 413 sysmgr: sysmgr@ffd12000 { 414 compatible = "altr,sys-mgr-s10","altr,sys-mgr"; 415 reg = <0xffd12000 0x500>; 416 }; 417 418 timer0: timer0@ffc03000 { 419 compatible = "snps,dw-apb-timer"; 420 interrupts = <0 113 4>; 421 reg = <0xffc03000 0x100>; 422 clocks = <&clkmgr AGILEX_L4_SP_CLK>; 423 clock-names = "timer"; 424 }; 425 426 timer1: timer1@ffc03100 { 427 compatible = "snps,dw-apb-timer"; 428 interrupts = <0 114 4>; 429 reg = <0xffc03100 0x100>; 430 clocks = <&clkmgr AGILEX_L4_SP_CLK>; 431 clock-names = "timer"; 432 }; 433 434 timer2: timer2@ffd00000 { 435 compatible = "snps,dw-apb-timer"; 436 interrupts = <0 115 4>; 437 reg = <0xffd00000 0x100>; 438 clocks = <&clkmgr AGILEX_L4_SP_CLK>; 439 clock-names = "timer"; 440 }; 441 442 timer3: timer3@ffd00100 { 443 compatible = "snps,dw-apb-timer"; 444 interrupts = <0 116 4>; 445 reg = <0xffd00100 0x100>; 446 clocks = <&clkmgr AGILEX_L4_SP_CLK>; 447 clock-names = "timer"; 448 }; 449 450 uart0: serial0@ffc02000 { 451 compatible = "snps,dw-apb-uart"; 452 reg = <0xffc02000 0x100>; 453 interrupts = <0 108 4>; 454 reg-shift = <2>; 455 reg-io-width = <4>; 456 resets = <&rst UART0_RESET>; 457 status = "disabled"; 458 clocks = <&clkmgr AGILEX_L4_SP_CLK>; 459 }; 460 461 uart1: serial1@ffc02100 { 462 compatible = "snps,dw-apb-uart"; 463 reg = <0xffc02100 0x100>; 464 interrupts = <0 109 4>; 465 reg-shift = <2>; 466 reg-io-width = <4>; 467 resets = <&rst UART1_RESET>; 468 clocks = <&clkmgr AGILEX_L4_SP_CLK>; 469 status = "disabled"; 470 }; 471 472 usbphy0: usbphy@0 { 473 #phy-cells = <0>; 474 compatible = "usb-nop-xceiv"; 475 }; 476 477 usb0: usb@ffb00000 { 478 compatible = "snps,dwc2"; 479 reg = <0xffb00000 0x40000>; 480 interrupts = <0 93 4>; 481 phys = <&usbphy0>; 482 phy-names = "usb2-phy"; 483 resets = <&rst USB0_RESET>, <&rst USB0_OCP_RESET>; 484 reset-names = "dwc2", "dwc2-ecc"; 485 clocks = <&clkmgr AGILEX_USB_CLK>; 486 iommus = <&smmu 6>; 487 status = "disabled"; 488 }; 489 490 usb1: usb@ffb40000 { 491 compatible = "snps,dwc2"; 492 reg = <0xffb40000 0x40000>; 493 interrupts = <0 94 4>; 494 phys = <&usbphy0>; 495 phy-names = "usb2-phy"; 496 resets = <&rst USB1_RESET>, <&rst USB1_OCP_RESET>; 497 reset-names = "dwc2", "dwc2-ecc"; 498 iommus = <&smmu 7>; 499 clocks = <&clkmgr AGILEX_USB_CLK>; 500 status = "disabled"; 501 }; 502 503 watchdog0: watchdog@ffd00200 { 504 compatible = "snps,dw-wdt"; 505 reg = <0xffd00200 0x100>; 506 interrupts = <0 117 4>; 507 resets = <&rst WATCHDOG0_RESET>; 508 clocks = <&clkmgr AGILEX_L4_SYS_FREE_CLK>; 509 status = "disabled"; 510 }; 511 512 watchdog1: watchdog@ffd00300 { 513 compatible = "snps,dw-wdt"; 514 reg = <0xffd00300 0x100>; 515 interrupts = <0 118 4>; 516 resets = <&rst WATCHDOG1_RESET>; 517 clocks = <&clkmgr AGILEX_L4_SYS_FREE_CLK>; 518 status = "disabled"; 519 }; 520 521 watchdog2: watchdog@ffd00400 { 522 compatible = "snps,dw-wdt"; 523 reg = <0xffd00400 0x100>; 524 interrupts = <0 125 4>; 525 resets = <&rst WATCHDOG2_RESET>; 526 clocks = <&clkmgr AGILEX_L4_SYS_FREE_CLK>; 527 status = "disabled"; 528 }; 529 530 watchdog3: watchdog@ffd00500 { 531 compatible = "snps,dw-wdt"; 532 reg = <0xffd00500 0x100>; 533 interrupts = <0 126 4>; 534 resets = <&rst WATCHDOG3_RESET>; 535 clocks = <&clkmgr AGILEX_L4_SYS_FREE_CLK>; 536 status = "disabled"; 537 }; 538 539 sdr: sdr@f8011100 { 540 compatible = "altr,sdr-ctl", "syscon"; 541 reg = <0xf8011100 0xc0>; 542 }; 543 544 eccmgr { 545 compatible = "altr,socfpga-s10-ecc-manager", 546 "altr,socfpga-a10-ecc-manager"; 547 altr,sysmgr-syscon = <&sysmgr>; 548 #address-cells = <1>; 549 #size-cells = <1>; 550 interrupts = <0 15 4>; 551 interrupt-controller; 552 #interrupt-cells = <2>; 553 ranges; 554 555 sdramedac { 556 compatible = "altr,sdram-edac-s10"; 557 altr,sdr-syscon = <&sdr>; 558 interrupts = <16 4>; 559 }; 560 561 ocram-ecc@ff8cc000 { 562 compatible = "altr,socfpga-s10-ocram-ecc", 563 "altr,socfpga-a10-ocram-ecc"; 564 reg = <0xff8cc000 0x100>; 565 altr,ecc-parent = <&ocram>; 566 interrupts = <1 4>; 567 }; 568 569 usb0-ecc@ff8c4000 { 570 compatible = "altr,socfpga-s10-usb-ecc", 571 "altr,socfpga-usb-ecc"; 572 reg = <0xff8c4000 0x100>; 573 altr,ecc-parent = <&usb0>; 574 interrupts = <2 4>; 575 }; 576 577 emac0-rx-ecc@ff8c0000 { 578 compatible = "altr,socfpga-s10-eth-mac-ecc", 579 "altr,socfpga-eth-mac-ecc"; 580 reg = <0xff8c0000 0x100>; 581 altr,ecc-parent = <&gmac0>; 582 interrupts = <4 4>; 583 }; 584 585 emac0-tx-ecc@ff8c0400 { 586 compatible = "altr,socfpga-s10-eth-mac-ecc", 587 "altr,socfpga-eth-mac-ecc"; 588 reg = <0xff8c0400 0x100>; 589 altr,ecc-parent = <&gmac0>; 590 interrupts = <5 4>; 591 }; 592 593 sdmmca-ecc@ff8c8c00 { 594 compatible = "altr,socfpga-s10-sdmmc-ecc", 595 "altr,socfpga-sdmmc-ecc"; 596 reg = <0xff8c8c00 0x100>; 597 altr,ecc-parent = <&mmc>; 598 interrupts = <14 4>, 599 <15 4>; 600 }; 601 }; 602 603 qspi: spi@ff8d2000 { 604 compatible = "cdns,qspi-nor"; 605 #address-cells = <1>; 606 #size-cells = <0>; 607 reg = <0xff8d2000 0x100>, 608 <0xff900000 0x100000>; 609 interrupts = <0 3 4>; 610 cdns,fifo-depth = <128>; 611 cdns,fifo-width = <4>; 612 cdns,trigger-address = <0x00000000>; 613 clocks = <&qspi_clk>; 614 615 status = "disabled"; 616 }; 617 618 firmware { 619 svc { 620 compatible = "intel,agilex-svc"; 621 method = "smc"; 622 memory-region = <&service_reserved>; 623 624 fpga_mgr: fpga-mgr { 625 compatible = "intel,agilex-soc-fpga-mgr"; 626 }; 627 }; 628 }; 629 }; 630}; 631