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68ecb5c1 |
| 13-Sep-2018 |
Rob Herring <robh@kernel.org> |
arm64: dts: meson: Fix erroneous SPI bus warnings
dtc has new checks for SPI buses. The meson dts files have a node named spi' which causes false positive warnings. As the node is a pinctrl child no
arm64: dts: meson: Fix erroneous SPI bus warnings
dtc has new checks for SPI buses. The meson dts files have a node named spi' which causes false positive warnings. As the node is a pinctrl child node, change the node name to be 'spi-pins' to fix the warnings.
arch/arm64/boot/dts/amlogic/meson-gxbb-nanopi-k2.dtb: Warning (spi_bus_bridge): /soc/periphs@c8834000/pinctrl@4b0/spi: incorrect #address-cells for SPI bus
Cc: Carlo Caione <carlo@caione.org> Cc: Kevin Hilman <khilman@baylibre.com> Cc: linux-amlogic@lists.infradead.org Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
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48e21ded |
| 07-Jun-2018 |
Kevin Hilman <khilman@baylibre.com> |
ARM64: dts: meson-gx: fix ATF reserved memory region
Vendor firmware/uboot has different reserved regions depending on firmware version, but current codebase reserves the same regions on GXL and GXB
ARM64: dts: meson-gx: fix ATF reserved memory region
Vendor firmware/uboot has different reserved regions depending on firmware version, but current codebase reserves the same regions on GXL and GXBB, so move the additional reserved memory region to common .dtsi.
Found when putting a recent vendor u-boot on meson-gxbb-p200.
Suggested-by: Neil Armstrong <narmstrong@baylibre.com> Cc: stable@vger.kernel.org Signed-off-by: Kevin Hilman <khilman@baylibre.com>
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9adda353 |
| 27-Mar-2018 |
Yixun Lan <yixun.lan@amlogic.com> |
ARM64: dts: meson: fix clock source of the pclk for UART_AO
>From the hardware perspective, the actual pclk of the AO uarts is the corresponding clkc_ao uart gate, not the main clock controller clk8
ARM64: dts: meson: fix clock source of the pclk for UART_AO
>From the hardware perspective, the actual pclk of the AO uarts is the corresponding clkc_ao uart gate, not the main clock controller clk81. This was not problem so far, because the uart_gate had the CLK_IGNORE_UNUSED flag, which kept the gate open.
We plan to remove the CLK_IGNORE_UNUSED flag in another patch, but before doing that, we need to fix the clock in the DTS file.
Signed-off-by: Yixun Lan <yixun.lan@amlogic.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
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098e5303 |
| 26-Apr-2018 |
Jerome Brunet <jbrunet@baylibre.com> |
ARM64: dts: meson: add MMC resets
Add reset lines to the mmc controllers of the meson gx and axg SoCs
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylib
ARM64: dts: meson: add MMC resets
Add reset lines to the mmc controllers of the meson gx and axg SoCs
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
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57ee9767 |
| 15-Mar-2018 |
Jerome Brunet <jbrunet@baylibre.com> |
ARM64: dts: meson-gx: fix gxl clock controller compatible
There are a few differences between the gxbb and gxl clock controllers which makes them incompatible. The hdmi, gp0 and fixed pll are differ
ARM64: dts: meson-gx: fix gxl clock controller compatible
There are a few differences between the gxbb and gxl clock controllers which makes them incompatible. The hdmi, gp0 and fixed pll are different. The rate of these plls reported by gxbb driver on a gxl device would be wrong.
Remove the gxbb compatible from the gxl clock controller node so only the correct driver is matched.
Fixes: 973fbd55b53c ("ARM64: dts: meson-gxl: Add clock nodes") Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
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6f95c8cd |
| 15-Mar-2018 |
Jerome Brunet <jbrunet@baylibre.com> |
ARM64: dts: meson-gx: sysctrl is the parent of the clock controller
The parent of the meson-gx clock controller should be the hhi system controller, not the HIU bus. This way, the HHI register regio
ARM64: dts: meson-gx: sysctrl is the parent of the clock controller
The parent of the meson-gx clock controller should be the hhi system controller, not the HIU bus. This way, the HHI register region can be used safely by multiple drivers
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
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8aec5fc1 |
| 26-Mar-2018 |
Martin Blumenstingl <martin.blumenstingl@googlemail.com> |
ARM64: dts: meson-gxl: add USB host support
This adds USB host support to the Meson GXL SoC. A dwc3 controller is used for host-mode, while a dwc2 controller (not added in this patch because I could
ARM64: dts: meson-gxl: add USB host support
This adds USB host support to the Meson GXL SoC. A dwc3 controller is used for host-mode, while a dwc2 controller (not added in this patch because I could not get it working) is used for device-mode only.
The dwc3 controller's internal roothub has two USB2 ports enabled but no USB3 port. Each of the ports is supplied by a separate PHY. The USB pins are connected to the SoC's USBHOST_A and USBOTG_B pins. Due to the way the roothub works internally the USB PHYs are left enabled. When the dwc3 controller is disabled the PHY is never powered on so it does not draw any extra power. However, when the dwc3 host controller is enabled then all PHYs also have to be enabled, otherwise USB devices will not be detected (regardless of whether they are plugged into an enabled port or not). This means that only the dwc3 controller has to be enabled on boards with USB support (instead of requiring all boards to enable the PHYs additionally with the chance of forgetting to enable one and breaking all other ports with that as well).
This also adds the USB3 PHY which currently only does some basic initialization. That however is required because without it high-speed devices (like USB thumb drives) do not work on some devices (probably because the bootloader does not configure the USB3 PHY registers).
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
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#
114abfe1 |
| 27-Feb-2018 |
Neil Armstrong <narmstrong@baylibre.com> |
ARM64: dts: amlogic: Convert to new-style SPDX license identifiers
Move the SPDX-License-Identifier lines to the top and drop the license splat.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.c
ARM64: dts: amlogic: Convert to new-style SPDX license identifiers
Move the SPDX-License-Identifier lines to the top and drop the license splat.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
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2363ec93 |
| 18-Dec-2017 |
Jerome Brunet <jbrunet@baylibre.com> |
ARM64: dts: meson-gxl: add internal ethernet PHY irq
Add the interrupt of the internal ethernet PHY
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre
ARM64: dts: meson-gxl: add internal ethernet PHY irq
Add the interrupt of the internal ethernet PHY
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
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#
39005e56 |
| 04-Dec-2017 |
Neil Armstrong <narmstrong@baylibre.com> |
ARM64: dts: meson-gx: fix UART pclk clock name
The clock-names for pclk was wrongly set to "core", but the bindings specifies "pclk". This was not cathed until the legacy non-documented bindings wer
ARM64: dts: meson-gx: fix UART pclk clock name
The clock-names for pclk was wrongly set to "core", but the bindings specifies "pclk". This was not cathed until the legacy non-documented bindings were removed.
Reported-by: Andreas Färber <afaerber@suse.de> Fixes: f72d6f6037b7 ("ARM64: dts: meson-gx: use stable UART bindings with correct gate clock") Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
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#
e102da49 |
| 16-Nov-2017 |
Xingyu Chen <xingyu.chen@amlogic.com> |
ARM64: dts: meson: drop "sana" clock from SAR ADC
The SAR ADC modules doesn't require The "sana" clock.
Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Singed-off-by: Xingyu Chen
ARM64: dts: meson: drop "sana" clock from SAR ADC
The SAR ADC modules doesn't require The "sana" clock.
Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Singed-off-by: Xingyu Chen <xingyu.chen@amlogic.com> Signed-off-by: Yixun Lan <yixun.lan@amlogic.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
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74d1c6e9 |
| 20-Nov-2017 |
Neil Armstrong <narmstrong@baylibre.com> |
ARM64: dts: meson-gx: add VPU power domain
This patch adds support for the VPU Power Domain nodes, and attaches the VPU power domain to the VPU node.
Signed-off-by: Neil Armstrong <narmstrong@bayli
ARM64: dts: meson-gx: add VPU power domain
This patch adds support for the VPU Power Domain nodes, and attaches the VPU power domain to the VPU node.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
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9dbb56ea |
| 19-Oct-2017 |
Jerome Brunet <jbrunet@baylibre.com> |
ARM64: dts: meson-gx: add gpio interrupt controller
Add gpio interrupt controller to Amlogic GX family SoCs
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Reviewed-by: Neil Armstrong <narmstro
ARM64: dts: meson-gx: add gpio interrupt controller
Add gpio interrupt controller to Amlogic GX family SoCs
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
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4ee8e51b |
| 11-Oct-2017 |
Neil Armstrong <narmstrong@baylibre.com> |
ARM64: dts: meson-gxl: Add alternate ARM Trusted Firmware reserved memory zone
This year, Amlogic updated the ARM Trusted Firmware reserved memory mapping for Meson GXL SoCs and products sold since
ARM64: dts: meson-gxl: Add alternate ARM Trusted Firmware reserved memory zone
This year, Amlogic updated the ARM Trusted Firmware reserved memory mapping for Meson GXL SoCs and products sold since May 2017 uses this alternate reserved memory mapping. But products had been sold using the previous mapping.
This issue has been explained in [1] and a dynamic solution is yet to be found to avoid loosing another 3Mbytes of reservable memory.
In the meantime, this patch adds this alternate memory zone only for the GXL and GXM SoCs since GXBB based new products stopped earlier.
[1] http://lists.infradead.org/pipermail/linux-amlogic/2017-October/004860.html
Fixes: bba8e3f42736 ("ARM64: dts: meson-gx: Add firmware reserved memory zones") Reported-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
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#
ab36be66 |
| 03-Oct-2017 |
Neil Armstrong <narmstrong@baylibre.com> |
ARM64: dts: meson-gxl: Take eMMC data strobe out of eMMC pins
Since the Data Strobe pin is optional, take it out of the default eMMC pins and add a separate entry.
Signed-off-by: Neil Armstrong <na
ARM64: dts: meson-gxl: Take eMMC data strobe out of eMMC pins
Since the Data Strobe pin is optional, take it out of the default eMMC pins and add a separate entry.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Tested-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
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#
7dbe78e5 |
| 21-Sep-2017 |
Jerome Brunet <jbrunet@baylibre.com> |
ARM64: dts: meson-gx: adjust gpio-ranges for TEST_N
TEST_N has moved from the EE controller to the AO controller so the gpio-ranges need to adjusted for it
Signed-off-by: Jerome Brunet <jbrunet@bay
ARM64: dts: meson-gx: adjust gpio-ranges for TEST_N
TEST_N has moved from the EE controller to the AO controller so the gpio-ranges need to adjusted for it
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
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352f72b4 |
| 21-Sep-2017 |
Jerome Brunet <jbrunet@baylibre.com> |
ARM64: dts: meson-gx: remove gpio offset
Remove pin offset on the EE controller. Meson pinctrl no longer has this quirk
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Kevin Hilm
ARM64: dts: meson-gx: remove gpio offset
Remove pin offset on the EE controller. Meson pinctrl no longer has this quirk
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
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67e7607f |
| 31-Aug-2017 |
Jerome Brunet <jbrunet@baylibre.com> |
ARM64: dts: meson: add mmc clk gate pins
Add the pinctrl to switch mmc clk pins in gpio (pulled down) mode. This is necessary to be able to gate the clk outside of the SoC while keeping it running i
ARM64: dts: meson: add mmc clk gate pins
Add the pinctrl to switch mmc clk pins in gpio (pulled down) mode. This is necessary to be able to gate the clk outside of the SoC while keeping it running in the controller
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
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#
50662499 |
| 31-Aug-2017 |
Jerome Brunet <jbrunet@baylibre.com> |
ARM64: dts: meson-gx: Use correct mmc clock source 0
Now that the clock source 0 is properly described in the CCF, use it instead of assuming the default value (xtal)
Signed-off-by: Jerome Brunet <
ARM64: dts: meson-gx: Use correct mmc clock source 0
Now that the clock source 0 is properly described in the CCF, use it instead of assuming the default value (xtal)
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
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#
b16c71c9 |
| 04-Aug-2017 |
Neil Armstrong <narmstrong@baylibre.com> |
ARM64: dts: meson-gx: Add AO CEC nodes
This patch adds the AO CEC node in all the HDMI enabled boards DTS.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilm
ARM64: dts: meson-gx: Add AO CEC nodes
This patch adds the AO CEC node in all the HDMI enabled boards DTS.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
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#
7fd2c355 |
| 04-Aug-2017 |
Neil Armstrong <narmstrong@baylibre.com> |
ARM64: dts: meson-gx: update AO clkc to new bindings
The AO clkc needs to be updated to new bindings with an system control parent node and moving the clkc node as subnode.
Also adds the SoC specif
ARM64: dts: meson-gx: update AO clkc to new bindings
The AO clkc needs to be updated to new bindings with an system control parent node and moving the clkc node as subnode.
Also adds the SoC specific compatible following the bindings requirements.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
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#
f72d6f60 |
| 21-Jun-2017 |
Helmut Klein <hgkr.klein@gmail.com> |
ARM64: dts: meson-gx: use stable UART bindings with correct gate clock
This patch switches to the stable UART bindings but also add the correct gate clock to the non-AO UART nodes for GXBB and GXL S
ARM64: dts: meson-gx: use stable UART bindings with correct gate clock
This patch switches to the stable UART bindings but also add the correct gate clock to the non-AO UART nodes for GXBB and GXL SoCs.
Acked-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Helmut Klein <hgkr.klein@gmail.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
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#
fa808631 |
| 29-May-2017 |
Neil Armstrong <narmstrong@baylibre.com> |
ARM64: dts: meson-gx: Add SPICC nodes
Add nodes for the SPICC controller on GX common dtsi, GXBB and GXL dtsi files.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hil
ARM64: dts: meson-gx: Add SPICC nodes
Add nodes for the SPICC controller on GX common dtsi, GXBB and GXL dtsi files.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
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85b2e743 |
| 24-May-2017 |
Neil Armstrong <narmstrong@baylibre.com> |
ARM64: dts: meson-gxl: Add SPI pinctrl nodes
This patch adds the SPICC Controller pins nodes for Amlogic GXL SoCs.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilma
ARM64: dts: meson-gxl: Add SPI pinctrl nodes
This patch adds the SPICC Controller pins nodes for Amlogic GXL SoCs.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
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#
44ddadc3 |
| 24-May-2017 |
Neil Armstrong <narmstrong@baylibre.com> |
ARM64: dts: meson-gxl: Add Ethernet PHY LEDS pins nodes
The Amlogic Meson GXL SoCs embeds an 10/100 Ethernet PHY, this patchs adds the Link and Activity LEDs signals pins nodes.
Signed-off-by: Neil
ARM64: dts: meson-gxl: Add Ethernet PHY LEDS pins nodes
The Amlogic Meson GXL SoCs embeds an 10/100 Ethernet PHY, this patchs adds the Link and Activity LEDs signals pins nodes.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
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