1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (c) 2016 Endless Computers, Inc.
4 * Author: Carlo Caione <carlo@endlessm.com>
5 */
6
7#include "meson-gx.dtsi"
8#include <dt-bindings/clock/gxbb-clkc.h>
9#include <dt-bindings/clock/gxbb-aoclkc.h>
10#include <dt-bindings/gpio/meson-gxl-gpio.h>
11#include <dt-bindings/reset/amlogic,meson-gxbb-reset.h>
12
13/ {
14	compatible = "amlogic,meson-gxl";
15
16	reserved-memory {
17		/* Alternate 3 MiB reserved for ARM Trusted Firmware (BL31) */
18		secmon_reserved_alt: secmon@5000000 {
19			reg = <0x0 0x05000000 0x0 0x300000>;
20			no-map;
21		};
22	};
23};
24
25&ethmac {
26	reg = <0x0 0xc9410000 0x0 0x10000
27	       0x0 0xc8834540 0x0 0x4>;
28
29	clocks = <&clkc CLKID_ETH>,
30		 <&clkc CLKID_FCLK_DIV2>,
31		 <&clkc CLKID_MPLL2>;
32	clock-names = "stmmaceth", "clkin0", "clkin1";
33
34	mdio0: mdio {
35		#address-cells = <1>;
36		#size-cells = <0>;
37		compatible = "snps,dwmac-mdio";
38	};
39};
40
41&aobus {
42	pinctrl_aobus: pinctrl@14 {
43		compatible = "amlogic,meson-gxl-aobus-pinctrl";
44		#address-cells = <2>;
45		#size-cells = <2>;
46		ranges;
47
48		gpio_ao: bank@14 {
49			reg = <0x0 0x00014 0x0 0x8>,
50			      <0x0 0x0002c 0x0 0x4>,
51			      <0x0 0x00024 0x0 0x8>;
52			reg-names = "mux", "pull", "gpio";
53			gpio-controller;
54			#gpio-cells = <2>;
55			gpio-ranges = <&pinctrl_aobus 0 0 14>;
56		};
57
58		uart_ao_a_pins: uart_ao_a {
59			mux {
60				groups = "uart_tx_ao_a", "uart_rx_ao_a";
61				function = "uart_ao";
62			};
63		};
64
65		uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts {
66			mux {
67				groups = "uart_cts_ao_a",
68				       "uart_rts_ao_a";
69				function = "uart_ao";
70			};
71		};
72
73		uart_ao_b_pins: uart_ao_b {
74			mux {
75				groups = "uart_tx_ao_b", "uart_rx_ao_b";
76				function = "uart_ao_b";
77			};
78		};
79
80		uart_ao_b_0_1_pins: uart_ao_b_0_1 {
81			mux {
82				groups = "uart_tx_ao_b_0", "uart_rx_ao_b_1";
83				function = "uart_ao_b";
84			};
85		};
86
87		uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts {
88			mux {
89				groups = "uart_cts_ao_b",
90				       "uart_rts_ao_b";
91				function = "uart_ao_b";
92			};
93		};
94
95		remote_input_ao_pins: remote_input_ao {
96			mux {
97				groups = "remote_input_ao";
98				function = "remote_input_ao";
99			};
100		};
101
102		i2c_ao_pins: i2c_ao {
103			mux {
104				groups = "i2c_sck_ao",
105				       "i2c_sda_ao";
106				function = "i2c_ao";
107			};
108		};
109
110		pwm_ao_a_3_pins: pwm_ao_a_3 {
111			mux {
112				groups = "pwm_ao_a_3";
113				function = "pwm_ao_a";
114			};
115		};
116
117		pwm_ao_a_8_pins: pwm_ao_a_8 {
118			mux {
119				groups = "pwm_ao_a_8";
120				function = "pwm_ao_a";
121			};
122		};
123
124		pwm_ao_b_pins: pwm_ao_b {
125			mux {
126				groups = "pwm_ao_b";
127				function = "pwm_ao_b";
128			};
129		};
130
131		pwm_ao_b_6_pins: pwm_ao_b_6 {
132			mux {
133				groups = "pwm_ao_b_6";
134				function = "pwm_ao_b";
135			};
136		};
137
138		i2s_out_ch23_ao_pins: i2s_out_ch23_ao {
139			mux {
140				groups = "i2s_out_ch23_ao";
141				function = "i2s_out_ao";
142			};
143		};
144
145		i2s_out_ch45_ao_pins: i2s_out_ch45_ao {
146			mux {
147				groups = "i2s_out_ch45_ao";
148				function = "i2s_out_ao";
149			};
150		};
151
152		spdif_out_ao_6_pins: spdif_out_ao_6 {
153			mux {
154				groups = "spdif_out_ao_6";
155				function = "spdif_out_ao";
156			};
157		};
158
159		spdif_out_ao_9_pins: spdif_out_ao_9 {
160			mux {
161				groups = "spdif_out_ao_9";
162				function = "spdif_out_ao";
163			};
164		};
165
166		ao_cec_pins: ao_cec {
167			mux {
168				groups = "ao_cec";
169				function = "cec_ao";
170			};
171		};
172
173		ee_cec_pins: ee_cec {
174			mux {
175				groups = "ee_cec";
176				function = "cec_ao";
177			};
178		};
179	};
180};
181
182&cec_AO {
183	clocks = <&clkc_AO CLKID_AO_CEC_32K>;
184	clock-names = "core";
185};
186
187&clkc_AO {
188	compatible = "amlogic,meson-gxl-aoclkc", "amlogic,meson-gx-aoclkc";
189};
190
191&gpio_intc {
192	compatible = "amlogic,meson-gpio-intc",
193		     "amlogic,meson-gxl-gpio-intc";
194	status = "okay";
195};
196
197&hdmi_tx {
198	compatible = "amlogic,meson-gxl-dw-hdmi", "amlogic,meson-gx-dw-hdmi";
199	resets = <&reset RESET_HDMITX_CAPB3>,
200		 <&reset RESET_HDMI_SYSTEM_RESET>,
201		 <&reset RESET_HDMI_TX>;
202	reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy";
203	clocks = <&clkc CLKID_HDMI_PCLK>,
204		 <&clkc CLKID_CLK81>,
205		 <&clkc CLKID_GCLK_VENCI_INT0>;
206	clock-names = "isfr", "iahb", "venci";
207};
208
209&hiubus {
210	clkc: clock-controller@0 {
211		compatible = "amlogic,gxl-clkc", "amlogic,gxbb-clkc";
212		#clock-cells = <1>;
213		reg = <0x0 0x0 0x0 0x3db>;
214	};
215};
216
217&i2c_A {
218	clocks = <&clkc CLKID_I2C>;
219};
220
221&i2c_AO {
222	clocks = <&clkc CLKID_AO_I2C>;
223};
224
225&i2c_B {
226	clocks = <&clkc CLKID_I2C>;
227};
228
229&i2c_C {
230	clocks = <&clkc CLKID_I2C>;
231};
232
233&periphs {
234	pinctrl_periphs: pinctrl@4b0 {
235		compatible = "amlogic,meson-gxl-periphs-pinctrl";
236		#address-cells = <2>;
237		#size-cells = <2>;
238		ranges;
239
240		gpio: bank@4b0 {
241			reg = <0x0 0x004b0 0x0 0x28>,
242			      <0x0 0x004e8 0x0 0x14>,
243			      <0x0 0x00520 0x0 0x14>,
244			      <0x0 0x00430 0x0 0x40>;
245			reg-names = "mux", "pull", "pull-enable", "gpio";
246			gpio-controller;
247			#gpio-cells = <2>;
248			gpio-ranges = <&pinctrl_periphs 0 0 100>;
249		};
250
251		emmc_pins: emmc {
252			mux {
253				groups = "emmc_nand_d07",
254				       "emmc_cmd",
255				       "emmc_clk";
256				function = "emmc";
257			};
258		};
259
260		emmc_ds_pins: emmc-ds {
261			mux {
262				groups = "emmc_ds";
263				function = "emmc";
264			};
265		};
266
267		emmc_clk_gate_pins: emmc_clk_gate {
268			mux {
269				groups = "BOOT_8";
270				function = "gpio_periphs";
271			};
272			cfg-pull-down {
273				pins = "BOOT_8";
274				bias-pull-down;
275			};
276		};
277
278		nor_pins: nor {
279			mux {
280				groups = "nor_d",
281				       "nor_q",
282				       "nor_c",
283				       "nor_cs";
284				function = "nor";
285			};
286		};
287
288		spi_pins: spi {
289			mux {
290				groups = "spi_miso",
291					"spi_mosi",
292					"spi_sclk";
293				function = "spi";
294			};
295		};
296
297		spi_ss0_pins: spi-ss0 {
298			mux {
299				groups = "spi_ss0";
300				function = "spi";
301			};
302		};
303
304		sdcard_pins: sdcard {
305			mux {
306				groups = "sdcard_d0",
307				       "sdcard_d1",
308				       "sdcard_d2",
309				       "sdcard_d3",
310				       "sdcard_cmd",
311				       "sdcard_clk";
312				function = "sdcard";
313			};
314		};
315
316		sdcard_clk_gate_pins: sdcard_clk_gate {
317			mux {
318				groups = "CARD_2";
319				function = "gpio_periphs";
320			};
321			cfg-pull-down {
322				pins = "CARD_2";
323				bias-pull-down;
324			};
325		};
326
327		sdio_pins: sdio {
328			mux {
329				groups = "sdio_d0",
330				       "sdio_d1",
331				       "sdio_d2",
332				       "sdio_d3",
333				       "sdio_cmd",
334				       "sdio_clk";
335				function = "sdio";
336			};
337		};
338
339		sdio_clk_gate_pins: sdio_clk_gate {
340			mux {
341				groups = "GPIOX_4";
342				function = "gpio_periphs";
343			};
344			cfg-pull-down {
345				pins = "GPIOX_4";
346				bias-pull-down;
347			};
348		};
349
350		sdio_irq_pins: sdio_irq {
351			mux {
352				groups = "sdio_irq";
353				function = "sdio";
354			};
355		};
356
357		uart_a_pins: uart_a {
358			mux {
359				groups = "uart_tx_a",
360				       "uart_rx_a";
361				function = "uart_a";
362			};
363		};
364
365		uart_a_cts_rts_pins: uart_a_cts_rts {
366			mux {
367				groups = "uart_cts_a",
368				       "uart_rts_a";
369				function = "uart_a";
370			};
371		};
372
373		uart_b_pins: uart_b {
374			mux {
375				groups = "uart_tx_b",
376				       "uart_rx_b";
377				function = "uart_b";
378			};
379		};
380
381		uart_b_cts_rts_pins: uart_b_cts_rts {
382			mux {
383				groups = "uart_cts_b",
384				       "uart_rts_b";
385				function = "uart_b";
386			};
387		};
388
389		uart_c_pins: uart_c {
390			mux {
391				groups = "uart_tx_c",
392				       "uart_rx_c";
393				function = "uart_c";
394			};
395		};
396
397		uart_c_cts_rts_pins: uart_c_cts_rts {
398			mux {
399				groups = "uart_cts_c",
400				       "uart_rts_c";
401				function = "uart_c";
402			};
403		};
404
405		i2c_a_pins: i2c_a {
406			mux {
407				groups = "i2c_sck_a",
408				     "i2c_sda_a";
409				function = "i2c_a";
410			};
411		};
412
413		i2c_b_pins: i2c_b {
414			mux {
415				groups = "i2c_sck_b",
416				      "i2c_sda_b";
417				function = "i2c_b";
418			};
419		};
420
421		i2c_c_pins: i2c_c {
422			mux {
423				groups = "i2c_sck_c",
424				      "i2c_sda_c";
425				function = "i2c_c";
426			};
427		};
428
429		eth_pins: eth_c {
430			mux {
431				groups = "eth_mdio",
432				       "eth_mdc",
433				       "eth_clk_rx_clk",
434				       "eth_rx_dv",
435				       "eth_rxd0",
436				       "eth_rxd1",
437				       "eth_rxd2",
438				       "eth_rxd3",
439				       "eth_rgmii_tx_clk",
440				       "eth_tx_en",
441				       "eth_txd0",
442				       "eth_txd1",
443				       "eth_txd2",
444				       "eth_txd3";
445				function = "eth";
446			};
447		};
448
449		eth_link_led_pins: eth_link_led {
450			mux {
451				groups = "eth_link_led";
452				function = "eth_led";
453			};
454		};
455
456		eth_act_led_pins: eth_act_led {
457			mux {
458				groups = "eth_act_led";
459				function = "eth_led";
460			};
461		};
462
463		pwm_a_pins: pwm_a {
464			mux {
465				groups = "pwm_a";
466				function = "pwm_a";
467			};
468		};
469
470		pwm_b_pins: pwm_b {
471			mux {
472				groups = "pwm_b";
473				function = "pwm_b";
474			};
475		};
476
477		pwm_c_pins: pwm_c {
478			mux {
479				groups = "pwm_c";
480				function = "pwm_c";
481			};
482		};
483
484		pwm_d_pins: pwm_d {
485			mux {
486				groups = "pwm_d";
487				function = "pwm_d";
488			};
489		};
490
491		pwm_e_pins: pwm_e {
492			mux {
493				groups = "pwm_e";
494				function = "pwm_e";
495			};
496		};
497
498		pwm_f_clk_pins: pwm_f_clk {
499			mux {
500				groups = "pwm_f_clk";
501				function = "pwm_f";
502			};
503		};
504
505		pwm_f_x_pins: pwm_f_x {
506			mux {
507				groups = "pwm_f_x";
508				function = "pwm_f";
509			};
510		};
511
512		hdmi_hpd_pins: hdmi_hpd {
513			mux {
514				groups = "hdmi_hpd";
515				function = "hdmi_hpd";
516			};
517		};
518
519		hdmi_i2c_pins: hdmi_i2c {
520			mux {
521				groups = "hdmi_sda", "hdmi_scl";
522				function = "hdmi_i2c";
523			};
524		};
525
526		i2s_am_clk_pins: i2s_am_clk {
527			mux {
528				groups = "i2s_am_clk";
529				function = "i2s_out";
530			};
531		};
532
533		i2s_out_ao_clk_pins: i2s_out_ao_clk {
534			mux {
535				groups = "i2s_out_ao_clk";
536				function = "i2s_out";
537			};
538		};
539
540		i2s_out_lr_clk_pins: i2s_out_lr_clk {
541			mux {
542				groups = "i2s_out_lr_clk";
543				function = "i2s_out";
544			};
545		};
546
547		i2s_out_ch01_pins: i2s_out_ch01 {
548			mux {
549				groups = "i2s_out_ch01";
550				function = "i2s_out";
551			};
552		};
553		i2sout_ch23_z_pins: i2sout_ch23_z {
554			mux {
555				groups = "i2sout_ch23_z";
556				function = "i2s_out";
557			};
558		};
559
560		i2sout_ch45_z_pins: i2sout_ch45_z {
561			mux {
562				groups = "i2sout_ch45_z";
563				function = "i2s_out";
564			};
565		};
566
567		i2sout_ch67_z_pins: i2sout_ch67_z {
568			mux {
569				groups = "i2sout_ch67_z";
570				function = "i2s_out";
571			};
572		};
573
574		spdif_out_h_pins: spdif_out_ao_h {
575			mux {
576				groups = "spdif_out_h";
577				function = "spdif_out";
578			};
579		};
580	};
581
582	eth-phy-mux {
583		compatible = "mdio-mux-mmioreg", "mdio-mux";
584		#address-cells = <1>;
585		#size-cells = <0>;
586		reg = <0x0 0x55c 0x0 0x4>;
587		mux-mask = <0xffffffff>;
588		mdio-parent-bus = <&mdio0>;
589
590		internal_mdio: mdio@e40908ff {
591			reg = <0xe40908ff>;
592			#address-cells = <1>;
593			#size-cells = <0>;
594
595			internal_phy: ethernet-phy@8 {
596				compatible = "ethernet-phy-id0181.4400", "ethernet-phy-ieee802.3-c22";
597				interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
598				reg = <8>;
599				max-speed = <100>;
600			};
601		};
602
603		external_mdio: mdio@2009087f {
604			reg = <0x2009087f>;
605			#address-cells = <1>;
606			#size-cells = <0>;
607		};
608	};
609};
610
611&pwrc_vpu {
612	resets = <&reset RESET_VIU>,
613		 <&reset RESET_VENC>,
614		 <&reset RESET_VCBUS>,
615		 <&reset RESET_BT656>,
616		 <&reset RESET_DVIN_RESET>,
617		 <&reset RESET_RDMA>,
618		 <&reset RESET_VENCI>,
619		 <&reset RESET_VENCP>,
620		 <&reset RESET_VDAC>,
621		 <&reset RESET_VDI6>,
622		 <&reset RESET_VENCL>,
623		 <&reset RESET_VID_LOCK>;
624	clocks = <&clkc CLKID_VPU>,
625	         <&clkc CLKID_VAPB>;
626	clock-names = "vpu", "vapb";
627	/*
628	 * VPU clocking is provided by two identical clock paths
629	 * VPU_0 and VPU_1 muxed to a single clock by a glitch
630	 * free mux to safely change frequency while running.
631	 * Same for VAPB but with a final gate after the glitch free mux.
632	 */
633	assigned-clocks = <&clkc CLKID_VPU_0_SEL>,
634			  <&clkc CLKID_VPU_0>,
635			  <&clkc CLKID_VPU>, /* Glitch free mux */
636			  <&clkc CLKID_VAPB_0_SEL>,
637			  <&clkc CLKID_VAPB_0>,
638			  <&clkc CLKID_VAPB_SEL>; /* Glitch free mux */
639	assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
640				 <0>, /* Do Nothing */
641				 <&clkc CLKID_VPU_0>,
642				 <&clkc CLKID_FCLK_DIV4>,
643				 <0>, /* Do Nothing */
644				 <&clkc CLKID_VAPB_0>;
645	assigned-clock-rates = <0>, /* Do Nothing */
646			       <666666666>,
647			       <0>, /* Do Nothing */
648			       <0>, /* Do Nothing */
649			       <250000000>,
650			       <0>; /* Do Nothing */
651};
652
653&saradc {
654	compatible = "amlogic,meson-gxl-saradc", "amlogic,meson-saradc";
655	clocks = <&xtal>,
656		 <&clkc CLKID_SAR_ADC>,
657		 <&clkc CLKID_SAR_ADC_CLK>,
658		 <&clkc CLKID_SAR_ADC_SEL>;
659	clock-names = "clkin", "core", "adc_clk", "adc_sel";
660};
661
662&sd_emmc_a {
663	clocks = <&clkc CLKID_SD_EMMC_A>,
664		 <&clkc CLKID_SD_EMMC_A_CLK0>,
665		 <&clkc CLKID_FCLK_DIV2>;
666	clock-names = "core", "clkin0", "clkin1";
667};
668
669&sd_emmc_b {
670	clocks = <&clkc CLKID_SD_EMMC_B>,
671		 <&clkc CLKID_SD_EMMC_B_CLK0>,
672		 <&clkc CLKID_FCLK_DIV2>;
673       clock-names = "core", "clkin0", "clkin1";
674};
675
676&sd_emmc_c {
677	clocks = <&clkc CLKID_SD_EMMC_C>,
678		 <&clkc CLKID_SD_EMMC_C_CLK0>,
679		 <&clkc CLKID_FCLK_DIV2>;
680	clock-names = "core", "clkin0", "clkin1";
681};
682
683&spicc {
684	clocks = <&clkc CLKID_SPICC>;
685	clock-names = "core";
686	resets = <&reset RESET_PERIPHS_SPICC>;
687	num-cs = <1>;
688};
689
690&spifc {
691	clocks = <&clkc CLKID_SPI>;
692};
693
694&uart_A {
695	clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
696	clock-names = "xtal", "pclk", "baud";
697};
698
699&uart_AO {
700	clocks = <&xtal>, <&clkc CLKID_CLK81>, <&xtal>;
701	clock-names = "xtal", "pclk", "baud";
702};
703
704&uart_AO_B {
705	clocks = <&xtal>, <&clkc CLKID_CLK81>, <&xtal>;
706	clock-names = "xtal", "pclk", "baud";
707};
708
709&uart_B {
710	clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
711	clock-names = "xtal", "pclk", "baud";
712};
713
714&uart_C {
715	clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>;
716	clock-names = "xtal", "pclk", "baud";
717};
718
719&vpu {
720	compatible = "amlogic,meson-gxl-vpu", "amlogic,meson-gx-vpu";
721	power-domains = <&pwrc_vpu>;
722};
723