1/*
2 * Copyright (c) 2016 Endless Computers, Inc.
3 * Author: Carlo Caione <carlo@endlessm.com>
4 *
5 * This file is dual-licensed: you can use it either under the terms
6 * of the GPL or the X11 license, at your option. Note that this dual
7 * licensing only applies to this file, and not this project as a
8 * whole.
9 *
10 *  a) This library is free software; you can redistribute it and/or
11 *     modify it under the terms of the GNU General Public License as
12 *     published by the Free Software Foundation; either version 2 of the
13 *     License, or (at your option) any later version.
14 *
15 *     This library is distributed in the hope that it will be useful,
16 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
17 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
18 *     GNU General Public License for more details.
19 *
20 * Or, alternatively,
21 *
22 *  b) Permission is hereby granted, free of charge, to any person
23 *     obtaining a copy of this software and associated documentation
24 *     files (the "Software"), to deal in the Software without
25 *     restriction, including without limitation the rights to use,
26 *     copy, modify, merge, publish, distribute, sublicense, and/or
27 *     sell copies of the Software, and to permit persons to whom the
28 *     Software is furnished to do so, subject to the following
29 *     conditions:
30 *
31 *     The above copyright notice and this permission notice shall be
32 *     included in all copies or substantial portions of the Software.
33 *
34 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
35 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
36 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
37 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
38 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
39 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
40 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
41 *     OTHER DEALINGS IN THE SOFTWARE.
42 */
43
44#include "meson-gx.dtsi"
45#include <dt-bindings/clock/gxbb-clkc.h>
46#include <dt-bindings/gpio/meson-gxl-gpio.h>
47#include <dt-bindings/reset/amlogic,meson-gxbb-reset.h>
48
49/ {
50	compatible = "amlogic,meson-gxl";
51};
52
53&ethmac {
54	reg = <0x0 0xc9410000 0x0 0x10000
55	       0x0 0xc8834540 0x0 0x4>;
56
57	clocks = <&clkc CLKID_ETH>,
58		 <&clkc CLKID_FCLK_DIV2>,
59		 <&clkc CLKID_MPLL2>;
60	clock-names = "stmmaceth", "clkin0", "clkin1";
61
62	mdio0: mdio {
63		#address-cells = <1>;
64		#size-cells = <0>;
65		compatible = "snps,dwmac-mdio";
66	};
67};
68
69&aobus {
70	pinctrl_aobus: pinctrl@14 {
71		compatible = "amlogic,meson-gxl-aobus-pinctrl";
72		#address-cells = <2>;
73		#size-cells = <2>;
74		ranges;
75
76		gpio_ao: bank@14 {
77			reg = <0x0 0x00014 0x0 0x8>,
78			      <0x0 0x0002c 0x0 0x4>,
79			      <0x0 0x00024 0x0 0x8>;
80			reg-names = "mux", "pull", "gpio";
81			gpio-controller;
82			#gpio-cells = <2>;
83			gpio-ranges = <&pinctrl_aobus 0 0 14>;
84		};
85
86		uart_ao_a_pins: uart_ao_a {
87			mux {
88				groups = "uart_tx_ao_a", "uart_rx_ao_a";
89				function = "uart_ao";
90			};
91		};
92
93		uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts {
94			mux {
95				groups = "uart_cts_ao_a",
96				       "uart_rts_ao_a";
97				function = "uart_ao";
98			};
99		};
100
101		uart_ao_b_pins: uart_ao_b {
102			mux {
103				groups = "uart_tx_ao_b", "uart_rx_ao_b";
104				function = "uart_ao_b";
105			};
106		};
107
108		uart_ao_b_0_1_pins: uart_ao_b_0_1 {
109			mux {
110				groups = "uart_tx_ao_b_0", "uart_rx_ao_b_1";
111				function = "uart_ao_b";
112			};
113		};
114
115		uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts {
116			mux {
117				groups = "uart_cts_ao_b",
118				       "uart_rts_ao_b";
119				function = "uart_ao_b";
120			};
121		};
122
123		remote_input_ao_pins: remote_input_ao {
124			mux {
125				groups = "remote_input_ao";
126				function = "remote_input_ao";
127			};
128		};
129
130		i2c_ao_pins: i2c_ao {
131			mux {
132				groups = "i2c_sck_ao",
133				       "i2c_sda_ao";
134				function = "i2c_ao";
135			};
136		};
137
138		pwm_ao_a_3_pins: pwm_ao_a_3 {
139			mux {
140				groups = "pwm_ao_a_3";
141				function = "pwm_ao_a";
142			};
143		};
144
145		pwm_ao_a_8_pins: pwm_ao_a_8 {
146			mux {
147				groups = "pwm_ao_a_8";
148				function = "pwm_ao_a";
149			};
150		};
151
152		pwm_ao_b_pins: pwm_ao_b {
153			mux {
154				groups = "pwm_ao_b";
155				function = "pwm_ao_b";
156			};
157		};
158
159		pwm_ao_b_6_pins: pwm_ao_b_6 {
160			mux {
161				groups = "pwm_ao_b_6";
162				function = "pwm_ao_b";
163			};
164		};
165
166		i2s_out_ch23_ao_pins: i2s_out_ch23_ao {
167			mux {
168				groups = "i2s_out_ch23_ao";
169				function = "i2s_out_ao";
170			};
171		};
172
173		i2s_out_ch45_ao_pins: i2s_out_ch45_ao {
174			mux {
175				groups = "i2s_out_ch45_ao";
176				function = "i2s_out_ao";
177			};
178		};
179
180		spdif_out_ao_6_pins: spdif_out_ao_6 {
181			mux {
182				groups = "spdif_out_ao_6";
183				function = "spdif_out_ao";
184			};
185		};
186
187		spdif_out_ao_9_pins: spdif_out_ao_9 {
188			mux {
189				groups = "spdif_out_ao_9";
190				function = "spdif_out_ao";
191			};
192		};
193
194		ao_cec_pins: ao_cec {
195			mux {
196				groups = "ao_cec";
197				function = "cec_ao";
198			};
199		};
200
201		ee_cec_pins: ee_cec {
202			mux {
203				groups = "ee_cec";
204				function = "cec_ao";
205			};
206		};
207	};
208};
209
210&clkc_AO {
211	compatible = "amlogic,meson-gxl-aoclkc", "amlogic,meson-gx-aoclkc";
212};
213
214&hdmi_tx {
215	compatible = "amlogic,meson-gxl-dw-hdmi", "amlogic,meson-gx-dw-hdmi";
216	resets = <&reset RESET_HDMITX_CAPB3>,
217		 <&reset RESET_HDMI_SYSTEM_RESET>,
218		 <&reset RESET_HDMI_TX>;
219	reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy";
220	clocks = <&clkc CLKID_HDMI_PCLK>,
221		 <&clkc CLKID_CLK81>,
222		 <&clkc CLKID_GCLK_VENCI_INT0>;
223	clock-names = "isfr", "iahb", "venci";
224};
225
226&hiubus {
227	clkc: clock-controller@0 {
228		compatible = "amlogic,gxl-clkc", "amlogic,gxbb-clkc";
229		#clock-cells = <1>;
230		reg = <0x0 0x0 0x0 0x3db>;
231	};
232};
233
234&i2c_A {
235	clocks = <&clkc CLKID_I2C>;
236};
237
238&i2c_AO {
239	clocks = <&clkc CLKID_AO_I2C>;
240};
241
242&i2c_B {
243	clocks = <&clkc CLKID_I2C>;
244};
245
246&i2c_C {
247	clocks = <&clkc CLKID_I2C>;
248};
249
250&periphs {
251	pinctrl_periphs: pinctrl@4b0 {
252		compatible = "amlogic,meson-gxl-periphs-pinctrl";
253		#address-cells = <2>;
254		#size-cells = <2>;
255		ranges;
256
257		gpio: bank@4b0 {
258			reg = <0x0 0x004b0 0x0 0x28>,
259			      <0x0 0x004e8 0x0 0x14>,
260			      <0x0 0x00520 0x0 0x14>,
261			      <0x0 0x00430 0x0 0x40>;
262			reg-names = "mux", "pull", "pull-enable", "gpio";
263			gpio-controller;
264			#gpio-cells = <2>;
265			gpio-ranges = <&pinctrl_periphs 0 10 101>;
266		};
267
268		emmc_pins: emmc {
269			mux {
270				groups = "emmc_nand_d07",
271				       "emmc_cmd",
272				       "emmc_clk",
273				       "emmc_ds";
274				function = "emmc";
275			};
276		};
277
278		nor_pins: nor {
279			mux {
280				groups = "nor_d",
281				       "nor_q",
282				       "nor_c",
283				       "nor_cs";
284				function = "nor";
285			};
286		};
287
288		spi_pins: spi {
289			mux {
290				groups = "spi_miso",
291					"spi_mosi",
292					"spi_sclk";
293				function = "spi";
294			};
295		};
296
297		spi_ss0_pins: spi-ss0 {
298			mux {
299				groups = "spi_ss0";
300				function = "spi";
301			};
302		};
303
304		sdcard_pins: sdcard {
305			mux {
306				groups = "sdcard_d0",
307				       "sdcard_d1",
308				       "sdcard_d2",
309				       "sdcard_d3",
310				       "sdcard_cmd",
311				       "sdcard_clk";
312				function = "sdcard";
313			};
314		};
315
316		sdio_pins: sdio {
317			mux {
318				groups = "sdio_d0",
319				       "sdio_d1",
320				       "sdio_d2",
321				       "sdio_d3",
322				       "sdio_cmd",
323				       "sdio_clk";
324				function = "sdio";
325			};
326		};
327
328		sdio_irq_pins: sdio_irq {
329			mux {
330				groups = "sdio_irq";
331				function = "sdio";
332			};
333		};
334
335		uart_a_pins: uart_a {
336			mux {
337				groups = "uart_tx_a",
338				       "uart_rx_a";
339				function = "uart_a";
340			};
341		};
342
343		uart_a_cts_rts_pins: uart_a_cts_rts {
344			mux {
345				groups = "uart_cts_a",
346				       "uart_rts_a";
347				function = "uart_a";
348			};
349		};
350
351		uart_b_pins: uart_b {
352			mux {
353				groups = "uart_tx_b",
354				       "uart_rx_b";
355				function = "uart_b";
356			};
357		};
358
359		uart_b_cts_rts_pins: uart_b_cts_rts {
360			mux {
361				groups = "uart_cts_b",
362				       "uart_rts_b";
363				function = "uart_b";
364			};
365		};
366
367		uart_c_pins: uart_c {
368			mux {
369				groups = "uart_tx_c",
370				       "uart_rx_c";
371				function = "uart_c";
372			};
373		};
374
375		uart_c_cts_rts_pins: uart_c_cts_rts {
376			mux {
377				groups = "uart_cts_c",
378				       "uart_rts_c";
379				function = "uart_c";
380			};
381		};
382
383		i2c_a_pins: i2c_a {
384			mux {
385				groups = "i2c_sck_a",
386				     "i2c_sda_a";
387				function = "i2c_a";
388			};
389		};
390
391		i2c_b_pins: i2c_b {
392			mux {
393				groups = "i2c_sck_b",
394				      "i2c_sda_b";
395				function = "i2c_b";
396			};
397		};
398
399		i2c_c_pins: i2c_c {
400			mux {
401				groups = "i2c_sck_c",
402				      "i2c_sda_c";
403				function = "i2c_c";
404			};
405		};
406
407		eth_pins: eth_c {
408			mux {
409				groups = "eth_mdio",
410				       "eth_mdc",
411				       "eth_clk_rx_clk",
412				       "eth_rx_dv",
413				       "eth_rxd0",
414				       "eth_rxd1",
415				       "eth_rxd2",
416				       "eth_rxd3",
417				       "eth_rgmii_tx_clk",
418				       "eth_tx_en",
419				       "eth_txd0",
420				       "eth_txd1",
421				       "eth_txd2",
422				       "eth_txd3";
423				function = "eth";
424			};
425		};
426
427		eth_link_led_pins: eth_link_led {
428			mux {
429				groups = "eth_link_led";
430				function = "eth_led";
431			};
432		};
433
434		eth_act_led_pins: eth_act_led {
435			mux {
436				groups = "eth_act_led";
437				function = "eth_led";
438			};
439		};
440
441		pwm_a_pins: pwm_a {
442			mux {
443				groups = "pwm_a";
444				function = "pwm_a";
445			};
446		};
447
448		pwm_b_pins: pwm_b {
449			mux {
450				groups = "pwm_b";
451				function = "pwm_b";
452			};
453		};
454
455		pwm_c_pins: pwm_c {
456			mux {
457				groups = "pwm_c";
458				function = "pwm_c";
459			};
460		};
461
462		pwm_d_pins: pwm_d {
463			mux {
464				groups = "pwm_d";
465				function = "pwm_d";
466			};
467		};
468
469		pwm_e_pins: pwm_e {
470			mux {
471				groups = "pwm_e";
472				function = "pwm_e";
473			};
474		};
475
476		pwm_f_clk_pins: pwm_f_clk {
477			mux {
478				groups = "pwm_f_clk";
479				function = "pwm_f";
480			};
481		};
482
483		pwm_f_x_pins: pwm_f_x {
484			mux {
485				groups = "pwm_f_x";
486				function = "pwm_f";
487			};
488		};
489
490		hdmi_hpd_pins: hdmi_hpd {
491			mux {
492				groups = "hdmi_hpd";
493				function = "hdmi_hpd";
494			};
495		};
496
497		hdmi_i2c_pins: hdmi_i2c {
498			mux {
499				groups = "hdmi_sda", "hdmi_scl";
500				function = "hdmi_i2c";
501			};
502		};
503
504		i2s_am_clk_pins: i2s_am_clk {
505			mux {
506				groups = "i2s_am_clk";
507				function = "i2s_out";
508			};
509		};
510
511		i2s_out_ao_clk_pins: i2s_out_ao_clk {
512			mux {
513				groups = "i2s_out_ao_clk";
514				function = "i2s_out";
515			};
516		};
517
518		i2s_out_lr_clk_pins: i2s_out_lr_clk {
519			mux {
520				groups = "i2s_out_lr_clk";
521				function = "i2s_out";
522			};
523		};
524
525		i2s_out_ch01_pins: i2s_out_ch01 {
526			mux {
527				groups = "i2s_out_ch01";
528				function = "i2s_out";
529			};
530		};
531		i2sout_ch23_z_pins: i2sout_ch23_z {
532			mux {
533				groups = "i2sout_ch23_z";
534				function = "i2s_out";
535			};
536		};
537
538		i2sout_ch45_z_pins: i2sout_ch45_z {
539			mux {
540				groups = "i2sout_ch45_z";
541				function = "i2s_out";
542			};
543		};
544
545		i2sout_ch67_z_pins: i2sout_ch67_z {
546			mux {
547				groups = "i2sout_ch67_z";
548				function = "i2s_out";
549			};
550		};
551
552		spdif_out_h_pins: spdif_out_ao_h {
553			mux {
554				groups = "spdif_out_h";
555				function = "spdif_out";
556			};
557		};
558	};
559
560	eth-phy-mux {
561		compatible = "mdio-mux-mmioreg", "mdio-mux";
562		#address-cells = <1>;
563		#size-cells = <0>;
564		reg = <0x0 0x55c 0x0 0x4>;
565		mux-mask = <0xffffffff>;
566		mdio-parent-bus = <&mdio0>;
567
568		internal_mdio: mdio@e40908ff {
569			reg = <0xe40908ff>;
570			#address-cells = <1>;
571			#size-cells = <0>;
572
573			internal_phy: ethernet-phy@8 {
574				compatible = "ethernet-phy-id0181.4400", "ethernet-phy-ieee802.3-c22";
575				reg = <8>;
576				max-speed = <100>;
577			};
578		};
579
580		external_mdio: mdio@2009087f {
581			reg = <0x2009087f>;
582			#address-cells = <1>;
583			#size-cells = <0>;
584		};
585	};
586};
587
588&saradc {
589	compatible = "amlogic,meson-gxl-saradc", "amlogic,meson-saradc";
590	clocks = <&xtal>,
591		 <&clkc CLKID_SAR_ADC>,
592		 <&clkc CLKID_SANA>,
593		 <&clkc CLKID_SAR_ADC_CLK>,
594		 <&clkc CLKID_SAR_ADC_SEL>;
595	clock-names = "clkin", "core", "sana", "adc_clk", "adc_sel";
596};
597
598&sd_emmc_a {
599	clocks = <&clkc CLKID_SD_EMMC_A>,
600		 <&xtal>,
601		 <&clkc CLKID_FCLK_DIV2>;
602	clock-names = "core", "clkin0", "clkin1";
603};
604
605&sd_emmc_b {
606	clocks = <&clkc CLKID_SD_EMMC_B>,
607		 <&xtal>,
608		 <&clkc CLKID_FCLK_DIV2>;
609       clock-names = "core", "clkin0", "clkin1";
610};
611
612&sd_emmc_c {
613	clocks = <&clkc CLKID_SD_EMMC_C>,
614		 <&xtal>,
615		 <&clkc CLKID_FCLK_DIV2>;
616	clock-names = "core", "clkin0", "clkin1";
617};
618
619&spicc {
620	clocks = <&clkc CLKID_SPICC>;
621	clock-names = "core";
622	resets = <&reset RESET_PERIPHS_SPICC>;
623	num-cs = <1>;
624};
625
626&spifc {
627	clocks = <&clkc CLKID_SPI>;
628};
629
630&uart_A {
631	clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
632	clock-names = "xtal", "core", "baud";
633};
634
635&uart_AO {
636	clocks = <&xtal>, <&clkc CLKID_CLK81>, <&xtal>;
637	clock-names = "xtal", "pclk", "baud";
638};
639
640&uart_AO_B {
641	clocks = <&xtal>, <&clkc CLKID_CLK81>, <&xtal>;
642	clock-names = "xtal", "pclk", "baud";
643};
644
645&uart_B {
646	clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
647	clock-names = "xtal", "core", "baud";
648};
649
650&uart_C {
651	clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>;
652	clock-names = "xtal", "core", "baud";
653};
654
655&vpu {
656	compatible = "amlogic,meson-gxl-vpu", "amlogic,meson-gx-vpu";
657};
658