1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (c) 2016 Endless Computers, Inc.
4 * Author: Carlo Caione <carlo@endlessm.com>
5 */
6
7#include "meson-gx.dtsi"
8#include <dt-bindings/clock/gxbb-clkc.h>
9#include <dt-bindings/clock/gxbb-aoclkc.h>
10#include <dt-bindings/gpio/meson-gxl-gpio.h>
11#include <dt-bindings/reset/amlogic,meson-gxbb-reset.h>
12
13/ {
14	compatible = "amlogic,meson-gxl";
15
16	reserved-memory {
17		/* Alternate 3 MiB reserved for ARM Trusted Firmware (BL31) */
18		secmon_reserved_alt: secmon@5000000 {
19			reg = <0x0 0x05000000 0x0 0x300000>;
20			no-map;
21		};
22	};
23
24	soc {
25		usb0: usb@c9000000 {
26			status = "disabled";
27			compatible = "amlogic,meson-gxl-dwc3";
28			#address-cells = <2>;
29			#size-cells = <2>;
30			ranges;
31
32			clocks = <&clkc CLKID_USB>;
33			clock-names = "usb_general";
34			resets = <&reset RESET_USB_OTG>;
35			reset-names = "usb_otg";
36
37			dwc3: dwc3@c9000000 {
38				compatible = "snps,dwc3";
39				reg = <0x0 0xc9000000 0x0 0x100000>;
40				interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
41				dr_mode = "host";
42				maximum-speed = "high-speed";
43				snps,dis_u2_susphy_quirk;
44				phys = <&usb3_phy>, <&usb2_phy0>, <&usb2_phy1>;
45			};
46		};
47	};
48};
49
50&apb {
51	usb2_phy0: phy@78000 {
52		compatible = "amlogic,meson-gxl-usb2-phy";
53		#phy-cells = <0>;
54		reg = <0x0 0x78000 0x0 0x20>;
55		clocks = <&clkc CLKID_USB>;
56		clock-names = "phy";
57		resets = <&reset RESET_USB_OTG>;
58		reset-names = "phy";
59		status = "okay";
60	};
61
62	usb2_phy1: phy@78020 {
63		compatible = "amlogic,meson-gxl-usb2-phy";
64		#phy-cells = <0>;
65		reg = <0x0 0x78020 0x0 0x20>;
66		clocks = <&clkc CLKID_USB>;
67		clock-names = "phy";
68		resets = <&reset RESET_USB_OTG>;
69		reset-names = "phy";
70		status = "okay";
71	};
72
73	usb3_phy: phy@78080 {
74		compatible = "amlogic,meson-gxl-usb3-phy";
75		#phy-cells = <0>;
76		reg = <0x0 0x78080 0x0 0x20>;
77		interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
78		clocks = <&clkc CLKID_USB>, <&clkc_AO CLKID_AO_CEC_32K>;
79		clock-names = "phy", "peripheral";
80		resets = <&reset RESET_USB_OTG>, <&reset RESET_USB_OTG>;
81		reset-names = "phy", "peripheral";
82		status = "okay";
83	};
84};
85
86&ethmac {
87	reg = <0x0 0xc9410000 0x0 0x10000
88	       0x0 0xc8834540 0x0 0x4>;
89
90	clocks = <&clkc CLKID_ETH>,
91		 <&clkc CLKID_FCLK_DIV2>,
92		 <&clkc CLKID_MPLL2>;
93	clock-names = "stmmaceth", "clkin0", "clkin1";
94
95	mdio0: mdio {
96		#address-cells = <1>;
97		#size-cells = <0>;
98		compatible = "snps,dwmac-mdio";
99	};
100};
101
102&aobus {
103	pinctrl_aobus: pinctrl@14 {
104		compatible = "amlogic,meson-gxl-aobus-pinctrl";
105		#address-cells = <2>;
106		#size-cells = <2>;
107		ranges;
108
109		gpio_ao: bank@14 {
110			reg = <0x0 0x00014 0x0 0x8>,
111			      <0x0 0x0002c 0x0 0x4>,
112			      <0x0 0x00024 0x0 0x8>;
113			reg-names = "mux", "pull", "gpio";
114			gpio-controller;
115			#gpio-cells = <2>;
116			gpio-ranges = <&pinctrl_aobus 0 0 14>;
117		};
118
119		uart_ao_a_pins: uart_ao_a {
120			mux {
121				groups = "uart_tx_ao_a", "uart_rx_ao_a";
122				function = "uart_ao";
123			};
124		};
125
126		uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts {
127			mux {
128				groups = "uart_cts_ao_a",
129				       "uart_rts_ao_a";
130				function = "uart_ao";
131			};
132		};
133
134		uart_ao_b_pins: uart_ao_b {
135			mux {
136				groups = "uart_tx_ao_b", "uart_rx_ao_b";
137				function = "uart_ao_b";
138			};
139		};
140
141		uart_ao_b_0_1_pins: uart_ao_b_0_1 {
142			mux {
143				groups = "uart_tx_ao_b_0", "uart_rx_ao_b_1";
144				function = "uart_ao_b";
145			};
146		};
147
148		uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts {
149			mux {
150				groups = "uart_cts_ao_b",
151				       "uart_rts_ao_b";
152				function = "uart_ao_b";
153			};
154		};
155
156		remote_input_ao_pins: remote_input_ao {
157			mux {
158				groups = "remote_input_ao";
159				function = "remote_input_ao";
160			};
161		};
162
163		i2c_ao_pins: i2c_ao {
164			mux {
165				groups = "i2c_sck_ao",
166				       "i2c_sda_ao";
167				function = "i2c_ao";
168			};
169		};
170
171		pwm_ao_a_3_pins: pwm_ao_a_3 {
172			mux {
173				groups = "pwm_ao_a_3";
174				function = "pwm_ao_a";
175			};
176		};
177
178		pwm_ao_a_8_pins: pwm_ao_a_8 {
179			mux {
180				groups = "pwm_ao_a_8";
181				function = "pwm_ao_a";
182			};
183		};
184
185		pwm_ao_b_pins: pwm_ao_b {
186			mux {
187				groups = "pwm_ao_b";
188				function = "pwm_ao_b";
189			};
190		};
191
192		pwm_ao_b_6_pins: pwm_ao_b_6 {
193			mux {
194				groups = "pwm_ao_b_6";
195				function = "pwm_ao_b";
196			};
197		};
198
199		i2s_out_ch23_ao_pins: i2s_out_ch23_ao {
200			mux {
201				groups = "i2s_out_ch23_ao";
202				function = "i2s_out_ao";
203			};
204		};
205
206		i2s_out_ch45_ao_pins: i2s_out_ch45_ao {
207			mux {
208				groups = "i2s_out_ch45_ao";
209				function = "i2s_out_ao";
210			};
211		};
212
213		spdif_out_ao_6_pins: spdif_out_ao_6 {
214			mux {
215				groups = "spdif_out_ao_6";
216				function = "spdif_out_ao";
217			};
218		};
219
220		spdif_out_ao_9_pins: spdif_out_ao_9 {
221			mux {
222				groups = "spdif_out_ao_9";
223				function = "spdif_out_ao";
224			};
225		};
226
227		ao_cec_pins: ao_cec {
228			mux {
229				groups = "ao_cec";
230				function = "cec_ao";
231			};
232		};
233
234		ee_cec_pins: ee_cec {
235			mux {
236				groups = "ee_cec";
237				function = "cec_ao";
238			};
239		};
240	};
241};
242
243&cec_AO {
244	clocks = <&clkc_AO CLKID_AO_CEC_32K>;
245	clock-names = "core";
246};
247
248&clkc_AO {
249	compatible = "amlogic,meson-gxl-aoclkc", "amlogic,meson-gx-aoclkc";
250};
251
252&gpio_intc {
253	compatible = "amlogic,meson-gpio-intc",
254		     "amlogic,meson-gxl-gpio-intc";
255	status = "okay";
256};
257
258&hdmi_tx {
259	compatible = "amlogic,meson-gxl-dw-hdmi", "amlogic,meson-gx-dw-hdmi";
260	resets = <&reset RESET_HDMITX_CAPB3>,
261		 <&reset RESET_HDMI_SYSTEM_RESET>,
262		 <&reset RESET_HDMI_TX>;
263	reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy";
264	clocks = <&clkc CLKID_HDMI_PCLK>,
265		 <&clkc CLKID_CLK81>,
266		 <&clkc CLKID_GCLK_VENCI_INT0>;
267	clock-names = "isfr", "iahb", "venci";
268};
269
270&sysctrl {
271	clkc: clock-controller {
272		compatible = "amlogic,gxl-clkc";
273		#clock-cells = <1>;
274	};
275};
276
277&i2c_A {
278	clocks = <&clkc CLKID_I2C>;
279};
280
281&i2c_AO {
282	clocks = <&clkc CLKID_AO_I2C>;
283};
284
285&i2c_B {
286	clocks = <&clkc CLKID_I2C>;
287};
288
289&i2c_C {
290	clocks = <&clkc CLKID_I2C>;
291};
292
293&periphs {
294	pinctrl_periphs: pinctrl@4b0 {
295		compatible = "amlogic,meson-gxl-periphs-pinctrl";
296		#address-cells = <2>;
297		#size-cells = <2>;
298		ranges;
299
300		gpio: bank@4b0 {
301			reg = <0x0 0x004b0 0x0 0x28>,
302			      <0x0 0x004e8 0x0 0x14>,
303			      <0x0 0x00520 0x0 0x14>,
304			      <0x0 0x00430 0x0 0x40>;
305			reg-names = "mux", "pull", "pull-enable", "gpio";
306			gpio-controller;
307			#gpio-cells = <2>;
308			gpio-ranges = <&pinctrl_periphs 0 0 100>;
309		};
310
311		emmc_pins: emmc {
312			mux {
313				groups = "emmc_nand_d07",
314				       "emmc_cmd",
315				       "emmc_clk";
316				function = "emmc";
317			};
318		};
319
320		emmc_ds_pins: emmc-ds {
321			mux {
322				groups = "emmc_ds";
323				function = "emmc";
324			};
325		};
326
327		emmc_clk_gate_pins: emmc_clk_gate {
328			mux {
329				groups = "BOOT_8";
330				function = "gpio_periphs";
331			};
332			cfg-pull-down {
333				pins = "BOOT_8";
334				bias-pull-down;
335			};
336		};
337
338		nor_pins: nor {
339			mux {
340				groups = "nor_d",
341				       "nor_q",
342				       "nor_c",
343				       "nor_cs";
344				function = "nor";
345			};
346		};
347
348		spi_pins: spi {
349			mux {
350				groups = "spi_miso",
351					"spi_mosi",
352					"spi_sclk";
353				function = "spi";
354			};
355		};
356
357		spi_ss0_pins: spi-ss0 {
358			mux {
359				groups = "spi_ss0";
360				function = "spi";
361			};
362		};
363
364		sdcard_pins: sdcard {
365			mux {
366				groups = "sdcard_d0",
367				       "sdcard_d1",
368				       "sdcard_d2",
369				       "sdcard_d3",
370				       "sdcard_cmd",
371				       "sdcard_clk";
372				function = "sdcard";
373			};
374		};
375
376		sdcard_clk_gate_pins: sdcard_clk_gate {
377			mux {
378				groups = "CARD_2";
379				function = "gpio_periphs";
380			};
381			cfg-pull-down {
382				pins = "CARD_2";
383				bias-pull-down;
384			};
385		};
386
387		sdio_pins: sdio {
388			mux {
389				groups = "sdio_d0",
390				       "sdio_d1",
391				       "sdio_d2",
392				       "sdio_d3",
393				       "sdio_cmd",
394				       "sdio_clk";
395				function = "sdio";
396			};
397		};
398
399		sdio_clk_gate_pins: sdio_clk_gate {
400			mux {
401				groups = "GPIOX_4";
402				function = "gpio_periphs";
403			};
404			cfg-pull-down {
405				pins = "GPIOX_4";
406				bias-pull-down;
407			};
408		};
409
410		sdio_irq_pins: sdio_irq {
411			mux {
412				groups = "sdio_irq";
413				function = "sdio";
414			};
415		};
416
417		uart_a_pins: uart_a {
418			mux {
419				groups = "uart_tx_a",
420				       "uart_rx_a";
421				function = "uart_a";
422			};
423		};
424
425		uart_a_cts_rts_pins: uart_a_cts_rts {
426			mux {
427				groups = "uart_cts_a",
428				       "uart_rts_a";
429				function = "uart_a";
430			};
431		};
432
433		uart_b_pins: uart_b {
434			mux {
435				groups = "uart_tx_b",
436				       "uart_rx_b";
437				function = "uart_b";
438			};
439		};
440
441		uart_b_cts_rts_pins: uart_b_cts_rts {
442			mux {
443				groups = "uart_cts_b",
444				       "uart_rts_b";
445				function = "uart_b";
446			};
447		};
448
449		uart_c_pins: uart_c {
450			mux {
451				groups = "uart_tx_c",
452				       "uart_rx_c";
453				function = "uart_c";
454			};
455		};
456
457		uart_c_cts_rts_pins: uart_c_cts_rts {
458			mux {
459				groups = "uart_cts_c",
460				       "uart_rts_c";
461				function = "uart_c";
462			};
463		};
464
465		i2c_a_pins: i2c_a {
466			mux {
467				groups = "i2c_sck_a",
468				     "i2c_sda_a";
469				function = "i2c_a";
470			};
471		};
472
473		i2c_b_pins: i2c_b {
474			mux {
475				groups = "i2c_sck_b",
476				      "i2c_sda_b";
477				function = "i2c_b";
478			};
479		};
480
481		i2c_c_pins: i2c_c {
482			mux {
483				groups = "i2c_sck_c",
484				      "i2c_sda_c";
485				function = "i2c_c";
486			};
487		};
488
489		eth_pins: eth_c {
490			mux {
491				groups = "eth_mdio",
492				       "eth_mdc",
493				       "eth_clk_rx_clk",
494				       "eth_rx_dv",
495				       "eth_rxd0",
496				       "eth_rxd1",
497				       "eth_rxd2",
498				       "eth_rxd3",
499				       "eth_rgmii_tx_clk",
500				       "eth_tx_en",
501				       "eth_txd0",
502				       "eth_txd1",
503				       "eth_txd2",
504				       "eth_txd3";
505				function = "eth";
506			};
507		};
508
509		eth_link_led_pins: eth_link_led {
510			mux {
511				groups = "eth_link_led";
512				function = "eth_led";
513			};
514		};
515
516		eth_act_led_pins: eth_act_led {
517			mux {
518				groups = "eth_act_led";
519				function = "eth_led";
520			};
521		};
522
523		pwm_a_pins: pwm_a {
524			mux {
525				groups = "pwm_a";
526				function = "pwm_a";
527			};
528		};
529
530		pwm_b_pins: pwm_b {
531			mux {
532				groups = "pwm_b";
533				function = "pwm_b";
534			};
535		};
536
537		pwm_c_pins: pwm_c {
538			mux {
539				groups = "pwm_c";
540				function = "pwm_c";
541			};
542		};
543
544		pwm_d_pins: pwm_d {
545			mux {
546				groups = "pwm_d";
547				function = "pwm_d";
548			};
549		};
550
551		pwm_e_pins: pwm_e {
552			mux {
553				groups = "pwm_e";
554				function = "pwm_e";
555			};
556		};
557
558		pwm_f_clk_pins: pwm_f_clk {
559			mux {
560				groups = "pwm_f_clk";
561				function = "pwm_f";
562			};
563		};
564
565		pwm_f_x_pins: pwm_f_x {
566			mux {
567				groups = "pwm_f_x";
568				function = "pwm_f";
569			};
570		};
571
572		hdmi_hpd_pins: hdmi_hpd {
573			mux {
574				groups = "hdmi_hpd";
575				function = "hdmi_hpd";
576			};
577		};
578
579		hdmi_i2c_pins: hdmi_i2c {
580			mux {
581				groups = "hdmi_sda", "hdmi_scl";
582				function = "hdmi_i2c";
583			};
584		};
585
586		i2s_am_clk_pins: i2s_am_clk {
587			mux {
588				groups = "i2s_am_clk";
589				function = "i2s_out";
590			};
591		};
592
593		i2s_out_ao_clk_pins: i2s_out_ao_clk {
594			mux {
595				groups = "i2s_out_ao_clk";
596				function = "i2s_out";
597			};
598		};
599
600		i2s_out_lr_clk_pins: i2s_out_lr_clk {
601			mux {
602				groups = "i2s_out_lr_clk";
603				function = "i2s_out";
604			};
605		};
606
607		i2s_out_ch01_pins: i2s_out_ch01 {
608			mux {
609				groups = "i2s_out_ch01";
610				function = "i2s_out";
611			};
612		};
613		i2sout_ch23_z_pins: i2sout_ch23_z {
614			mux {
615				groups = "i2sout_ch23_z";
616				function = "i2s_out";
617			};
618		};
619
620		i2sout_ch45_z_pins: i2sout_ch45_z {
621			mux {
622				groups = "i2sout_ch45_z";
623				function = "i2s_out";
624			};
625		};
626
627		i2sout_ch67_z_pins: i2sout_ch67_z {
628			mux {
629				groups = "i2sout_ch67_z";
630				function = "i2s_out";
631			};
632		};
633
634		spdif_out_h_pins: spdif_out_ao_h {
635			mux {
636				groups = "spdif_out_h";
637				function = "spdif_out";
638			};
639		};
640	};
641
642	eth-phy-mux {
643		compatible = "mdio-mux-mmioreg", "mdio-mux";
644		#address-cells = <1>;
645		#size-cells = <0>;
646		reg = <0x0 0x55c 0x0 0x4>;
647		mux-mask = <0xffffffff>;
648		mdio-parent-bus = <&mdio0>;
649
650		internal_mdio: mdio@e40908ff {
651			reg = <0xe40908ff>;
652			#address-cells = <1>;
653			#size-cells = <0>;
654
655			internal_phy: ethernet-phy@8 {
656				compatible = "ethernet-phy-id0181.4400", "ethernet-phy-ieee802.3-c22";
657				interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
658				reg = <8>;
659				max-speed = <100>;
660			};
661		};
662
663		external_mdio: mdio@2009087f {
664			reg = <0x2009087f>;
665			#address-cells = <1>;
666			#size-cells = <0>;
667		};
668	};
669};
670
671&pwrc_vpu {
672	resets = <&reset RESET_VIU>,
673		 <&reset RESET_VENC>,
674		 <&reset RESET_VCBUS>,
675		 <&reset RESET_BT656>,
676		 <&reset RESET_DVIN_RESET>,
677		 <&reset RESET_RDMA>,
678		 <&reset RESET_VENCI>,
679		 <&reset RESET_VENCP>,
680		 <&reset RESET_VDAC>,
681		 <&reset RESET_VDI6>,
682		 <&reset RESET_VENCL>,
683		 <&reset RESET_VID_LOCK>;
684	clocks = <&clkc CLKID_VPU>,
685	         <&clkc CLKID_VAPB>;
686	clock-names = "vpu", "vapb";
687	/*
688	 * VPU clocking is provided by two identical clock paths
689	 * VPU_0 and VPU_1 muxed to a single clock by a glitch
690	 * free mux to safely change frequency while running.
691	 * Same for VAPB but with a final gate after the glitch free mux.
692	 */
693	assigned-clocks = <&clkc CLKID_VPU_0_SEL>,
694			  <&clkc CLKID_VPU_0>,
695			  <&clkc CLKID_VPU>, /* Glitch free mux */
696			  <&clkc CLKID_VAPB_0_SEL>,
697			  <&clkc CLKID_VAPB_0>,
698			  <&clkc CLKID_VAPB_SEL>; /* Glitch free mux */
699	assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
700				 <0>, /* Do Nothing */
701				 <&clkc CLKID_VPU_0>,
702				 <&clkc CLKID_FCLK_DIV4>,
703				 <0>, /* Do Nothing */
704				 <&clkc CLKID_VAPB_0>;
705	assigned-clock-rates = <0>, /* Do Nothing */
706			       <666666666>,
707			       <0>, /* Do Nothing */
708			       <0>, /* Do Nothing */
709			       <250000000>,
710			       <0>; /* Do Nothing */
711};
712
713&saradc {
714	compatible = "amlogic,meson-gxl-saradc", "amlogic,meson-saradc";
715	clocks = <&xtal>,
716		 <&clkc CLKID_SAR_ADC>,
717		 <&clkc CLKID_SAR_ADC_CLK>,
718		 <&clkc CLKID_SAR_ADC_SEL>;
719	clock-names = "clkin", "core", "adc_clk", "adc_sel";
720};
721
722&sd_emmc_a {
723	clocks = <&clkc CLKID_SD_EMMC_A>,
724		 <&clkc CLKID_SD_EMMC_A_CLK0>,
725		 <&clkc CLKID_FCLK_DIV2>;
726	clock-names = "core", "clkin0", "clkin1";
727	resets = <&reset RESET_SD_EMMC_A>;
728};
729
730&sd_emmc_b {
731	clocks = <&clkc CLKID_SD_EMMC_B>,
732		 <&clkc CLKID_SD_EMMC_B_CLK0>,
733		 <&clkc CLKID_FCLK_DIV2>;
734	clock-names = "core", "clkin0", "clkin1";
735	resets = <&reset RESET_SD_EMMC_B>;
736};
737
738&sd_emmc_c {
739	clocks = <&clkc CLKID_SD_EMMC_C>,
740		 <&clkc CLKID_SD_EMMC_C_CLK0>,
741		 <&clkc CLKID_FCLK_DIV2>;
742	clock-names = "core", "clkin0", "clkin1";
743	resets = <&reset RESET_SD_EMMC_C>;
744};
745
746&spicc {
747	clocks = <&clkc CLKID_SPICC>;
748	clock-names = "core";
749	resets = <&reset RESET_PERIPHS_SPICC>;
750	num-cs = <1>;
751};
752
753&spifc {
754	clocks = <&clkc CLKID_SPI>;
755};
756
757&uart_A {
758	clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
759	clock-names = "xtal", "pclk", "baud";
760};
761
762&uart_AO {
763	clocks = <&xtal>, <&clkc CLKID_CLK81>, <&xtal>;
764	clock-names = "xtal", "pclk", "baud";
765};
766
767&uart_AO_B {
768	clocks = <&xtal>, <&clkc CLKID_CLK81>, <&xtal>;
769	clock-names = "xtal", "pclk", "baud";
770};
771
772&uart_B {
773	clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
774	clock-names = "xtal", "pclk", "baud";
775};
776
777&uart_C {
778	clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>;
779	clock-names = "xtal", "pclk", "baud";
780};
781
782&vpu {
783	compatible = "amlogic,meson-gxl-vpu", "amlogic,meson-gx-vpu";
784	power-domains = <&pwrc_vpu>;
785};
786