1/*
2 * Copyright (c) 2016 Endless Computers, Inc.
3 * Author: Carlo Caione <carlo@endlessm.com>
4 *
5 * This file is dual-licensed: you can use it either under the terms
6 * of the GPL or the X11 license, at your option. Note that this dual
7 * licensing only applies to this file, and not this project as a
8 * whole.
9 *
10 *  a) This library is free software; you can redistribute it and/or
11 *     modify it under the terms of the GNU General Public License as
12 *     published by the Free Software Foundation; either version 2 of the
13 *     License, or (at your option) any later version.
14 *
15 *     This library is distributed in the hope that it will be useful,
16 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
17 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
18 *     GNU General Public License for more details.
19 *
20 * Or, alternatively,
21 *
22 *  b) Permission is hereby granted, free of charge, to any person
23 *     obtaining a copy of this software and associated documentation
24 *     files (the "Software"), to deal in the Software without
25 *     restriction, including without limitation the rights to use,
26 *     copy, modify, merge, publish, distribute, sublicense, and/or
27 *     sell copies of the Software, and to permit persons to whom the
28 *     Software is furnished to do so, subject to the following
29 *     conditions:
30 *
31 *     The above copyright notice and this permission notice shall be
32 *     included in all copies or substantial portions of the Software.
33 *
34 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
35 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
36 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
37 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
38 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
39 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
40 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
41 *     OTHER DEALINGS IN THE SOFTWARE.
42 */
43
44#include "meson-gx.dtsi"
45#include <dt-bindings/clock/gxbb-clkc.h>
46#include <dt-bindings/clock/gxbb-aoclkc.h>
47#include <dt-bindings/gpio/meson-gxl-gpio.h>
48#include <dt-bindings/reset/amlogic,meson-gxbb-reset.h>
49
50/ {
51	compatible = "amlogic,meson-gxl";
52};
53
54&ethmac {
55	reg = <0x0 0xc9410000 0x0 0x10000
56	       0x0 0xc8834540 0x0 0x4>;
57
58	clocks = <&clkc CLKID_ETH>,
59		 <&clkc CLKID_FCLK_DIV2>,
60		 <&clkc CLKID_MPLL2>;
61	clock-names = "stmmaceth", "clkin0", "clkin1";
62
63	mdio0: mdio {
64		#address-cells = <1>;
65		#size-cells = <0>;
66		compatible = "snps,dwmac-mdio";
67	};
68};
69
70&aobus {
71	pinctrl_aobus: pinctrl@14 {
72		compatible = "amlogic,meson-gxl-aobus-pinctrl";
73		#address-cells = <2>;
74		#size-cells = <2>;
75		ranges;
76
77		gpio_ao: bank@14 {
78			reg = <0x0 0x00014 0x0 0x8>,
79			      <0x0 0x0002c 0x0 0x4>,
80			      <0x0 0x00024 0x0 0x8>;
81			reg-names = "mux", "pull", "gpio";
82			gpio-controller;
83			#gpio-cells = <2>;
84			gpio-ranges = <&pinctrl_aobus 0 0 14>;
85		};
86
87		uart_ao_a_pins: uart_ao_a {
88			mux {
89				groups = "uart_tx_ao_a", "uart_rx_ao_a";
90				function = "uart_ao";
91			};
92		};
93
94		uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts {
95			mux {
96				groups = "uart_cts_ao_a",
97				       "uart_rts_ao_a";
98				function = "uart_ao";
99			};
100		};
101
102		uart_ao_b_pins: uart_ao_b {
103			mux {
104				groups = "uart_tx_ao_b", "uart_rx_ao_b";
105				function = "uart_ao_b";
106			};
107		};
108
109		uart_ao_b_0_1_pins: uart_ao_b_0_1 {
110			mux {
111				groups = "uart_tx_ao_b_0", "uart_rx_ao_b_1";
112				function = "uart_ao_b";
113			};
114		};
115
116		uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts {
117			mux {
118				groups = "uart_cts_ao_b",
119				       "uart_rts_ao_b";
120				function = "uart_ao_b";
121			};
122		};
123
124		remote_input_ao_pins: remote_input_ao {
125			mux {
126				groups = "remote_input_ao";
127				function = "remote_input_ao";
128			};
129		};
130
131		i2c_ao_pins: i2c_ao {
132			mux {
133				groups = "i2c_sck_ao",
134				       "i2c_sda_ao";
135				function = "i2c_ao";
136			};
137		};
138
139		pwm_ao_a_3_pins: pwm_ao_a_3 {
140			mux {
141				groups = "pwm_ao_a_3";
142				function = "pwm_ao_a";
143			};
144		};
145
146		pwm_ao_a_8_pins: pwm_ao_a_8 {
147			mux {
148				groups = "pwm_ao_a_8";
149				function = "pwm_ao_a";
150			};
151		};
152
153		pwm_ao_b_pins: pwm_ao_b {
154			mux {
155				groups = "pwm_ao_b";
156				function = "pwm_ao_b";
157			};
158		};
159
160		pwm_ao_b_6_pins: pwm_ao_b_6 {
161			mux {
162				groups = "pwm_ao_b_6";
163				function = "pwm_ao_b";
164			};
165		};
166
167		i2s_out_ch23_ao_pins: i2s_out_ch23_ao {
168			mux {
169				groups = "i2s_out_ch23_ao";
170				function = "i2s_out_ao";
171			};
172		};
173
174		i2s_out_ch45_ao_pins: i2s_out_ch45_ao {
175			mux {
176				groups = "i2s_out_ch45_ao";
177				function = "i2s_out_ao";
178			};
179		};
180
181		spdif_out_ao_6_pins: spdif_out_ao_6 {
182			mux {
183				groups = "spdif_out_ao_6";
184				function = "spdif_out_ao";
185			};
186		};
187
188		spdif_out_ao_9_pins: spdif_out_ao_9 {
189			mux {
190				groups = "spdif_out_ao_9";
191				function = "spdif_out_ao";
192			};
193		};
194
195		ao_cec_pins: ao_cec {
196			mux {
197				groups = "ao_cec";
198				function = "cec_ao";
199			};
200		};
201
202		ee_cec_pins: ee_cec {
203			mux {
204				groups = "ee_cec";
205				function = "cec_ao";
206			};
207		};
208	};
209};
210
211&cec_AO {
212	clocks = <&clkc_AO CLKID_AO_CEC_32K>;
213	clock-names = "core";
214};
215
216&clkc_AO {
217	compatible = "amlogic,meson-gxl-aoclkc", "amlogic,meson-gx-aoclkc";
218};
219
220&hdmi_tx {
221	compatible = "amlogic,meson-gxl-dw-hdmi", "amlogic,meson-gx-dw-hdmi";
222	resets = <&reset RESET_HDMITX_CAPB3>,
223		 <&reset RESET_HDMI_SYSTEM_RESET>,
224		 <&reset RESET_HDMI_TX>;
225	reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy";
226	clocks = <&clkc CLKID_HDMI_PCLK>,
227		 <&clkc CLKID_CLK81>,
228		 <&clkc CLKID_GCLK_VENCI_INT0>;
229	clock-names = "isfr", "iahb", "venci";
230};
231
232&hiubus {
233	clkc: clock-controller@0 {
234		compatible = "amlogic,gxl-clkc", "amlogic,gxbb-clkc";
235		#clock-cells = <1>;
236		reg = <0x0 0x0 0x0 0x3db>;
237	};
238};
239
240&i2c_A {
241	clocks = <&clkc CLKID_I2C>;
242};
243
244&i2c_AO {
245	clocks = <&clkc CLKID_AO_I2C>;
246};
247
248&i2c_B {
249	clocks = <&clkc CLKID_I2C>;
250};
251
252&i2c_C {
253	clocks = <&clkc CLKID_I2C>;
254};
255
256&periphs {
257	pinctrl_periphs: pinctrl@4b0 {
258		compatible = "amlogic,meson-gxl-periphs-pinctrl";
259		#address-cells = <2>;
260		#size-cells = <2>;
261		ranges;
262
263		gpio: bank@4b0 {
264			reg = <0x0 0x004b0 0x0 0x28>,
265			      <0x0 0x004e8 0x0 0x14>,
266			      <0x0 0x00520 0x0 0x14>,
267			      <0x0 0x00430 0x0 0x40>;
268			reg-names = "mux", "pull", "pull-enable", "gpio";
269			gpio-controller;
270			#gpio-cells = <2>;
271			gpio-ranges = <&pinctrl_periphs 0 0 100>;
272		};
273
274		emmc_pins: emmc {
275			mux {
276				groups = "emmc_nand_d07",
277				       "emmc_cmd",
278				       "emmc_clk";
279				function = "emmc";
280			};
281		};
282
283		emmc_ds_pins: emmc-ds {
284			mux {
285				groups = "emmc_ds";
286				function = "emmc";
287			};
288		};
289
290		emmc_clk_gate_pins: emmc_clk_gate {
291			mux {
292				groups = "BOOT_8";
293				function = "gpio_periphs";
294			};
295			cfg-pull-down {
296				pins = "BOOT_8";
297				bias-pull-down;
298			};
299		};
300
301		nor_pins: nor {
302			mux {
303				groups = "nor_d",
304				       "nor_q",
305				       "nor_c",
306				       "nor_cs";
307				function = "nor";
308			};
309		};
310
311		spi_pins: spi {
312			mux {
313				groups = "spi_miso",
314					"spi_mosi",
315					"spi_sclk";
316				function = "spi";
317			};
318		};
319
320		spi_ss0_pins: spi-ss0 {
321			mux {
322				groups = "spi_ss0";
323				function = "spi";
324			};
325		};
326
327		sdcard_pins: sdcard {
328			mux {
329				groups = "sdcard_d0",
330				       "sdcard_d1",
331				       "sdcard_d2",
332				       "sdcard_d3",
333				       "sdcard_cmd",
334				       "sdcard_clk";
335				function = "sdcard";
336			};
337		};
338
339		sdcard_clk_gate_pins: sdcard_clk_gate {
340			mux {
341				groups = "CARD_2";
342				function = "gpio_periphs";
343			};
344			cfg-pull-down {
345				pins = "CARD_2";
346				bias-pull-down;
347			};
348		};
349
350		sdio_pins: sdio {
351			mux {
352				groups = "sdio_d0",
353				       "sdio_d1",
354				       "sdio_d2",
355				       "sdio_d3",
356				       "sdio_cmd",
357				       "sdio_clk";
358				function = "sdio";
359			};
360		};
361
362		sdio_clk_gate_pins: sdio_clk_gate {
363			mux {
364				groups = "GPIOX_4";
365				function = "gpio_periphs";
366			};
367			cfg-pull-down {
368				pins = "GPIOX_4";
369				bias-pull-down;
370			};
371		};
372
373		sdio_irq_pins: sdio_irq {
374			mux {
375				groups = "sdio_irq";
376				function = "sdio";
377			};
378		};
379
380		uart_a_pins: uart_a {
381			mux {
382				groups = "uart_tx_a",
383				       "uart_rx_a";
384				function = "uart_a";
385			};
386		};
387
388		uart_a_cts_rts_pins: uart_a_cts_rts {
389			mux {
390				groups = "uart_cts_a",
391				       "uart_rts_a";
392				function = "uart_a";
393			};
394		};
395
396		uart_b_pins: uart_b {
397			mux {
398				groups = "uart_tx_b",
399				       "uart_rx_b";
400				function = "uart_b";
401			};
402		};
403
404		uart_b_cts_rts_pins: uart_b_cts_rts {
405			mux {
406				groups = "uart_cts_b",
407				       "uart_rts_b";
408				function = "uart_b";
409			};
410		};
411
412		uart_c_pins: uart_c {
413			mux {
414				groups = "uart_tx_c",
415				       "uart_rx_c";
416				function = "uart_c";
417			};
418		};
419
420		uart_c_cts_rts_pins: uart_c_cts_rts {
421			mux {
422				groups = "uart_cts_c",
423				       "uart_rts_c";
424				function = "uart_c";
425			};
426		};
427
428		i2c_a_pins: i2c_a {
429			mux {
430				groups = "i2c_sck_a",
431				     "i2c_sda_a";
432				function = "i2c_a";
433			};
434		};
435
436		i2c_b_pins: i2c_b {
437			mux {
438				groups = "i2c_sck_b",
439				      "i2c_sda_b";
440				function = "i2c_b";
441			};
442		};
443
444		i2c_c_pins: i2c_c {
445			mux {
446				groups = "i2c_sck_c",
447				      "i2c_sda_c";
448				function = "i2c_c";
449			};
450		};
451
452		eth_pins: eth_c {
453			mux {
454				groups = "eth_mdio",
455				       "eth_mdc",
456				       "eth_clk_rx_clk",
457				       "eth_rx_dv",
458				       "eth_rxd0",
459				       "eth_rxd1",
460				       "eth_rxd2",
461				       "eth_rxd3",
462				       "eth_rgmii_tx_clk",
463				       "eth_tx_en",
464				       "eth_txd0",
465				       "eth_txd1",
466				       "eth_txd2",
467				       "eth_txd3";
468				function = "eth";
469			};
470		};
471
472		eth_link_led_pins: eth_link_led {
473			mux {
474				groups = "eth_link_led";
475				function = "eth_led";
476			};
477		};
478
479		eth_act_led_pins: eth_act_led {
480			mux {
481				groups = "eth_act_led";
482				function = "eth_led";
483			};
484		};
485
486		pwm_a_pins: pwm_a {
487			mux {
488				groups = "pwm_a";
489				function = "pwm_a";
490			};
491		};
492
493		pwm_b_pins: pwm_b {
494			mux {
495				groups = "pwm_b";
496				function = "pwm_b";
497			};
498		};
499
500		pwm_c_pins: pwm_c {
501			mux {
502				groups = "pwm_c";
503				function = "pwm_c";
504			};
505		};
506
507		pwm_d_pins: pwm_d {
508			mux {
509				groups = "pwm_d";
510				function = "pwm_d";
511			};
512		};
513
514		pwm_e_pins: pwm_e {
515			mux {
516				groups = "pwm_e";
517				function = "pwm_e";
518			};
519		};
520
521		pwm_f_clk_pins: pwm_f_clk {
522			mux {
523				groups = "pwm_f_clk";
524				function = "pwm_f";
525			};
526		};
527
528		pwm_f_x_pins: pwm_f_x {
529			mux {
530				groups = "pwm_f_x";
531				function = "pwm_f";
532			};
533		};
534
535		hdmi_hpd_pins: hdmi_hpd {
536			mux {
537				groups = "hdmi_hpd";
538				function = "hdmi_hpd";
539			};
540		};
541
542		hdmi_i2c_pins: hdmi_i2c {
543			mux {
544				groups = "hdmi_sda", "hdmi_scl";
545				function = "hdmi_i2c";
546			};
547		};
548
549		i2s_am_clk_pins: i2s_am_clk {
550			mux {
551				groups = "i2s_am_clk";
552				function = "i2s_out";
553			};
554		};
555
556		i2s_out_ao_clk_pins: i2s_out_ao_clk {
557			mux {
558				groups = "i2s_out_ao_clk";
559				function = "i2s_out";
560			};
561		};
562
563		i2s_out_lr_clk_pins: i2s_out_lr_clk {
564			mux {
565				groups = "i2s_out_lr_clk";
566				function = "i2s_out";
567			};
568		};
569
570		i2s_out_ch01_pins: i2s_out_ch01 {
571			mux {
572				groups = "i2s_out_ch01";
573				function = "i2s_out";
574			};
575		};
576		i2sout_ch23_z_pins: i2sout_ch23_z {
577			mux {
578				groups = "i2sout_ch23_z";
579				function = "i2s_out";
580			};
581		};
582
583		i2sout_ch45_z_pins: i2sout_ch45_z {
584			mux {
585				groups = "i2sout_ch45_z";
586				function = "i2s_out";
587			};
588		};
589
590		i2sout_ch67_z_pins: i2sout_ch67_z {
591			mux {
592				groups = "i2sout_ch67_z";
593				function = "i2s_out";
594			};
595		};
596
597		spdif_out_h_pins: spdif_out_ao_h {
598			mux {
599				groups = "spdif_out_h";
600				function = "spdif_out";
601			};
602		};
603	};
604
605	eth-phy-mux {
606		compatible = "mdio-mux-mmioreg", "mdio-mux";
607		#address-cells = <1>;
608		#size-cells = <0>;
609		reg = <0x0 0x55c 0x0 0x4>;
610		mux-mask = <0xffffffff>;
611		mdio-parent-bus = <&mdio0>;
612
613		internal_mdio: mdio@e40908ff {
614			reg = <0xe40908ff>;
615			#address-cells = <1>;
616			#size-cells = <0>;
617
618			internal_phy: ethernet-phy@8 {
619				compatible = "ethernet-phy-id0181.4400", "ethernet-phy-ieee802.3-c22";
620				reg = <8>;
621				max-speed = <100>;
622			};
623		};
624
625		external_mdio: mdio@2009087f {
626			reg = <0x2009087f>;
627			#address-cells = <1>;
628			#size-cells = <0>;
629		};
630	};
631};
632
633&saradc {
634	compatible = "amlogic,meson-gxl-saradc", "amlogic,meson-saradc";
635	clocks = <&xtal>,
636		 <&clkc CLKID_SAR_ADC>,
637		 <&clkc CLKID_SANA>,
638		 <&clkc CLKID_SAR_ADC_CLK>,
639		 <&clkc CLKID_SAR_ADC_SEL>;
640	clock-names = "clkin", "core", "sana", "adc_clk", "adc_sel";
641};
642
643&sd_emmc_a {
644	clocks = <&clkc CLKID_SD_EMMC_A>,
645		 <&clkc CLKID_SD_EMMC_A_CLK0>,
646		 <&clkc CLKID_FCLK_DIV2>;
647	clock-names = "core", "clkin0", "clkin1";
648};
649
650&sd_emmc_b {
651	clocks = <&clkc CLKID_SD_EMMC_B>,
652		 <&clkc CLKID_SD_EMMC_B_CLK0>,
653		 <&clkc CLKID_FCLK_DIV2>;
654       clock-names = "core", "clkin0", "clkin1";
655};
656
657&sd_emmc_c {
658	clocks = <&clkc CLKID_SD_EMMC_C>,
659		 <&clkc CLKID_SD_EMMC_C_CLK0>,
660		 <&clkc CLKID_FCLK_DIV2>;
661	clock-names = "core", "clkin0", "clkin1";
662};
663
664&spicc {
665	clocks = <&clkc CLKID_SPICC>;
666	clock-names = "core";
667	resets = <&reset RESET_PERIPHS_SPICC>;
668	num-cs = <1>;
669};
670
671&spifc {
672	clocks = <&clkc CLKID_SPI>;
673};
674
675&uart_A {
676	clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
677	clock-names = "xtal", "core", "baud";
678};
679
680&uart_AO {
681	clocks = <&xtal>, <&clkc CLKID_CLK81>, <&xtal>;
682	clock-names = "xtal", "pclk", "baud";
683};
684
685&uart_AO_B {
686	clocks = <&xtal>, <&clkc CLKID_CLK81>, <&xtal>;
687	clock-names = "xtal", "pclk", "baud";
688};
689
690&uart_B {
691	clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
692	clock-names = "xtal", "core", "baud";
693};
694
695&uart_C {
696	clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>;
697	clock-names = "xtal", "core", "baud";
698};
699
700&vpu {
701	compatible = "amlogic,meson-gxl-vpu", "amlogic,meson-gx-vpu";
702};
703