clk: samsung: exynos5433: Add missing clocks for CMU_FSYS domain

This patch adds the mux/divider/gate clocks for CMU_FSYS domain which
contains the clocks of USB/UFS/SDMMC/TSI/PDMA IPs.

clk: samsung: exynos5433: Add missing clocks for CMU_FSYS domain

This patch adds the mux/divider/gate clocks for CMU_FSYS domain which
contains the clocks of USB/UFS/SDMMC/TSI/PDMA IPs.

Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Acked-by: Inki Dae <inki.dae@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>

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clk: samsung: exynos5433: Add clocks for CMU_BUS{0|1|2} domains

This patch adds the mux/divider/gate clocks for CMU_BUS{0|1|2} domains
which contain global data buses clocked at up the 4

clk: samsung: exynos5433: Add clocks for CMU_BUS{0|1|2} domains

This patch adds the mux/divider/gate clocks for CMU_BUS{0|1|2} domains
which contain global data buses clocked at up the 400MHz. These blocks
transfer data between DRAM and various sub-blocks. These clock domains
also contain global peripheral buses clocked at 67/111/200/222/266/333/400
MHz and used for register accesses.

Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Acked-by: Inki Dae <inki.dae@samsung.com>
Reviewed-by: Pankaj Dubey <pankaj.dubey@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>

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clk: samsung: exynos5433: Add clocks for CMU_AUD domain

This patch adds the mux/divider/gate clocks for CMU_AUD domain which
includes the clocks of Cortex-A5/Bus/Audio clocks.

S

clk: samsung: exynos5433: Add clocks for CMU_AUD domain

This patch adds the mux/divider/gate clocks for CMU_AUD domain which
includes the clocks of Cortex-A5/Bus/Audio clocks.

Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Acked-by: Inki Dae <inki.dae@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>

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clk: samsung: exynos5433: Add clocks for CMU_DISP domain

This patch adds the the mux/divider/gate clocks for CMU_DISP domain
which includes clocks of the display IPs (DECON/HDMI/DSIM/MIX

clk: samsung: exynos5433: Add clocks for CMU_DISP domain

This patch adds the the mux/divider/gate clocks for CMU_DISP domain
which includes clocks of the display IPs (DECON/HDMI/DSIM/MIXER).

Also, CMU_DISP requires 'sclk_hdmi_spdif_disp' source clock from CMU_TOP
domain. This patch adds the clocks of CMU_TOP related to HDMI.

Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Acked-by: Inki Dae <inki.dae@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>

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clk: samsung: exynos5433: Add clocks for CMU_MIF domain

This patch adds the mux/divider/gate clocks of CMU_MIF domain which includes
the clocks for DMC(DRAM memory controller) and CCI(Ca

clk: samsung: exynos5433: Add clocks for CMU_MIF domain

This patch adds the mux/divider/gate clocks of CMU_MIF domain which includes
the clocks for DMC(DRAM memory controller) and CCI(Cache Coherent Interconnect).
The CMU_MIF domain provides the source clocks for CMU_DISP/CMU_BUS2.

Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Acked-by: Inki Dae <inki.dae@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>

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clk: samsung: exynos5433: Add clocks for CMU_G2D domain

This patch adds ths mux/divider/gate clocks of CMU_G2D domain which
includes G2D/MDMA IPs. The CMU_G2D requires its parent defined

clk: samsung: exynos5433: Add clocks for CMU_G2D domain

This patch adds ths mux/divider/gate clocks of CMU_G2D domain which
includes G2D/MDMA IPs. The CMU_G2D requires its parent defined in
the CMU_TOP domain. Hence this patch adds G2D related clocks to the
CMU_TOP domain.

Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Acked-by: Inki Dae <inki.dae@samsung.com>
Reviewed-by: Pankaj Dubey <pankaj.dubey@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>

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clk: samsung: exynos5433: Add clocks for CMU_PERIS domain

This patch adds missing gate clocks of CMU_PERIS domain
which includes TMU/TZPC/SECKEY/CHIPID/TOPRTC/EFUSE IPs.
The special

clk: samsung: exynos5433: Add clocks for CMU_PERIS domain

This patch adds missing gate clocks of CMU_PERIS domain
which includes TMU/TZPC/SECKEY/CHIPID/TOPRTC/EFUSE IPs.
The special clocks of CMU_PERIS use oscclk source clock directly.

Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Acked-by: Inki Dae <inki.dae@samsung.com>
Reviewed-by: Pankaj Dubey <pankaj.dubey@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>

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clk: samsung: exynos5433: Add clocks for CMU_PERIC domain

This patch adds missing divider/gate clocks of CMU_PERIC domain
which includes I2S/PCM/SPDIF/PWM/SLIMBUS IPs. The SPI/I2S may us

clk: samsung: exynos5433: Add clocks for CMU_PERIC domain

This patch adds missing divider/gate clocks of CMU_PERIC domain
which includes I2S/PCM/SPDIF/PWM/SLIMBUS IPs. The SPI/I2S may use
external input clock which has 'ioclk_*' prefix.

Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
[ideal.song: Change clk flags of to pclk_gpio_* clk, pclk_gpio_* should be always on]
Signed-off-by: Inha Song <ideal.song@samsung.com>
Acked-by: Inki Dae <inki.dae@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>

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clk: samsung: exynos5433: Add MUX clocks of CMU_TOP domain

This patch adds the MUX (multiplexer) clocks for CMU_TOP domain of Exynos5433.
CMU_TOP domain provides source clocks to other C

clk: samsung: exynos5433: Add MUX clocks of CMU_TOP domain

This patch adds the MUX (multiplexer) clocks for CMU_TOP domain of Exynos5433.
CMU_TOP domain provides source clocks to other CMU domains.

Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Acked-by: Inki Dae <inki.dae@samsung.com>
Reviewed-by: Pankaj Dubey <pankaj.dubey@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>

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clk: samsung: exynos5433: Add clocks using common clock framework

This patch adds support for the CMU (Clock Management Units) of Exynos5433
which is an Octa-core 64bit SoC. This patch s

clk: samsung: exynos5433: Add clocks using common clock framework

This patch adds support for the CMU (Clock Management Units) of Exynos5433
which is an Octa-core 64bit SoC. This patch supports necessary clocks
(PLL/MMC/UART/MCT/I2C/SPI) for kernel boot and includes binding documentation
for Exynos5433 clock controller.

Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Acked-by: Inki Dae <inki.dae@samsung.com>
[s.nawrocki@samsung.com: whitespace cleanup in dt-bindings/clock/exynos5433.h]
[ added U suffix to first arguments of PLL_35XX_RATE()]
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>

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