1 /* 2 * Copyright (c) 2014 Samsung Electronics Co., Ltd. 3 * Author: Chanwoo Choi <cw00.choi@samsung.com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 */ 9 10 #ifndef _DT_BINDINGS_CLOCK_EXYNOS5433_H 11 #define _DT_BINDINGS_CLOCK_EXYNOS5433_H 12 13 /* CMU_TOP */ 14 #define CLK_FOUT_ISP_PLL 1 15 #define CLK_FOUT_AUD_PLL 2 16 17 #define CLK_MOUT_AUD_PLL 10 18 #define CLK_MOUT_ISP_PLL 11 19 #define CLK_MOUT_AUD_PLL_USER_T 12 20 #define CLK_MOUT_MPHY_PLL_USER 13 21 #define CLK_MOUT_MFC_PLL_USER 14 22 #define CLK_MOUT_BUS_PLL_USER 15 23 #define CLK_MOUT_ACLK_HEVC_400 16 24 #define CLK_MOUT_ACLK_CAM1_333 17 25 #define CLK_MOUT_ACLK_CAM1_552_B 18 26 #define CLK_MOUT_ACLK_CAM1_552_A 19 27 #define CLK_MOUT_ACLK_ISP_DIS_400 20 28 #define CLK_MOUT_ACLK_ISP_400 21 29 #define CLK_MOUT_ACLK_BUS0_400 22 30 #define CLK_MOUT_ACLK_MSCL_400_B 23 31 #define CLK_MOUT_ACLK_MSCL_400_A 24 32 #define CLK_MOUT_ACLK_GSCL_333 25 33 #define CLK_MOUT_ACLK_G2D_400_B 26 34 #define CLK_MOUT_ACLK_G2D_400_A 27 35 #define CLK_MOUT_SCLK_JPEG_C 28 36 #define CLK_MOUT_SCLK_JPEG_B 29 37 #define CLK_MOUT_SCLK_JPEG_A 30 38 #define CLK_MOUT_SCLK_MMC2_B 31 39 #define CLK_MOUT_SCLK_MMC2_A 32 40 #define CLK_MOUT_SCLK_MMC1_B 33 41 #define CLK_MOUT_SCLK_MMC1_A 34 42 #define CLK_MOUT_SCLK_MMC0_D 35 43 #define CLK_MOUT_SCLK_MMC0_C 36 44 #define CLK_MOUT_SCLK_MMC0_B 37 45 #define CLK_MOUT_SCLK_MMC0_A 38 46 #define CLK_MOUT_SCLK_SPI4 39 47 #define CLK_MOUT_SCLK_SPI3 40 48 #define CLK_MOUT_SCLK_UART2 41 49 #define CLK_MOUT_SCLK_UART1 42 50 #define CLK_MOUT_SCLK_UART0 43 51 #define CLK_MOUT_SCLK_SPI2 44 52 #define CLK_MOUT_SCLK_SPI1 45 53 #define CLK_MOUT_SCLK_SPI0 46 54 #define CLK_MOUT_ACLK_MFC_400_C 47 55 #define CLK_MOUT_ACLK_MFC_400_B 48 56 #define CLK_MOUT_ACLK_MFC_400_A 49 57 #define CLK_MOUT_SCLK_ISP_SENSOR2 50 58 #define CLK_MOUT_SCLK_ISP_SENSOR1 51 59 #define CLK_MOUT_SCLK_ISP_SENSOR0 52 60 #define CLK_MOUT_SCLK_ISP_UART 53 61 #define CLK_MOUT_SCLK_ISP_SPI1 54 62 #define CLK_MOUT_SCLK_ISP_SPI0 55 63 #define CLK_MOUT_SCLK_PCIE_100 56 64 #define CLK_MOUT_SCLK_UFSUNIPRO 57 65 #define CLK_MOUT_SCLK_USBHOST30 58 66 #define CLK_MOUT_SCLK_USBDRD30 59 67 #define CLK_MOUT_SCLK_SLIMBUS 60 68 #define CLK_MOUT_SCLK_SPDIF 61 69 #define CLK_MOUT_SCLK_AUDIO1 62 70 #define CLK_MOUT_SCLK_AUDIO0 63 71 72 #define CLK_DIV_ACLK_FSYS_200 100 73 #define CLK_DIV_ACLK_IMEM_SSSX_266 101 74 #define CLK_DIV_ACLK_IMEM_200 102 75 #define CLK_DIV_ACLK_IMEM_266 103 76 #define CLK_DIV_ACLK_PERIC_66_B 104 77 #define CLK_DIV_ACLK_PERIC_66_A 105 78 #define CLK_DIV_ACLK_PERIS_66_B 106 79 #define CLK_DIV_ACLK_PERIS_66_A 107 80 #define CLK_DIV_SCLK_MMC1_B 108 81 #define CLK_DIV_SCLK_MMC1_A 109 82 #define CLK_DIV_SCLK_MMC0_B 110 83 #define CLK_DIV_SCLK_MMC0_A 111 84 #define CLK_DIV_SCLK_MMC2_B 112 85 #define CLK_DIV_SCLK_MMC2_A 113 86 #define CLK_DIV_SCLK_SPI1_B 114 87 #define CLK_DIV_SCLK_SPI1_A 115 88 #define CLK_DIV_SCLK_SPI0_B 116 89 #define CLK_DIV_SCLK_SPI0_A 117 90 #define CLK_DIV_SCLK_SPI2_B 118 91 #define CLK_DIV_SCLK_SPI2_A 119 92 #define CLK_DIV_SCLK_UART2 120 93 #define CLK_DIV_SCLK_UART1 121 94 #define CLK_DIV_SCLK_UART0 122 95 #define CLK_DIV_SCLK_SPI4_B 123 96 #define CLK_DIV_SCLK_SPI4_A 124 97 #define CLK_DIV_SCLK_SPI3_B 125 98 #define CLK_DIV_SCLK_SPI3_A 126 99 #define CLK_DIV_SCLK_I2S1 127 100 #define CLK_DIV_SCLK_PCM1 128 101 #define CLK_DIV_SCLK_AUDIO1 129 102 #define CLK_DIV_SCLK_AUDIO0 130 103 104 #define CLK_ACLK_PERIC_66 200 105 #define CLK_ACLK_PERIS_66 201 106 #define CLK_ACLK_FSYS_200 202 107 #define CLK_SCLK_MMC2_FSYS 203 108 #define CLK_SCLK_MMC1_FSYS 204 109 #define CLK_SCLK_MMC0_FSYS 205 110 #define CLK_SCLK_SPI4_PERIC 206 111 #define CLK_SCLK_SPI3_PERIC 207 112 #define CLK_SCLK_UART2_PERIC 208 113 #define CLK_SCLK_UART1_PERIC 209 114 #define CLK_SCLK_UART0_PERIC 210 115 #define CLK_SCLK_SPI2_PERIC 211 116 #define CLK_SCLK_SPI1_PERIC 212 117 #define CLK_SCLK_SPI0_PERIC 213 118 #define CLK_SCLK_SPDIF_PERIC 214 119 #define CLK_SCLK_I2S1_PERIC 215 120 #define CLK_SCLK_PCM1_PERIC 216 121 #define CLK_SCLK_SLIMBUS 217 122 #define CLK_SCLK_AUDIO1 218 123 #define CLK_SCLK_AUDIO0 219 124 125 #define TOP_NR_CLK 220 126 127 /* CMU_CPIF */ 128 #define CLK_FOUT_MPHY_PLL 1 129 130 #define CLK_MOUT_MPHY_PLL 2 131 132 #define CLK_DIV_SCLK_MPHY 10 133 134 #define CLK_SCLK_MPHY_PLL 11 135 #define CLK_SCLK_UFS_MPHY 11 136 137 #define CPIF_NR_CLK 12 138 139 /* CMU_MIF */ 140 #define CLK_FOUT_MEM0_PLL 1 141 #define CLK_FOUT_MEM1_PLL 2 142 #define CLK_FOUT_BUS_PLL 3 143 #define CLK_FOUT_MFC_PLL 4 144 145 #define MIF_NR_CLK 5 146 147 /* CMU_PERIC */ 148 #define CLK_PCLK_SPI2 1 149 #define CLK_PCLK_SPI1 2 150 #define CLK_PCLK_SPI0 3 151 #define CLK_PCLK_UART2 4 152 #define CLK_PCLK_UART1 5 153 #define CLK_PCLK_UART0 6 154 #define CLK_PCLK_HSI2C3 7 155 #define CLK_PCLK_HSI2C2 8 156 #define CLK_PCLK_HSI2C1 9 157 #define CLK_PCLK_HSI2C0 10 158 #define CLK_PCLK_I2C7 11 159 #define CLK_PCLK_I2C6 12 160 #define CLK_PCLK_I2C5 13 161 #define CLK_PCLK_I2C4 14 162 #define CLK_PCLK_I2C3 15 163 #define CLK_PCLK_I2C2 16 164 #define CLK_PCLK_I2C1 17 165 #define CLK_PCLK_I2C0 18 166 #define CLK_PCLK_SPI4 19 167 #define CLK_PCLK_SPI3 20 168 #define CLK_PCLK_HSI2C11 21 169 #define CLK_PCLK_HSI2C10 22 170 #define CLK_PCLK_HSI2C9 23 171 #define CLK_PCLK_HSI2C8 24 172 #define CLK_PCLK_HSI2C7 25 173 #define CLK_PCLK_HSI2C6 26 174 #define CLK_PCLK_HSI2C5 27 175 #define CLK_PCLK_HSI2C4 28 176 #define CLK_SCLK_SPI4 29 177 #define CLK_SCLK_SPI3 30 178 #define CLK_SCLK_SPI2 31 179 #define CLK_SCLK_SPI1 32 180 #define CLK_SCLK_SPI0 33 181 #define CLK_SCLK_UART2 34 182 #define CLK_SCLK_UART1 35 183 #define CLK_SCLK_UART0 36 184 #define CLK_ACLK_AHB2APB_PERIC2P 37 185 #define CLK_ACLK_AHB2APB_PERIC1P 38 186 #define CLK_ACLK_AHB2APB_PERIC0P 39 187 #define CLK_ACLK_PERICNP_66 40 188 #define CLK_PCLK_SCI 41 189 #define CLK_PCLK_GPIO_FINGER 42 190 #define CLK_PCLK_GPIO_ESE 43 191 #define CLK_PCLK_PWM 44 192 #define CLK_PCLK_SPDIF 45 193 #define CLK_PCLK_PCM1 46 194 #define CLK_PCLK_I2S1 47 195 #define CLK_PCLK_ADCIF 48 196 #define CLK_PCLK_GPIO_TOUCH 49 197 #define CLK_PCLK_GPIO_NFC 50 198 #define CLK_PCLK_GPIO_PERIC 51 199 #define CLK_PCLK_PMU_PERIC 52 200 #define CLK_PCLK_SYSREG_PERIC 53 201 #define CLK_SCLK_IOCLK_SPI4 54 202 #define CLK_SCLK_IOCLK_SPI3 55 203 #define CLK_SCLK_SCI 56 204 #define CLK_SCLK_SC_IN 57 205 #define CLK_SCLK_PWM 58 206 #define CLK_SCLK_IOCLK_SPI2 59 207 #define CLK_SCLK_IOCLK_SPI1 60 208 #define CLK_SCLK_IOCLK_SPI0 61 209 #define CLK_SCLK_IOCLK_I2S1_BCLK 62 210 #define CLK_SCLK_SPDIF 63 211 #define CLK_SCLK_PCM1 64 212 #define CLK_SCLK_I2S1 65 213 214 #define CLK_DIV_SCLK_SCI 70 215 #define CLK_DIV_SCLK_SC_IN 71 216 217 #define PERIC_NR_CLK 72 218 219 /* CMU_PERIS */ 220 #define CLK_PCLK_HPM_APBIF 1 221 #define CLK_PCLK_TMU1_APBIF 2 222 #define CLK_PCLK_TMU0_APBIF 3 223 #define CLK_PCLK_PMU_PERIS 4 224 #define CLK_PCLK_SYSREG_PERIS 5 225 #define CLK_PCLK_CMU_TOP_APBIF 6 226 #define CLK_PCLK_WDT_APOLLO 7 227 #define CLK_PCLK_WDT_ATLAS 8 228 #define CLK_PCLK_MCT 9 229 #define CLK_PCLK_HDMI_CEC 10 230 231 #define PERIS_NR_CLK 11 232 233 /* CMU_FSYS */ 234 #define CLK_MOUT_ACLK_FSYS_200_USER 1 235 #define CLK_MOUT_SCLK_MMC2_USER 2 236 #define CLK_MOUT_SCLK_MMC1_USER 3 237 #define CLK_MOUT_SCLK_MMC0_USER 4 238 239 #define CLK_ACLK_PCIE 50 240 #define CLK_ACLK_PDMA1 51 241 #define CLK_ACLK_TSI 52 242 #define CLK_ACLK_MMC2 53 243 #define CLK_ACLK_MMC1 54 244 #define CLK_ACLK_MMC0 55 245 #define CLK_ACLK_UFS 56 246 #define CLK_ACLK_USBHOST20 57 247 #define CLK_ACLK_USBHOST30 58 248 #define CLK_ACLK_USBDRD30 59 249 #define CLK_ACLK_PDMA0 60 250 #define CLK_SCLK_MMC2 61 251 #define CLK_SCLK_MMC1 62 252 #define CLK_SCLK_MMC0 63 253 #define CLK_PDMA1 64 254 #define CLK_PDMA0 65 255 256 #define FSYS_NR_CLK 66 257 258 #endif /* _DT_BINDINGS_CLOCK_EXYNOS5433_H */ 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