1 /* 2 * Copyright (c) 2014 Samsung Electronics Co., Ltd. 3 * Author: Chanwoo Choi <cw00.choi@samsung.com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 */ 9 10 #ifndef _DT_BINDINGS_CLOCK_EXYNOS5433_H 11 #define _DT_BINDINGS_CLOCK_EXYNOS5433_H 12 13 /* CMU_TOP */ 14 #define CLK_FOUT_ISP_PLL 1 15 #define CLK_FOUT_AUD_PLL 2 16 17 #define CLK_MOUT_AUD_PLL 10 18 #define CLK_MOUT_ISP_PLL 11 19 #define CLK_MOUT_AUD_PLL_USER_T 12 20 #define CLK_MOUT_MPHY_PLL_USER 13 21 #define CLK_MOUT_MFC_PLL_USER 14 22 #define CLK_MOUT_BUS_PLL_USER 15 23 #define CLK_MOUT_ACLK_HEVC_400 16 24 #define CLK_MOUT_ACLK_CAM1_333 17 25 #define CLK_MOUT_ACLK_CAM1_552_B 18 26 #define CLK_MOUT_ACLK_CAM1_552_A 19 27 #define CLK_MOUT_ACLK_ISP_DIS_400 20 28 #define CLK_MOUT_ACLK_ISP_400 21 29 #define CLK_MOUT_ACLK_BUS0_400 22 30 #define CLK_MOUT_ACLK_MSCL_400_B 23 31 #define CLK_MOUT_ACLK_MSCL_400_A 24 32 #define CLK_MOUT_ACLK_GSCL_333 25 33 #define CLK_MOUT_ACLK_G2D_400_B 26 34 #define CLK_MOUT_ACLK_G2D_400_A 27 35 #define CLK_MOUT_SCLK_JPEG_C 28 36 #define CLK_MOUT_SCLK_JPEG_B 29 37 #define CLK_MOUT_SCLK_JPEG_A 30 38 #define CLK_MOUT_SCLK_MMC2_B 31 39 #define CLK_MOUT_SCLK_MMC2_A 32 40 #define CLK_MOUT_SCLK_MMC1_B 33 41 #define CLK_MOUT_SCLK_MMC1_A 34 42 #define CLK_MOUT_SCLK_MMC0_D 35 43 #define CLK_MOUT_SCLK_MMC0_C 36 44 #define CLK_MOUT_SCLK_MMC0_B 37 45 #define CLK_MOUT_SCLK_MMC0_A 38 46 #define CLK_MOUT_SCLK_SPI4 39 47 #define CLK_MOUT_SCLK_SPI3 40 48 #define CLK_MOUT_SCLK_UART2 41 49 #define CLK_MOUT_SCLK_UART1 42 50 #define CLK_MOUT_SCLK_UART0 43 51 #define CLK_MOUT_SCLK_SPI2 44 52 #define CLK_MOUT_SCLK_SPI1 45 53 #define CLK_MOUT_SCLK_SPI0 46 54 #define CLK_MOUT_ACLK_MFC_400_C 47 55 #define CLK_MOUT_ACLK_MFC_400_B 48 56 #define CLK_MOUT_ACLK_MFC_400_A 49 57 #define CLK_MOUT_SCLK_ISP_SENSOR2 50 58 #define CLK_MOUT_SCLK_ISP_SENSOR1 51 59 #define CLK_MOUT_SCLK_ISP_SENSOR0 52 60 #define CLK_MOUT_SCLK_ISP_UART 53 61 #define CLK_MOUT_SCLK_ISP_SPI1 54 62 #define CLK_MOUT_SCLK_ISP_SPI0 55 63 #define CLK_MOUT_SCLK_PCIE_100 56 64 #define CLK_MOUT_SCLK_UFSUNIPRO 57 65 #define CLK_MOUT_SCLK_USBHOST30 58 66 #define CLK_MOUT_SCLK_USBDRD30 59 67 #define CLK_MOUT_SCLK_SLIMBUS 60 68 #define CLK_MOUT_SCLK_SPDIF 61 69 #define CLK_MOUT_SCLK_AUDIO1 62 70 #define CLK_MOUT_SCLK_AUDIO0 63 71 72 #define CLK_DIV_ACLK_FSYS_200 100 73 #define CLK_DIV_ACLK_IMEM_SSSX_266 101 74 #define CLK_DIV_ACLK_IMEM_200 102 75 #define CLK_DIV_ACLK_IMEM_266 103 76 #define CLK_DIV_ACLK_PERIC_66_B 104 77 #define CLK_DIV_ACLK_PERIC_66_A 105 78 #define CLK_DIV_ACLK_PERIS_66_B 106 79 #define CLK_DIV_ACLK_PERIS_66_A 107 80 #define CLK_DIV_SCLK_MMC1_B 108 81 #define CLK_DIV_SCLK_MMC1_A 109 82 #define CLK_DIV_SCLK_MMC0_B 110 83 #define CLK_DIV_SCLK_MMC0_A 111 84 #define CLK_DIV_SCLK_MMC2_B 112 85 #define CLK_DIV_SCLK_MMC2_A 113 86 #define CLK_DIV_SCLK_SPI1_B 114 87 #define CLK_DIV_SCLK_SPI1_A 115 88 #define CLK_DIV_SCLK_SPI0_B 116 89 #define CLK_DIV_SCLK_SPI0_A 117 90 #define CLK_DIV_SCLK_SPI2_B 118 91 #define CLK_DIV_SCLK_SPI2_A 119 92 #define CLK_DIV_SCLK_UART2 120 93 #define CLK_DIV_SCLK_UART1 121 94 #define CLK_DIV_SCLK_UART0 122 95 #define CLK_DIV_SCLK_SPI4_B 123 96 #define CLK_DIV_SCLK_SPI4_A 124 97 #define CLK_DIV_SCLK_SPI3_B 125 98 #define CLK_DIV_SCLK_SPI3_A 126 99 #define CLK_DIV_SCLK_I2S1 127 100 #define CLK_DIV_SCLK_PCM1 128 101 #define CLK_DIV_SCLK_AUDIO1 129 102 #define CLK_DIV_SCLK_AUDIO0 130 103 #define CLK_DIV_ACLK_GSCL_111 131 104 #define CLK_DIV_ACLK_GSCL_333 132 105 #define CLK_DIV_ACLK_HEVC_400 133 106 #define CLK_DIV_ACLK_MFC_400 134 107 #define CLK_DIV_ACLK_G2D_266 135 108 #define CLK_DIV_ACLK_G2D_400 136 109 110 #define CLK_ACLK_PERIC_66 200 111 #define CLK_ACLK_PERIS_66 201 112 #define CLK_ACLK_FSYS_200 202 113 #define CLK_SCLK_MMC2_FSYS 203 114 #define CLK_SCLK_MMC1_FSYS 204 115 #define CLK_SCLK_MMC0_FSYS 205 116 #define CLK_SCLK_SPI4_PERIC 206 117 #define CLK_SCLK_SPI3_PERIC 207 118 #define CLK_SCLK_UART2_PERIC 208 119 #define CLK_SCLK_UART1_PERIC 209 120 #define CLK_SCLK_UART0_PERIC 210 121 #define CLK_SCLK_SPI2_PERIC 211 122 #define CLK_SCLK_SPI1_PERIC 212 123 #define CLK_SCLK_SPI0_PERIC 213 124 #define CLK_SCLK_SPDIF_PERIC 214 125 #define CLK_SCLK_I2S1_PERIC 215 126 #define CLK_SCLK_PCM1_PERIC 216 127 #define CLK_SCLK_SLIMBUS 217 128 #define CLK_SCLK_AUDIO1 218 129 #define CLK_SCLK_AUDIO0 219 130 #define CLK_ACLK_G2D_266 220 131 #define CLK_ACLK_G2D_400 221 132 133 #define TOP_NR_CLK 222 134 135 /* CMU_CPIF */ 136 #define CLK_FOUT_MPHY_PLL 1 137 138 #define CLK_MOUT_MPHY_PLL 2 139 140 #define CLK_DIV_SCLK_MPHY 10 141 142 #define CLK_SCLK_MPHY_PLL 11 143 #define CLK_SCLK_UFS_MPHY 11 144 145 #define CPIF_NR_CLK 12 146 147 /* CMU_MIF */ 148 #define CLK_FOUT_MEM0_PLL 1 149 #define CLK_FOUT_MEM1_PLL 2 150 #define CLK_FOUT_BUS_PLL 3 151 #define CLK_FOUT_MFC_PLL 4 152 #define CLK_DOUT_MFC_PLL 5 153 #define CLK_DOUT_BUS_PLL 6 154 #define CLK_DOUT_MEM1_PLL 7 155 #define CLK_DOUT_MEM0_PLL 8 156 157 #define CLK_MOUT_MFC_PLL_DIV2 10 158 #define CLK_MOUT_BUS_PLL_DIV2 11 159 #define CLK_MOUT_MEM1_PLL_DIV2 12 160 #define CLK_MOUT_MEM0_PLL_DIV2 13 161 #define CLK_MOUT_MFC_PLL 14 162 #define CLK_MOUT_BUS_PLL 15 163 #define CLK_MOUT_MEM1_PLL 16 164 #define CLK_MOUT_MEM0_PLL 17 165 #define CLK_MOUT_CLK2X_PHY_C 18 166 #define CLK_MOUT_CLK2X_PHY_B 19 167 #define CLK_MOUT_CLK2X_PHY_A 20 168 #define CLK_MOUT_CLKM_PHY_C 21 169 #define CLK_MOUT_CLKM_PHY_B 22 170 #define CLK_MOUT_CLKM_PHY_A 23 171 #define CLK_MOUT_ACLK_MIFNM_200 24 172 #define CLK_MOUT_ACLK_MIFNM_400 25 173 #define CLK_MOUT_ACLK_DISP_333_B 26 174 #define CLK_MOUT_ACLK_DISP_333_A 27 175 #define CLK_MOUT_SCLK_DECON_VCLK_C 28 176 #define CLK_MOUT_SCLK_DECON_VCLK_B 29 177 #define CLK_MOUT_SCLK_DECON_VCLK_A 30 178 #define CLK_MOUT_SCLK_DECON_ECLK_C 31 179 #define CLK_MOUT_SCLK_DECON_ECLK_B 32 180 #define CLK_MOUT_SCLK_DECON_ECLK_A 33 181 #define CLK_MOUT_SCLK_DECON_TV_ECLK_C 34 182 #define CLK_MOUT_SCLK_DECON_TV_ECLK_B 35 183 #define CLK_MOUT_SCLK_DECON_TV_ECLK_A 36 184 #define CLK_MOUT_SCLK_DSD_C 37 185 #define CLK_MOUT_SCLK_DSD_B 38 186 #define CLK_MOUT_SCLK_DSD_A 39 187 #define CLK_MOUT_SCLK_DSIM0_C 40 188 #define CLK_MOUT_SCLK_DSIM0_B 41 189 #define CLK_MOUT_SCLK_DSIM0_A 42 190 #define CLK_MOUT_SCLK_DECON_TV_VCLK_C 46 191 #define CLK_MOUT_SCLK_DECON_TV_VCLK_B 47 192 #define CLK_MOUT_SCLK_DECON_TV_VCLK_A 48 193 #define CLK_MOUT_SCLK_DSIM1_C 49 194 #define CLK_MOUT_SCLK_DSIM1_B 50 195 #define CLK_MOUT_SCLK_DSIM1_A 51 196 197 #define CLK_DIV_SCLK_HPM_MIF 55 198 #define CLK_DIV_ACLK_DREX1 56 199 #define CLK_DIV_ACLK_DREX0 57 200 #define CLK_DIV_CLK2XPHY 58 201 #define CLK_DIV_ACLK_MIF_266 59 202 #define CLK_DIV_ACLK_MIFND_133 60 203 #define CLK_DIV_ACLK_MIF_133 61 204 #define CLK_DIV_ACLK_MIFNM_200 62 205 #define CLK_DIV_ACLK_MIF_200 63 206 #define CLK_DIV_ACLK_MIF_400 64 207 #define CLK_DIV_ACLK_BUS2_400 65 208 #define CLK_DIV_ACLK_DISP_333 66 209 #define CLK_DIV_ACLK_CPIF_200 67 210 #define CLK_DIV_SCLK_DSIM1 68 211 #define CLK_DIV_SCLK_DECON_TV_VCLK 69 212 #define CLK_DIV_SCLK_DSIM0 70 213 #define CLK_DIV_SCLK_DSD 71 214 #define CLK_DIV_SCLK_DECON_TV_ECLK 72 215 #define CLK_DIV_SCLK_DECON_VCLK 73 216 #define CLK_DIV_SCLK_DECON_ECLK 74 217 #define CLK_DIV_MIF_PRE 75 218 219 #define CLK_CLK2X_PHY1 80 220 #define CLK_CLK2X_PHY0 81 221 #define CLK_CLKM_PHY1 82 222 #define CLK_CLKM_PHY0 83 223 #define CLK_RCLK_DREX1 84 224 #define CLK_RCLK_DREX0 85 225 #define CLK_ACLK_DREX1_TZ 86 226 #define CLK_ACLK_DREX0_TZ 87 227 #define CLK_ACLK_DREX1_PEREV 88 228 #define CLK_ACLK_DREX0_PEREV 89 229 #define CLK_ACLK_DREX1_MEMIF 90 230 #define CLK_ACLK_DREX0_MEMIF 91 231 #define CLK_ACLK_DREX1_SCH 92 232 #define CLK_ACLK_DREX0_SCH 93 233 #define CLK_ACLK_DREX1_BUSIF 94 234 #define CLK_ACLK_DREX0_BUSIF 95 235 #define CLK_ACLK_DREX1_BUSIF_RD 96 236 #define CLK_ACLK_DREX0_BUSIF_RD 97 237 #define CLK_ACLK_DREX1 98 238 #define CLK_ACLK_DREX0 99 239 #define CLK_ACLK_ASYNCAXIM_ATLAS_CCIX 100 240 #define CLK_ACLK_ASYNCAXIS_ATLAS_MIF 101 241 #define CLK_ACLK_ASYNCAXIM_ATLAS_MIF 102 242 #define CLK_ACLK_ASYNCAXIS_MIF_IMEM 103 243 #define CLK_ACLK_ASYNCAXIS_NOC_P_CCI 104 244 #define CLK_ACLK_ASYNCAXIM_NOC_P_CCI 105 245 #define CLK_ACLK_ASYNCAXIS_CP1 106 246 #define CLK_ACLK_ASYNCAXIM_CP1 107 247 #define CLK_ACLK_ASYNCAXIS_CP0 108 248 #define CLK_ACLK_ASYNCAXIM_CP0 109 249 #define CLK_ACLK_ASYNCAXIS_DREX1_3 110 250 #define CLK_ACLK_ASYNCAXIM_DREX1_3 111 251 #define CLK_ACLK_ASYNCAXIS_DREX1_1 112 252 #define CLK_ACLK_ASYNCAXIM_DREX1_1 113 253 #define CLK_ACLK_ASYNCAXIS_DREX1_0 114 254 #define CLK_ACLK_ASYNCAXIM_DREX1_0 115 255 #define CLK_ACLK_ASYNCAXIS_DREX0_3 116 256 #define CLK_ACLK_ASYNCAXIM_DREX0_3 117 257 #define CLK_ACLK_ASYNCAXIS_DREX0_1 118 258 #define CLK_ACLK_ASYNCAXIM_DREX0_1 119 259 #define CLK_ACLK_ASYNCAXIS_DREX0_0 120 260 #define CLK_ACLK_ASYNCAXIM_DREX0_0 121 261 #define CLK_ACLK_AHB2APB_MIF2P 122 262 #define CLK_ACLK_AHB2APB_MIF1P 123 263 #define CLK_ACLK_AHB2APB_MIF0P 124 264 #define CLK_ACLK_IXIU_CCI 125 265 #define CLK_ACLK_XIU_MIFSFRX 126 266 #define CLK_ACLK_MIFNP_133 127 267 #define CLK_ACLK_MIFNM_200 128 268 #define CLK_ACLK_MIFND_133 129 269 #define CLK_ACLK_MIFND_400 130 270 #define CLK_ACLK_CCI 131 271 #define CLK_ACLK_MIFND_266 132 272 #define CLK_ACLK_PPMU_DREX1S3 133 273 #define CLK_ACLK_PPMU_DREX1S1 134 274 #define CLK_ACLK_PPMU_DREX1S0 135 275 #define CLK_ACLK_PPMU_DREX0S3 136 276 #define CLK_ACLK_PPMU_DREX0S1 137 277 #define CLK_ACLK_PPMU_DREX0S0 138 278 #define CLK_ACLK_BTS_APOLLO 139 279 #define CLK_ACLK_BTS_ATLAS 140 280 #define CLK_ACLK_ACE_SEL_APOLL 141 281 #define CLK_ACLK_ACE_SEL_ATLAS 142 282 #define CLK_ACLK_AXIDS_CCI_MIFSFRX 143 283 #define CLK_ACLK_AXIUS_ATLAS_CCI 144 284 #define CLK_ACLK_AXISYNCDNS_CCI 145 285 #define CLK_ACLK_AXISYNCDN_CCI 146 286 #define CLK_ACLK_AXISYNCDN_NOC_D 147 287 #define CLK_ACLK_ASYNCACEM_APOLLO_CCI 148 288 #define CLK_ACLK_ASYNCACEM_ATLAS_CCI 149 289 #define CLK_ACLK_ASYNCAPBS_MIF_CSSYS 150 290 #define CLK_ACLK_BUS2_400 151 291 #define CLK_ACLK_DISP_333 152 292 #define CLK_ACLK_CPIF_200 153 293 #define CLK_PCLK_PPMU_DREX1S3 154 294 #define CLK_PCLK_PPMU_DREX1S1 155 295 #define CLK_PCLK_PPMU_DREX1S0 156 296 #define CLK_PCLK_PPMU_DREX0S3 157 297 #define CLK_PCLK_PPMU_DREX0S1 158 298 #define CLK_PCLK_PPMU_DREX0S0 159 299 #define CLK_PCLK_BTS_APOLLO 160 300 #define CLK_PCLK_BTS_ATLAS 161 301 #define CLK_PCLK_ASYNCAXI_NOC_P_CCI 162 302 #define CLK_PCLK_ASYNCAXI_CP1 163 303 #define CLK_PCLK_ASYNCAXI_CP0 164 304 #define CLK_PCLK_ASYNCAXI_DREX1_3 165 305 #define CLK_PCLK_ASYNCAXI_DREX1_1 166 306 #define CLK_PCLK_ASYNCAXI_DREX1_0 167 307 #define CLK_PCLK_ASYNCAXI_DREX0_3 168 308 #define CLK_PCLK_ASYNCAXI_DREX0_1 169 309 #define CLK_PCLK_ASYNCAXI_DREX0_0 170 310 #define CLK_PCLK_MIFSRVND_133 171 311 #define CLK_PCLK_PMU_MIF 172 312 #define CLK_PCLK_SYSREG_MIF 173 313 #define CLK_PCLK_GPIO_ALIVE 174 314 #define CLK_PCLK_ABB 175 315 #define CLK_PCLK_PMU_APBIF 176 316 #define CLK_PCLK_DDR_PHY1 177 317 #define CLK_PCLK_DREX1 178 318 #define CLK_PCLK_DDR_PHY0 179 319 #define CLK_PCLK_DREX0 180 320 #define CLK_PCLK_DREX0_TZ 181 321 #define CLK_PCLK_DREX1_TZ 182 322 #define CLK_PCLK_MONOTONIC_CNT 183 323 #define CLK_PCLK_RTC 184 324 #define CLK_SCLK_DSIM1_DISP 185 325 #define CLK_SCLK_DECON_TV_VCLK_DISP 186 326 #define CLK_SCLK_FREQ_DET_BUS_PLL 187 327 #define CLK_SCLK_FREQ_DET_MFC_PLL 188 328 #define CLK_SCLK_FREQ_DET_MEM0_PLL 189 329 #define CLK_SCLK_FREQ_DET_MEM1_PLL 190 330 #define CLK_SCLK_DSIM0_DISP 191 331 #define CLK_SCLK_DSD_DISP 192 332 #define CLK_SCLK_DECON_TV_ECLK_DISP 193 333 #define CLK_SCLK_DECON_VCLK_DISP 194 334 #define CLK_SCLK_DECON_ECLK_DISP 195 335 #define CLK_SCLK_HPM_MIF 196 336 #define CLK_SCLK_MFC_PLL 197 337 #define CLK_SCLK_BUS_PLL 198 338 #define CLK_SCLK_BUS_PLL_APOLLO 199 339 #define CLK_SCLK_BUS_PLL_ATLAS 200 340 341 #define MIF_NR_CLK 201 342 343 /* CMU_PERIC */ 344 #define CLK_PCLK_SPI2 1 345 #define CLK_PCLK_SPI1 2 346 #define CLK_PCLK_SPI0 3 347 #define CLK_PCLK_UART2 4 348 #define CLK_PCLK_UART1 5 349 #define CLK_PCLK_UART0 6 350 #define CLK_PCLK_HSI2C3 7 351 #define CLK_PCLK_HSI2C2 8 352 #define CLK_PCLK_HSI2C1 9 353 #define CLK_PCLK_HSI2C0 10 354 #define CLK_PCLK_I2C7 11 355 #define CLK_PCLK_I2C6 12 356 #define CLK_PCLK_I2C5 13 357 #define CLK_PCLK_I2C4 14 358 #define CLK_PCLK_I2C3 15 359 #define CLK_PCLK_I2C2 16 360 #define CLK_PCLK_I2C1 17 361 #define CLK_PCLK_I2C0 18 362 #define CLK_PCLK_SPI4 19 363 #define CLK_PCLK_SPI3 20 364 #define CLK_PCLK_HSI2C11 21 365 #define CLK_PCLK_HSI2C10 22 366 #define CLK_PCLK_HSI2C9 23 367 #define CLK_PCLK_HSI2C8 24 368 #define CLK_PCLK_HSI2C7 25 369 #define CLK_PCLK_HSI2C6 26 370 #define CLK_PCLK_HSI2C5 27 371 #define CLK_PCLK_HSI2C4 28 372 #define CLK_SCLK_SPI4 29 373 #define CLK_SCLK_SPI3 30 374 #define CLK_SCLK_SPI2 31 375 #define CLK_SCLK_SPI1 32 376 #define CLK_SCLK_SPI0 33 377 #define CLK_SCLK_UART2 34 378 #define CLK_SCLK_UART1 35 379 #define CLK_SCLK_UART0 36 380 #define CLK_ACLK_AHB2APB_PERIC2P 37 381 #define CLK_ACLK_AHB2APB_PERIC1P 38 382 #define CLK_ACLK_AHB2APB_PERIC0P 39 383 #define CLK_ACLK_PERICNP_66 40 384 #define CLK_PCLK_SCI 41 385 #define CLK_PCLK_GPIO_FINGER 42 386 #define CLK_PCLK_GPIO_ESE 43 387 #define CLK_PCLK_PWM 44 388 #define CLK_PCLK_SPDIF 45 389 #define CLK_PCLK_PCM1 46 390 #define CLK_PCLK_I2S1 47 391 #define CLK_PCLK_ADCIF 48 392 #define CLK_PCLK_GPIO_TOUCH 49 393 #define CLK_PCLK_GPIO_NFC 50 394 #define CLK_PCLK_GPIO_PERIC 51 395 #define CLK_PCLK_PMU_PERIC 52 396 #define CLK_PCLK_SYSREG_PERIC 53 397 #define CLK_SCLK_IOCLK_SPI4 54 398 #define CLK_SCLK_IOCLK_SPI3 55 399 #define CLK_SCLK_SCI 56 400 #define CLK_SCLK_SC_IN 57 401 #define CLK_SCLK_PWM 58 402 #define CLK_SCLK_IOCLK_SPI2 59 403 #define CLK_SCLK_IOCLK_SPI1 60 404 #define CLK_SCLK_IOCLK_SPI0 61 405 #define CLK_SCLK_IOCLK_I2S1_BCLK 62 406 #define CLK_SCLK_SPDIF 63 407 #define CLK_SCLK_PCM1 64 408 #define CLK_SCLK_I2S1 65 409 410 #define CLK_DIV_SCLK_SCI 70 411 #define CLK_DIV_SCLK_SC_IN 71 412 413 #define PERIC_NR_CLK 72 414 415 /* CMU_PERIS */ 416 #define CLK_PCLK_HPM_APBIF 1 417 #define CLK_PCLK_TMU1_APBIF 2 418 #define CLK_PCLK_TMU0_APBIF 3 419 #define CLK_PCLK_PMU_PERIS 4 420 #define CLK_PCLK_SYSREG_PERIS 5 421 #define CLK_PCLK_CMU_TOP_APBIF 6 422 #define CLK_PCLK_WDT_APOLLO 7 423 #define CLK_PCLK_WDT_ATLAS 8 424 #define CLK_PCLK_MCT 9 425 #define CLK_PCLK_HDMI_CEC 10 426 #define CLK_ACLK_AHB2APB_PERIS1P 11 427 #define CLK_ACLK_AHB2APB_PERIS0P 12 428 #define CLK_ACLK_PERISNP_66 13 429 #define CLK_PCLK_TZPC12 14 430 #define CLK_PCLK_TZPC11 15 431 #define CLK_PCLK_TZPC10 16 432 #define CLK_PCLK_TZPC9 17 433 #define CLK_PCLK_TZPC8 18 434 #define CLK_PCLK_TZPC7 19 435 #define CLK_PCLK_TZPC6 20 436 #define CLK_PCLK_TZPC5 21 437 #define CLK_PCLK_TZPC4 22 438 #define CLK_PCLK_TZPC3 23 439 #define CLK_PCLK_TZPC2 24 440 #define CLK_PCLK_TZPC1 25 441 #define CLK_PCLK_TZPC0 26 442 #define CLK_PCLK_SECKEY_APBIF 27 443 #define CLK_PCLK_CHIPID_APBIF 28 444 #define CLK_PCLK_TOPRTC 29 445 #define CLK_PCLK_CUSTOM_EFUSE_APBIF 30 446 #define CLK_PCLK_ANTIRBK_CNT_APBIF 31 447 #define CLK_PCLK_OTP_CON_APBIF 32 448 #define CLK_SCLK_ASV_TB 33 449 #define CLK_SCLK_TMU1 34 450 #define CLK_SCLK_TMU0 35 451 #define CLK_SCLK_SECKEY 36 452 #define CLK_SCLK_CHIPID 37 453 #define CLK_SCLK_TOPRTC 38 454 #define CLK_SCLK_CUSTOM_EFUSE 39 455 #define CLK_SCLK_ANTIRBK_CNT 40 456 #define CLK_SCLK_OTP_CON 41 457 458 #define PERIS_NR_CLK 42 459 460 /* CMU_FSYS */ 461 #define CLK_MOUT_ACLK_FSYS_200_USER 1 462 #define CLK_MOUT_SCLK_MMC2_USER 2 463 #define CLK_MOUT_SCLK_MMC1_USER 3 464 #define CLK_MOUT_SCLK_MMC0_USER 4 465 466 #define CLK_ACLK_PCIE 50 467 #define CLK_ACLK_PDMA1 51 468 #define CLK_ACLK_TSI 52 469 #define CLK_ACLK_MMC2 53 470 #define CLK_ACLK_MMC1 54 471 #define CLK_ACLK_MMC0 55 472 #define CLK_ACLK_UFS 56 473 #define CLK_ACLK_USBHOST20 57 474 #define CLK_ACLK_USBHOST30 58 475 #define CLK_ACLK_USBDRD30 59 476 #define CLK_ACLK_PDMA0 60 477 #define CLK_SCLK_MMC2 61 478 #define CLK_SCLK_MMC1 62 479 #define CLK_SCLK_MMC0 63 480 #define CLK_PDMA1 64 481 #define CLK_PDMA0 65 482 483 #define FSYS_NR_CLK 66 484 485 /* CMU_G2D */ 486 #define CLK_MUX_ACLK_G2D_266_USER 1 487 #define CLK_MUX_ACLK_G2D_400_USER 2 488 489 #define CLK_DIV_PCLK_G2D 3 490 491 #define CLK_ACLK_SMMU_MDMA1 4 492 #define CLK_ACLK_BTS_MDMA1 5 493 #define CLK_ACLK_BTS_G2D 6 494 #define CLK_ACLK_ALB_G2D 7 495 #define CLK_ACLK_AXIUS_G2DX 8 496 #define CLK_ACLK_ASYNCAXI_SYSX 9 497 #define CLK_ACLK_AHB2APB_G2D1P 10 498 #define CLK_ACLK_AHB2APB_G2D0P 11 499 #define CLK_ACLK_XIU_G2DX 12 500 #define CLK_ACLK_G2DNP_133 13 501 #define CLK_ACLK_G2DND_400 14 502 #define CLK_ACLK_MDMA1 15 503 #define CLK_ACLK_G2D 16 504 #define CLK_ACLK_SMMU_G2D 17 505 #define CLK_PCLK_SMMU_MDMA1 18 506 #define CLK_PCLK_BTS_MDMA1 19 507 #define CLK_PCLK_BTS_G2D 20 508 #define CLK_PCLK_ALB_G2D 21 509 #define CLK_PCLK_ASYNCAXI_SYSX 22 510 #define CLK_PCLK_PMU_G2D 23 511 #define CLK_PCLK_SYSREG_G2D 24 512 #define CLK_PCLK_G2D 25 513 #define CLK_PCLK_SMMU_G2D 26 514 515 #define G2D_NR_CLK 27 516 517 #endif /* _DT_BINDINGS_CLOCK_EXYNOS5433_H */ 518