1 /* 2 * Copyright (c) 2014 Samsung Electronics Co., Ltd. 3 * Author: Chanwoo Choi <cw00.choi@samsung.com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 */ 9 10 #ifndef _DT_BINDINGS_CLOCK_EXYNOS5433_H 11 #define _DT_BINDINGS_CLOCK_EXYNOS5433_H 12 13 /* CMU_TOP */ 14 #define CLK_FOUT_ISP_PLL 1 15 #define CLK_FOUT_AUD_PLL 2 16 17 #define CLK_MOUT_AUD_PLL 10 18 #define CLK_MOUT_ISP_PLL 11 19 #define CLK_MOUT_AUD_PLL_USER_T 12 20 #define CLK_MOUT_MPHY_PLL_USER 13 21 #define CLK_MOUT_MFC_PLL_USER 14 22 #define CLK_MOUT_BUS_PLL_USER 15 23 #define CLK_MOUT_ACLK_HEVC_400 16 24 #define CLK_MOUT_ACLK_CAM1_333 17 25 #define CLK_MOUT_ACLK_CAM1_552_B 18 26 #define CLK_MOUT_ACLK_CAM1_552_A 19 27 #define CLK_MOUT_ACLK_ISP_DIS_400 20 28 #define CLK_MOUT_ACLK_ISP_400 21 29 #define CLK_MOUT_ACLK_BUS0_400 22 30 #define CLK_MOUT_ACLK_MSCL_400_B 23 31 #define CLK_MOUT_ACLK_MSCL_400_A 24 32 #define CLK_MOUT_ACLK_GSCL_333 25 33 #define CLK_MOUT_ACLK_G2D_400_B 26 34 #define CLK_MOUT_ACLK_G2D_400_A 27 35 #define CLK_MOUT_SCLK_JPEG_C 28 36 #define CLK_MOUT_SCLK_JPEG_B 29 37 #define CLK_MOUT_SCLK_JPEG_A 30 38 #define CLK_MOUT_SCLK_MMC2_B 31 39 #define CLK_MOUT_SCLK_MMC2_A 32 40 #define CLK_MOUT_SCLK_MMC1_B 33 41 #define CLK_MOUT_SCLK_MMC1_A 34 42 #define CLK_MOUT_SCLK_MMC0_D 35 43 #define CLK_MOUT_SCLK_MMC0_C 36 44 #define CLK_MOUT_SCLK_MMC0_B 37 45 #define CLK_MOUT_SCLK_MMC0_A 38 46 #define CLK_MOUT_SCLK_SPI4 39 47 #define CLK_MOUT_SCLK_SPI3 40 48 #define CLK_MOUT_SCLK_UART2 41 49 #define CLK_MOUT_SCLK_UART1 42 50 #define CLK_MOUT_SCLK_UART0 43 51 #define CLK_MOUT_SCLK_SPI2 44 52 #define CLK_MOUT_SCLK_SPI1 45 53 #define CLK_MOUT_SCLK_SPI0 46 54 #define CLK_MOUT_ACLK_MFC_400_C 47 55 #define CLK_MOUT_ACLK_MFC_400_B 48 56 #define CLK_MOUT_ACLK_MFC_400_A 49 57 #define CLK_MOUT_SCLK_ISP_SENSOR2 50 58 #define CLK_MOUT_SCLK_ISP_SENSOR1 51 59 #define CLK_MOUT_SCLK_ISP_SENSOR0 52 60 #define CLK_MOUT_SCLK_ISP_UART 53 61 #define CLK_MOUT_SCLK_ISP_SPI1 54 62 #define CLK_MOUT_SCLK_ISP_SPI0 55 63 #define CLK_MOUT_SCLK_PCIE_100 56 64 #define CLK_MOUT_SCLK_UFSUNIPRO 57 65 #define CLK_MOUT_SCLK_USBHOST30 58 66 #define CLK_MOUT_SCLK_USBDRD30 59 67 #define CLK_MOUT_SCLK_SLIMBUS 60 68 #define CLK_MOUT_SCLK_SPDIF 61 69 #define CLK_MOUT_SCLK_AUDIO1 62 70 #define CLK_MOUT_SCLK_AUDIO0 63 71 #define CLK_MOUT_SCLK_HDMI_SPDIF 64 72 73 #define CLK_DIV_ACLK_FSYS_200 100 74 #define CLK_DIV_ACLK_IMEM_SSSX_266 101 75 #define CLK_DIV_ACLK_IMEM_200 102 76 #define CLK_DIV_ACLK_IMEM_266 103 77 #define CLK_DIV_ACLK_PERIC_66_B 104 78 #define CLK_DIV_ACLK_PERIC_66_A 105 79 #define CLK_DIV_ACLK_PERIS_66_B 106 80 #define CLK_DIV_ACLK_PERIS_66_A 107 81 #define CLK_DIV_SCLK_MMC1_B 108 82 #define CLK_DIV_SCLK_MMC1_A 109 83 #define CLK_DIV_SCLK_MMC0_B 110 84 #define CLK_DIV_SCLK_MMC0_A 111 85 #define CLK_DIV_SCLK_MMC2_B 112 86 #define CLK_DIV_SCLK_MMC2_A 113 87 #define CLK_DIV_SCLK_SPI1_B 114 88 #define CLK_DIV_SCLK_SPI1_A 115 89 #define CLK_DIV_SCLK_SPI0_B 116 90 #define CLK_DIV_SCLK_SPI0_A 117 91 #define CLK_DIV_SCLK_SPI2_B 118 92 #define CLK_DIV_SCLK_SPI2_A 119 93 #define CLK_DIV_SCLK_UART2 120 94 #define CLK_DIV_SCLK_UART1 121 95 #define CLK_DIV_SCLK_UART0 122 96 #define CLK_DIV_SCLK_SPI4_B 123 97 #define CLK_DIV_SCLK_SPI4_A 124 98 #define CLK_DIV_SCLK_SPI3_B 125 99 #define CLK_DIV_SCLK_SPI3_A 126 100 #define CLK_DIV_SCLK_I2S1 127 101 #define CLK_DIV_SCLK_PCM1 128 102 #define CLK_DIV_SCLK_AUDIO1 129 103 #define CLK_DIV_SCLK_AUDIO0 130 104 #define CLK_DIV_ACLK_GSCL_111 131 105 #define CLK_DIV_ACLK_GSCL_333 132 106 #define CLK_DIV_ACLK_HEVC_400 133 107 #define CLK_DIV_ACLK_MFC_400 134 108 #define CLK_DIV_ACLK_G2D_266 135 109 #define CLK_DIV_ACLK_G2D_400 136 110 #define CLK_DIV_ACLK_G3D_400 137 111 #define CLK_DIV_ACLK_BUS0_400 138 112 #define CLK_DIV_ACLK_BUS1_400 139 113 114 #define CLK_ACLK_PERIC_66 200 115 #define CLK_ACLK_PERIS_66 201 116 #define CLK_ACLK_FSYS_200 202 117 #define CLK_SCLK_MMC2_FSYS 203 118 #define CLK_SCLK_MMC1_FSYS 204 119 #define CLK_SCLK_MMC0_FSYS 205 120 #define CLK_SCLK_SPI4_PERIC 206 121 #define CLK_SCLK_SPI3_PERIC 207 122 #define CLK_SCLK_UART2_PERIC 208 123 #define CLK_SCLK_UART1_PERIC 209 124 #define CLK_SCLK_UART0_PERIC 210 125 #define CLK_SCLK_SPI2_PERIC 211 126 #define CLK_SCLK_SPI1_PERIC 212 127 #define CLK_SCLK_SPI0_PERIC 213 128 #define CLK_SCLK_SPDIF_PERIC 214 129 #define CLK_SCLK_I2S1_PERIC 215 130 #define CLK_SCLK_PCM1_PERIC 216 131 #define CLK_SCLK_SLIMBUS 217 132 #define CLK_SCLK_AUDIO1 218 133 #define CLK_SCLK_AUDIO0 219 134 #define CLK_ACLK_G2D_266 220 135 #define CLK_ACLK_G2D_400 221 136 #define CLK_ACLK_G3D_400 222 137 #define CLK_ACLK_IMEM_SSX_266 223 138 #define CLK_ACLK_BUS0_400 224 139 #define CLK_ACLK_BUS1_400 225 140 #define CLK_ACLK_IMEM_200 226 141 #define CLK_ACLK_IMEM_266 227 142 143 #define TOP_NR_CLK 228 144 145 /* CMU_CPIF */ 146 #define CLK_FOUT_MPHY_PLL 1 147 148 #define CLK_MOUT_MPHY_PLL 2 149 150 #define CLK_DIV_SCLK_MPHY 10 151 152 #define CLK_SCLK_MPHY_PLL 11 153 #define CLK_SCLK_UFS_MPHY 11 154 155 #define CPIF_NR_CLK 12 156 157 /* CMU_MIF */ 158 #define CLK_FOUT_MEM0_PLL 1 159 #define CLK_FOUT_MEM1_PLL 2 160 #define CLK_FOUT_BUS_PLL 3 161 #define CLK_FOUT_MFC_PLL 4 162 #define CLK_DOUT_MFC_PLL 5 163 #define CLK_DOUT_BUS_PLL 6 164 #define CLK_DOUT_MEM1_PLL 7 165 #define CLK_DOUT_MEM0_PLL 8 166 167 #define CLK_MOUT_MFC_PLL_DIV2 10 168 #define CLK_MOUT_BUS_PLL_DIV2 11 169 #define CLK_MOUT_MEM1_PLL_DIV2 12 170 #define CLK_MOUT_MEM0_PLL_DIV2 13 171 #define CLK_MOUT_MFC_PLL 14 172 #define CLK_MOUT_BUS_PLL 15 173 #define CLK_MOUT_MEM1_PLL 16 174 #define CLK_MOUT_MEM0_PLL 17 175 #define CLK_MOUT_CLK2X_PHY_C 18 176 #define CLK_MOUT_CLK2X_PHY_B 19 177 #define CLK_MOUT_CLK2X_PHY_A 20 178 #define CLK_MOUT_CLKM_PHY_C 21 179 #define CLK_MOUT_CLKM_PHY_B 22 180 #define CLK_MOUT_CLKM_PHY_A 23 181 #define CLK_MOUT_ACLK_MIFNM_200 24 182 #define CLK_MOUT_ACLK_MIFNM_400 25 183 #define CLK_MOUT_ACLK_DISP_333_B 26 184 #define CLK_MOUT_ACLK_DISP_333_A 27 185 #define CLK_MOUT_SCLK_DECON_VCLK_C 28 186 #define CLK_MOUT_SCLK_DECON_VCLK_B 29 187 #define CLK_MOUT_SCLK_DECON_VCLK_A 30 188 #define CLK_MOUT_SCLK_DECON_ECLK_C 31 189 #define CLK_MOUT_SCLK_DECON_ECLK_B 32 190 #define CLK_MOUT_SCLK_DECON_ECLK_A 33 191 #define CLK_MOUT_SCLK_DECON_TV_ECLK_C 34 192 #define CLK_MOUT_SCLK_DECON_TV_ECLK_B 35 193 #define CLK_MOUT_SCLK_DECON_TV_ECLK_A 36 194 #define CLK_MOUT_SCLK_DSD_C 37 195 #define CLK_MOUT_SCLK_DSD_B 38 196 #define CLK_MOUT_SCLK_DSD_A 39 197 #define CLK_MOUT_SCLK_DSIM0_C 40 198 #define CLK_MOUT_SCLK_DSIM0_B 41 199 #define CLK_MOUT_SCLK_DSIM0_A 42 200 #define CLK_MOUT_SCLK_DECON_TV_VCLK_C 46 201 #define CLK_MOUT_SCLK_DECON_TV_VCLK_B 47 202 #define CLK_MOUT_SCLK_DECON_TV_VCLK_A 48 203 #define CLK_MOUT_SCLK_DSIM1_C 49 204 #define CLK_MOUT_SCLK_DSIM1_B 50 205 #define CLK_MOUT_SCLK_DSIM1_A 51 206 207 #define CLK_DIV_SCLK_HPM_MIF 55 208 #define CLK_DIV_ACLK_DREX1 56 209 #define CLK_DIV_ACLK_DREX0 57 210 #define CLK_DIV_CLK2XPHY 58 211 #define CLK_DIV_ACLK_MIF_266 59 212 #define CLK_DIV_ACLK_MIFND_133 60 213 #define CLK_DIV_ACLK_MIF_133 61 214 #define CLK_DIV_ACLK_MIFNM_200 62 215 #define CLK_DIV_ACLK_MIF_200 63 216 #define CLK_DIV_ACLK_MIF_400 64 217 #define CLK_DIV_ACLK_BUS2_400 65 218 #define CLK_DIV_ACLK_DISP_333 66 219 #define CLK_DIV_ACLK_CPIF_200 67 220 #define CLK_DIV_SCLK_DSIM1 68 221 #define CLK_DIV_SCLK_DECON_TV_VCLK 69 222 #define CLK_DIV_SCLK_DSIM0 70 223 #define CLK_DIV_SCLK_DSD 71 224 #define CLK_DIV_SCLK_DECON_TV_ECLK 72 225 #define CLK_DIV_SCLK_DECON_VCLK 73 226 #define CLK_DIV_SCLK_DECON_ECLK 74 227 #define CLK_DIV_MIF_PRE 75 228 229 #define CLK_CLK2X_PHY1 80 230 #define CLK_CLK2X_PHY0 81 231 #define CLK_CLKM_PHY1 82 232 #define CLK_CLKM_PHY0 83 233 #define CLK_RCLK_DREX1 84 234 #define CLK_RCLK_DREX0 85 235 #define CLK_ACLK_DREX1_TZ 86 236 #define CLK_ACLK_DREX0_TZ 87 237 #define CLK_ACLK_DREX1_PEREV 88 238 #define CLK_ACLK_DREX0_PEREV 89 239 #define CLK_ACLK_DREX1_MEMIF 90 240 #define CLK_ACLK_DREX0_MEMIF 91 241 #define CLK_ACLK_DREX1_SCH 92 242 #define CLK_ACLK_DREX0_SCH 93 243 #define CLK_ACLK_DREX1_BUSIF 94 244 #define CLK_ACLK_DREX0_BUSIF 95 245 #define CLK_ACLK_DREX1_BUSIF_RD 96 246 #define CLK_ACLK_DREX0_BUSIF_RD 97 247 #define CLK_ACLK_DREX1 98 248 #define CLK_ACLK_DREX0 99 249 #define CLK_ACLK_ASYNCAXIM_ATLAS_CCIX 100 250 #define CLK_ACLK_ASYNCAXIS_ATLAS_MIF 101 251 #define CLK_ACLK_ASYNCAXIM_ATLAS_MIF 102 252 #define CLK_ACLK_ASYNCAXIS_MIF_IMEM 103 253 #define CLK_ACLK_ASYNCAXIS_NOC_P_CCI 104 254 #define CLK_ACLK_ASYNCAXIM_NOC_P_CCI 105 255 #define CLK_ACLK_ASYNCAXIS_CP1 106 256 #define CLK_ACLK_ASYNCAXIM_CP1 107 257 #define CLK_ACLK_ASYNCAXIS_CP0 108 258 #define CLK_ACLK_ASYNCAXIM_CP0 109 259 #define CLK_ACLK_ASYNCAXIS_DREX1_3 110 260 #define CLK_ACLK_ASYNCAXIM_DREX1_3 111 261 #define CLK_ACLK_ASYNCAXIS_DREX1_1 112 262 #define CLK_ACLK_ASYNCAXIM_DREX1_1 113 263 #define CLK_ACLK_ASYNCAXIS_DREX1_0 114 264 #define CLK_ACLK_ASYNCAXIM_DREX1_0 115 265 #define CLK_ACLK_ASYNCAXIS_DREX0_3 116 266 #define CLK_ACLK_ASYNCAXIM_DREX0_3 117 267 #define CLK_ACLK_ASYNCAXIS_DREX0_1 118 268 #define CLK_ACLK_ASYNCAXIM_DREX0_1 119 269 #define CLK_ACLK_ASYNCAXIS_DREX0_0 120 270 #define CLK_ACLK_ASYNCAXIM_DREX0_0 121 271 #define CLK_ACLK_AHB2APB_MIF2P 122 272 #define CLK_ACLK_AHB2APB_MIF1P 123 273 #define CLK_ACLK_AHB2APB_MIF0P 124 274 #define CLK_ACLK_IXIU_CCI 125 275 #define CLK_ACLK_XIU_MIFSFRX 126 276 #define CLK_ACLK_MIFNP_133 127 277 #define CLK_ACLK_MIFNM_200 128 278 #define CLK_ACLK_MIFND_133 129 279 #define CLK_ACLK_MIFND_400 130 280 #define CLK_ACLK_CCI 131 281 #define CLK_ACLK_MIFND_266 132 282 #define CLK_ACLK_PPMU_DREX1S3 133 283 #define CLK_ACLK_PPMU_DREX1S1 134 284 #define CLK_ACLK_PPMU_DREX1S0 135 285 #define CLK_ACLK_PPMU_DREX0S3 136 286 #define CLK_ACLK_PPMU_DREX0S1 137 287 #define CLK_ACLK_PPMU_DREX0S0 138 288 #define CLK_ACLK_BTS_APOLLO 139 289 #define CLK_ACLK_BTS_ATLAS 140 290 #define CLK_ACLK_ACE_SEL_APOLL 141 291 #define CLK_ACLK_ACE_SEL_ATLAS 142 292 #define CLK_ACLK_AXIDS_CCI_MIFSFRX 143 293 #define CLK_ACLK_AXIUS_ATLAS_CCI 144 294 #define CLK_ACLK_AXISYNCDNS_CCI 145 295 #define CLK_ACLK_AXISYNCDN_CCI 146 296 #define CLK_ACLK_AXISYNCDN_NOC_D 147 297 #define CLK_ACLK_ASYNCACEM_APOLLO_CCI 148 298 #define CLK_ACLK_ASYNCACEM_ATLAS_CCI 149 299 #define CLK_ACLK_ASYNCAPBS_MIF_CSSYS 150 300 #define CLK_ACLK_BUS2_400 151 301 #define CLK_ACLK_DISP_333 152 302 #define CLK_ACLK_CPIF_200 153 303 #define CLK_PCLK_PPMU_DREX1S3 154 304 #define CLK_PCLK_PPMU_DREX1S1 155 305 #define CLK_PCLK_PPMU_DREX1S0 156 306 #define CLK_PCLK_PPMU_DREX0S3 157 307 #define CLK_PCLK_PPMU_DREX0S1 158 308 #define CLK_PCLK_PPMU_DREX0S0 159 309 #define CLK_PCLK_BTS_APOLLO 160 310 #define CLK_PCLK_BTS_ATLAS 161 311 #define CLK_PCLK_ASYNCAXI_NOC_P_CCI 162 312 #define CLK_PCLK_ASYNCAXI_CP1 163 313 #define CLK_PCLK_ASYNCAXI_CP0 164 314 #define CLK_PCLK_ASYNCAXI_DREX1_3 165 315 #define CLK_PCLK_ASYNCAXI_DREX1_1 166 316 #define CLK_PCLK_ASYNCAXI_DREX1_0 167 317 #define CLK_PCLK_ASYNCAXI_DREX0_3 168 318 #define CLK_PCLK_ASYNCAXI_DREX0_1 169 319 #define CLK_PCLK_ASYNCAXI_DREX0_0 170 320 #define CLK_PCLK_MIFSRVND_133 171 321 #define CLK_PCLK_PMU_MIF 172 322 #define CLK_PCLK_SYSREG_MIF 173 323 #define CLK_PCLK_GPIO_ALIVE 174 324 #define CLK_PCLK_ABB 175 325 #define CLK_PCLK_PMU_APBIF 176 326 #define CLK_PCLK_DDR_PHY1 177 327 #define CLK_PCLK_DREX1 178 328 #define CLK_PCLK_DDR_PHY0 179 329 #define CLK_PCLK_DREX0 180 330 #define CLK_PCLK_DREX0_TZ 181 331 #define CLK_PCLK_DREX1_TZ 182 332 #define CLK_PCLK_MONOTONIC_CNT 183 333 #define CLK_PCLK_RTC 184 334 #define CLK_SCLK_DSIM1_DISP 185 335 #define CLK_SCLK_DECON_TV_VCLK_DISP 186 336 #define CLK_SCLK_FREQ_DET_BUS_PLL 187 337 #define CLK_SCLK_FREQ_DET_MFC_PLL 188 338 #define CLK_SCLK_FREQ_DET_MEM0_PLL 189 339 #define CLK_SCLK_FREQ_DET_MEM1_PLL 190 340 #define CLK_SCLK_DSIM0_DISP 191 341 #define CLK_SCLK_DSD_DISP 192 342 #define CLK_SCLK_DECON_TV_ECLK_DISP 193 343 #define CLK_SCLK_DECON_VCLK_DISP 194 344 #define CLK_SCLK_DECON_ECLK_DISP 195 345 #define CLK_SCLK_HPM_MIF 196 346 #define CLK_SCLK_MFC_PLL 197 347 #define CLK_SCLK_BUS_PLL 198 348 #define CLK_SCLK_BUS_PLL_APOLLO 199 349 #define CLK_SCLK_BUS_PLL_ATLAS 200 350 #define CLK_SCLK_HDMI_SPDIF_DISP 201 351 352 #define MIF_NR_CLK 202 353 354 /* CMU_PERIC */ 355 #define CLK_PCLK_SPI2 1 356 #define CLK_PCLK_SPI1 2 357 #define CLK_PCLK_SPI0 3 358 #define CLK_PCLK_UART2 4 359 #define CLK_PCLK_UART1 5 360 #define CLK_PCLK_UART0 6 361 #define CLK_PCLK_HSI2C3 7 362 #define CLK_PCLK_HSI2C2 8 363 #define CLK_PCLK_HSI2C1 9 364 #define CLK_PCLK_HSI2C0 10 365 #define CLK_PCLK_I2C7 11 366 #define CLK_PCLK_I2C6 12 367 #define CLK_PCLK_I2C5 13 368 #define CLK_PCLK_I2C4 14 369 #define CLK_PCLK_I2C3 15 370 #define CLK_PCLK_I2C2 16 371 #define CLK_PCLK_I2C1 17 372 #define CLK_PCLK_I2C0 18 373 #define CLK_PCLK_SPI4 19 374 #define CLK_PCLK_SPI3 20 375 #define CLK_PCLK_HSI2C11 21 376 #define CLK_PCLK_HSI2C10 22 377 #define CLK_PCLK_HSI2C9 23 378 #define CLK_PCLK_HSI2C8 24 379 #define CLK_PCLK_HSI2C7 25 380 #define CLK_PCLK_HSI2C6 26 381 #define CLK_PCLK_HSI2C5 27 382 #define CLK_PCLK_HSI2C4 28 383 #define CLK_SCLK_SPI4 29 384 #define CLK_SCLK_SPI3 30 385 #define CLK_SCLK_SPI2 31 386 #define CLK_SCLK_SPI1 32 387 #define CLK_SCLK_SPI0 33 388 #define CLK_SCLK_UART2 34 389 #define CLK_SCLK_UART1 35 390 #define CLK_SCLK_UART0 36 391 #define CLK_ACLK_AHB2APB_PERIC2P 37 392 #define CLK_ACLK_AHB2APB_PERIC1P 38 393 #define CLK_ACLK_AHB2APB_PERIC0P 39 394 #define CLK_ACLK_PERICNP_66 40 395 #define CLK_PCLK_SCI 41 396 #define CLK_PCLK_GPIO_FINGER 42 397 #define CLK_PCLK_GPIO_ESE 43 398 #define CLK_PCLK_PWM 44 399 #define CLK_PCLK_SPDIF 45 400 #define CLK_PCLK_PCM1 46 401 #define CLK_PCLK_I2S1 47 402 #define CLK_PCLK_ADCIF 48 403 #define CLK_PCLK_GPIO_TOUCH 49 404 #define CLK_PCLK_GPIO_NFC 50 405 #define CLK_PCLK_GPIO_PERIC 51 406 #define CLK_PCLK_PMU_PERIC 52 407 #define CLK_PCLK_SYSREG_PERIC 53 408 #define CLK_SCLK_IOCLK_SPI4 54 409 #define CLK_SCLK_IOCLK_SPI3 55 410 #define CLK_SCLK_SCI 56 411 #define CLK_SCLK_SC_IN 57 412 #define CLK_SCLK_PWM 58 413 #define CLK_SCLK_IOCLK_SPI2 59 414 #define CLK_SCLK_IOCLK_SPI1 60 415 #define CLK_SCLK_IOCLK_SPI0 61 416 #define CLK_SCLK_IOCLK_I2S1_BCLK 62 417 #define CLK_SCLK_SPDIF 63 418 #define CLK_SCLK_PCM1 64 419 #define CLK_SCLK_I2S1 65 420 421 #define CLK_DIV_SCLK_SCI 70 422 #define CLK_DIV_SCLK_SC_IN 71 423 424 #define PERIC_NR_CLK 72 425 426 /* CMU_PERIS */ 427 #define CLK_PCLK_HPM_APBIF 1 428 #define CLK_PCLK_TMU1_APBIF 2 429 #define CLK_PCLK_TMU0_APBIF 3 430 #define CLK_PCLK_PMU_PERIS 4 431 #define CLK_PCLK_SYSREG_PERIS 5 432 #define CLK_PCLK_CMU_TOP_APBIF 6 433 #define CLK_PCLK_WDT_APOLLO 7 434 #define CLK_PCLK_WDT_ATLAS 8 435 #define CLK_PCLK_MCT 9 436 #define CLK_PCLK_HDMI_CEC 10 437 #define CLK_ACLK_AHB2APB_PERIS1P 11 438 #define CLK_ACLK_AHB2APB_PERIS0P 12 439 #define CLK_ACLK_PERISNP_66 13 440 #define CLK_PCLK_TZPC12 14 441 #define CLK_PCLK_TZPC11 15 442 #define CLK_PCLK_TZPC10 16 443 #define CLK_PCLK_TZPC9 17 444 #define CLK_PCLK_TZPC8 18 445 #define CLK_PCLK_TZPC7 19 446 #define CLK_PCLK_TZPC6 20 447 #define CLK_PCLK_TZPC5 21 448 #define CLK_PCLK_TZPC4 22 449 #define CLK_PCLK_TZPC3 23 450 #define CLK_PCLK_TZPC2 24 451 #define CLK_PCLK_TZPC1 25 452 #define CLK_PCLK_TZPC0 26 453 #define CLK_PCLK_SECKEY_APBIF 27 454 #define CLK_PCLK_CHIPID_APBIF 28 455 #define CLK_PCLK_TOPRTC 29 456 #define CLK_PCLK_CUSTOM_EFUSE_APBIF 30 457 #define CLK_PCLK_ANTIRBK_CNT_APBIF 31 458 #define CLK_PCLK_OTP_CON_APBIF 32 459 #define CLK_SCLK_ASV_TB 33 460 #define CLK_SCLK_TMU1 34 461 #define CLK_SCLK_TMU0 35 462 #define CLK_SCLK_SECKEY 36 463 #define CLK_SCLK_CHIPID 37 464 #define CLK_SCLK_TOPRTC 38 465 #define CLK_SCLK_CUSTOM_EFUSE 39 466 #define CLK_SCLK_ANTIRBK_CNT 40 467 #define CLK_SCLK_OTP_CON 41 468 469 #define PERIS_NR_CLK 42 470 471 /* CMU_FSYS */ 472 #define CLK_MOUT_ACLK_FSYS_200_USER 1 473 #define CLK_MOUT_SCLK_MMC2_USER 2 474 #define CLK_MOUT_SCLK_MMC1_USER 3 475 #define CLK_MOUT_SCLK_MMC0_USER 4 476 477 #define CLK_ACLK_PCIE 50 478 #define CLK_ACLK_PDMA1 51 479 #define CLK_ACLK_TSI 52 480 #define CLK_ACLK_MMC2 53 481 #define CLK_ACLK_MMC1 54 482 #define CLK_ACLK_MMC0 55 483 #define CLK_ACLK_UFS 56 484 #define CLK_ACLK_USBHOST20 57 485 #define CLK_ACLK_USBHOST30 58 486 #define CLK_ACLK_USBDRD30 59 487 #define CLK_ACLK_PDMA0 60 488 #define CLK_SCLK_MMC2 61 489 #define CLK_SCLK_MMC1 62 490 #define CLK_SCLK_MMC0 63 491 #define CLK_PDMA1 64 492 #define CLK_PDMA0 65 493 494 #define FSYS_NR_CLK 66 495 496 /* CMU_G2D */ 497 #define CLK_MUX_ACLK_G2D_266_USER 1 498 #define CLK_MUX_ACLK_G2D_400_USER 2 499 500 #define CLK_DIV_PCLK_G2D 3 501 502 #define CLK_ACLK_SMMU_MDMA1 4 503 #define CLK_ACLK_BTS_MDMA1 5 504 #define CLK_ACLK_BTS_G2D 6 505 #define CLK_ACLK_ALB_G2D 7 506 #define CLK_ACLK_AXIUS_G2DX 8 507 #define CLK_ACLK_ASYNCAXI_SYSX 9 508 #define CLK_ACLK_AHB2APB_G2D1P 10 509 #define CLK_ACLK_AHB2APB_G2D0P 11 510 #define CLK_ACLK_XIU_G2DX 12 511 #define CLK_ACLK_G2DNP_133 13 512 #define CLK_ACLK_G2DND_400 14 513 #define CLK_ACLK_MDMA1 15 514 #define CLK_ACLK_G2D 16 515 #define CLK_ACLK_SMMU_G2D 17 516 #define CLK_PCLK_SMMU_MDMA1 18 517 #define CLK_PCLK_BTS_MDMA1 19 518 #define CLK_PCLK_BTS_G2D 20 519 #define CLK_PCLK_ALB_G2D 21 520 #define CLK_PCLK_ASYNCAXI_SYSX 22 521 #define CLK_PCLK_PMU_G2D 23 522 #define CLK_PCLK_SYSREG_G2D 24 523 #define CLK_PCLK_G2D 25 524 #define CLK_PCLK_SMMU_G2D 26 525 526 #define G2D_NR_CLK 27 527 528 /* CMU_DISP */ 529 #define CLK_FOUT_DISP_PLL 1 530 531 #define CLK_MOUT_DISP_PLL 2 532 #define CLK_MOUT_SCLK_DSIM1_USER 3 533 #define CLK_MOUT_SCLK_DSIM0_USER 4 534 #define CLK_MOUT_SCLK_DSD_USER 5 535 #define CLK_MOUT_SCLK_DECON_TV_ECLK_USER 6 536 #define CLK_MOUT_SCLK_DECON_VCLK_USER 7 537 #define CLK_MOUT_SCLK_DECON_ECLK_USER 8 538 #define CLK_MOUT_SCLK_DECON_TV_VCLK_USER 9 539 #define CLK_MOUT_ACLK_DISP_333_USER 10 540 #define CLK_MOUT_PHYCLK_MIPIDPHY1_BITCLKDIV8_USER 11 541 #define CLK_MOUT_PHYCLK_MIPIDPHY1_RXCLKESC0_USER 12 542 #define CLK_MOUT_PHYCLK_MIPIDPHY0_BITCLKDIV8_USER 13 543 #define CLK_MOUT_PHYCLK_MIPIDPHY0_RXCLKESC0_USER 14 544 #define CLK_MOUT_PHYCLK_HDMIPHY_TMDS_CLKO_USER 15 545 #define CLK_MOUT_PHYCLK_HDMIPHY_PIXEL_CLKO_USER 16 546 #define CLK_MOUT_SCLK_DSIM0 17 547 #define CLK_MOUT_SCLK_DECON_TV_ECLK 18 548 #define CLK_MOUT_SCLK_DECON_VCLK 19 549 #define CLK_MOUT_SCLK_DECON_ECLK 20 550 #define CLK_MOUT_SCLK_DSIM1_B_DISP 21 551 #define CLK_MOUT_SCLK_DSIM1_A_DISP 22 552 #define CLK_MOUT_SCLK_DECON_TV_VCLK_C_DISP 23 553 #define CLK_MOUT_SCLK_DECON_TV_VCLK_B_DISP 24 554 #define CLK_MOUT_SCLK_DECON_TV_VCLK_A_DISP 25 555 556 #define CLK_DIV_SCLK_DSIM1_DISP 30 557 #define CLK_DIV_SCLK_DECON_TV_VCLK_DISP 31 558 #define CLK_DIV_SCLK_DSIM0_DISP 32 559 #define CLK_DIV_SCLK_DECON_TV_ECLK_DISP 33 560 #define CLK_DIV_SCLK_DECON_VCLK_DISP 34 561 #define CLK_DIV_SCLK_DECON_ECLK_DISP 35 562 #define CLK_DIV_PCLK_DISP 36 563 564 #define CLK_ACLK_DECON_TV 40 565 #define CLK_ACLK_DECON 41 566 #define CLK_ACLK_SMMU_TV1X 42 567 #define CLK_ACLK_SMMU_TV0X 43 568 #define CLK_ACLK_SMMU_DECON1X 44 569 #define CLK_ACLK_SMMU_DECON0X 45 570 #define CLK_ACLK_BTS_DECON_TV_M3 46 571 #define CLK_ACLK_BTS_DECON_TV_M2 47 572 #define CLK_ACLK_BTS_DECON_TV_M1 48 573 #define CLK_ACLK_BTS_DECON_TV_M0 49 574 #define CLK_ACLK_BTS_DECON_NM4 50 575 #define CLK_ACLK_BTS_DECON_NM3 51 576 #define CLK_ACLK_BTS_DECON_NM2 52 577 #define CLK_ACLK_BTS_DECON_NM1 53 578 #define CLK_ACLK_BTS_DECON_NM0 54 579 #define CLK_ACLK_AHB2APB_DISPSFR2P 55 580 #define CLK_ACLK_AHB2APB_DISPSFR1P 56 581 #define CLK_ACLK_AHB2APB_DISPSFR0P 57 582 #define CLK_ACLK_AHB_DISPH 58 583 #define CLK_ACLK_XIU_TV1X 59 584 #define CLK_ACLK_XIU_TV0X 60 585 #define CLK_ACLK_XIU_DECON1X 61 586 #define CLK_ACLK_XIU_DECON0X 62 587 #define CLK_ACLK_XIU_DISP1X 63 588 #define CLK_ACLK_XIU_DISPNP_100 64 589 #define CLK_ACLK_DISP1ND_333 65 590 #define CLK_ACLK_DISP0ND_333 66 591 #define CLK_PCLK_SMMU_TV1X 67 592 #define CLK_PCLK_SMMU_TV0X 68 593 #define CLK_PCLK_SMMU_DECON1X 69 594 #define CLK_PCLK_SMMU_DECON0X 70 595 #define CLK_PCLK_BTS_DECON_TV_M3 71 596 #define CLK_PCLK_BTS_DECON_TV_M2 72 597 #define CLK_PCLK_BTS_DECON_TV_M1 73 598 #define CLK_PCLK_BTS_DECON_TV_M0 74 599 #define CLK_PCLK_BTS_DECONM4 75 600 #define CLK_PCLK_BTS_DECONM3 76 601 #define CLK_PCLK_BTS_DECONM2 77 602 #define CLK_PCLK_BTS_DECONM1 78 603 #define CLK_PCLK_BTS_DECONM0 79 604 #define CLK_PCLK_MIC1 80 605 #define CLK_PCLK_PMU_DISP 81 606 #define CLK_PCLK_SYSREG_DISP 82 607 #define CLK_PCLK_HDMIPHY 83 608 #define CLK_PCLK_HDMI 84 609 #define CLK_PCLK_MIC0 85 610 #define CLK_PCLK_DSIM1 86 611 #define CLK_PCLK_DSIM0 87 612 #define CLK_PCLK_DECON_TV 88 613 #define CLK_PHYCLK_MIPIDPHY1_BITCLKDIV8 89 614 #define CLK_PHYCLK_MIPIDPHY1_RXCLKESC0 90 615 #define CLK_SCLK_RGB_TV_VCLK_TO_DSIM1 91 616 #define CLK_SCLK_RGB_TV_VCLK_TO_MIC1 92 617 #define CLK_SCLK_DSIM1 93 618 #define CLK_SCLK_DECON_TV_VCLK 94 619 #define CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8 95 620 #define CLK_PHYCLK_MIPIDPHY0_RXCLKESC0 96 621 #define CLK_PHYCLK_HDMIPHY_TMDS_CLKO 97 622 #define CLK_PHYCLK_HDMI_PIXEL 98 623 #define CLK_SCLK_RGB_VCLK_TO_SMIES 99 624 #define CLK_SCLK_FREQ_DET_DISP_PLL 100 625 #define CLK_SCLK_RGB_VCLK_TO_DSIM0 101 626 #define CLK_SCLK_RGB_VCLK_TO_MIC0 102 627 #define CLK_SCLK_DSD 103 628 #define CLK_SCLK_HDMI_SPDIF 104 629 #define CLK_SCLK_DSIM0 105 630 #define CLK_SCLK_DECON_TV_ECLK 106 631 #define CLK_SCLK_DECON_VCLK 107 632 #define CLK_SCLK_DECON_ECLK 108 633 #define CLK_SCLK_RGB_VCLK 109 634 #define CLK_SCLK_RGB_TV_VCLK 110 635 636 #define DISP_NR_CLK 111 637 638 /* CMU_AUD */ 639 #define CLK_MOUT_AUD_PLL_USER 1 640 #define CLK_MOUT_SCLK_AUD_PCM 2 641 #define CLK_MOUT_SCLK_AUD_I2S 3 642 643 #define CLK_DIV_ATCLK_AUD 4 644 #define CLK_DIV_PCLK_DBG_AUD 5 645 #define CLK_DIV_ACLK_AUD 6 646 #define CLK_DIV_AUD_CA5 7 647 #define CLK_DIV_SCLK_AUD_SLIMBUS 8 648 #define CLK_DIV_SCLK_AUD_UART 9 649 #define CLK_DIV_SCLK_AUD_PCM 10 650 #define CLK_DIV_SCLK_AUD_I2S 11 651 652 #define CLK_ACLK_INTR_CTRL 12 653 #define CLK_ACLK_AXIDS2_LPASSP 13 654 #define CLK_ACLK_AXIDS1_LPASSP 14 655 #define CLK_ACLK_AXI2APB1_LPASSP 15 656 #define CLK_ACLK_AXI2APH_LPASSP 16 657 #define CLK_ACLK_SMMU_LPASSX 17 658 #define CLK_ACLK_AXIDS0_LPASSP 18 659 #define CLK_ACLK_AXI2APB0_LPASSP 19 660 #define CLK_ACLK_XIU_LPASSX 20 661 #define CLK_ACLK_AUDNP_133 21 662 #define CLK_ACLK_AUDND_133 22 663 #define CLK_ACLK_SRAMC 23 664 #define CLK_ACLK_DMAC 24 665 #define CLK_PCLK_WDT1 25 666 #define CLK_PCLK_WDT0 26 667 #define CLK_PCLK_SFR1 27 668 #define CLK_PCLK_SMMU_LPASSX 28 669 #define CLK_PCLK_GPIO_AUD 29 670 #define CLK_PCLK_PMU_AUD 30 671 #define CLK_PCLK_SYSREG_AUD 31 672 #define CLK_PCLK_AUD_SLIMBUS 32 673 #define CLK_PCLK_AUD_UART 33 674 #define CLK_PCLK_AUD_PCM 34 675 #define CLK_PCLK_AUD_I2S 35 676 #define CLK_PCLK_TIMER 36 677 #define CLK_PCLK_SFR0_CTRL 37 678 #define CLK_ATCLK_AUD 38 679 #define CLK_PCLK_DBG_AUD 39 680 #define CLK_SCLK_AUD_CA5 40 681 #define CLK_SCLK_JTAG_TCK 41 682 #define CLK_SCLK_SLIMBUS_CLKIN 42 683 #define CLK_SCLK_AUD_SLIMBUS 43 684 #define CLK_SCLK_AUD_UART 44 685 #define CLK_SCLK_AUD_PCM 45 686 #define CLK_SCLK_I2S_BCLK 46 687 #define CLK_SCLK_AUD_I2S 47 688 689 #define AUD_NR_CLK 48 690 691 /* CMU_BUS{0|1|2} */ 692 #define CLK_DIV_PCLK_BUS_133 1 693 694 #define CLK_ACLK_AHB2APB_BUSP 2 695 #define CLK_ACLK_BUSNP_133 3 696 #define CLK_ACLK_BUSND_400 4 697 #define CLK_PCLK_BUSSRVND_133 5 698 #define CLK_PCLK_PMU_BUS 6 699 #define CLK_PCLK_SYSREG_BUS 7 700 701 #define CLK_MOUT_ACLK_BUS2_400_USER 8 /* Only CMU_BUS2 */ 702 #define CLK_ACLK_BUS2BEND_400 9 /* Only CMU_BUS2 */ 703 #define CLK_ACLK_BUS2RTND_400 10 /* Only CMU_BUS2 */ 704 705 #define BUSx_NR_CLK 11 706 707 #endif /* _DT_BINDINGS_CLOCK_EXYNOS5433_H */ 708