1 /* 2 * Copyright (c) 2014 Samsung Electronics Co., Ltd. 3 * Author: Chanwoo Choi <cw00.choi@samsung.com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 */ 9 10 #ifndef _DT_BINDINGS_CLOCK_EXYNOS5433_H 11 #define _DT_BINDINGS_CLOCK_EXYNOS5433_H 12 13 /* CMU_TOP */ 14 #define CLK_FOUT_ISP_PLL 1 15 #define CLK_FOUT_AUD_PLL 2 16 17 #define CLK_MOUT_AUD_PLL 10 18 #define CLK_MOUT_ISP_PLL 11 19 #define CLK_MOUT_AUD_PLL_USER_T 12 20 #define CLK_MOUT_MPHY_PLL_USER 13 21 #define CLK_MOUT_MFC_PLL_USER 14 22 #define CLK_MOUT_BUS_PLL_USER 15 23 #define CLK_MOUT_ACLK_HEVC_400 16 24 #define CLK_MOUT_ACLK_CAM1_333 17 25 #define CLK_MOUT_ACLK_CAM1_552_B 18 26 #define CLK_MOUT_ACLK_CAM1_552_A 19 27 #define CLK_MOUT_ACLK_ISP_DIS_400 20 28 #define CLK_MOUT_ACLK_ISP_400 21 29 #define CLK_MOUT_ACLK_BUS0_400 22 30 #define CLK_MOUT_ACLK_MSCL_400_B 23 31 #define CLK_MOUT_ACLK_MSCL_400_A 24 32 #define CLK_MOUT_ACLK_GSCL_333 25 33 #define CLK_MOUT_ACLK_G2D_400_B 26 34 #define CLK_MOUT_ACLK_G2D_400_A 27 35 #define CLK_MOUT_SCLK_JPEG_C 28 36 #define CLK_MOUT_SCLK_JPEG_B 29 37 #define CLK_MOUT_SCLK_JPEG_A 30 38 #define CLK_MOUT_SCLK_MMC2_B 31 39 #define CLK_MOUT_SCLK_MMC2_A 32 40 #define CLK_MOUT_SCLK_MMC1_B 33 41 #define CLK_MOUT_SCLK_MMC1_A 34 42 #define CLK_MOUT_SCLK_MMC0_D 35 43 #define CLK_MOUT_SCLK_MMC0_C 36 44 #define CLK_MOUT_SCLK_MMC0_B 37 45 #define CLK_MOUT_SCLK_MMC0_A 38 46 #define CLK_MOUT_SCLK_SPI4 39 47 #define CLK_MOUT_SCLK_SPI3 40 48 #define CLK_MOUT_SCLK_UART2 41 49 #define CLK_MOUT_SCLK_UART1 42 50 #define CLK_MOUT_SCLK_UART0 43 51 #define CLK_MOUT_SCLK_SPI2 44 52 #define CLK_MOUT_SCLK_SPI1 45 53 #define CLK_MOUT_SCLK_SPI0 46 54 55 #define CLK_DIV_ACLK_FSYS_200 100 56 #define CLK_DIV_ACLK_IMEM_SSSX_266 101 57 #define CLK_DIV_ACLK_IMEM_200 102 58 #define CLK_DIV_ACLK_IMEM_266 103 59 #define CLK_DIV_ACLK_PERIC_66_B 104 60 #define CLK_DIV_ACLK_PERIC_66_A 105 61 #define CLK_DIV_ACLK_PERIS_66_B 106 62 #define CLK_DIV_ACLK_PERIS_66_A 107 63 #define CLK_DIV_SCLK_MMC1_B 108 64 #define CLK_DIV_SCLK_MMC1_A 109 65 #define CLK_DIV_SCLK_MMC0_B 110 66 #define CLK_DIV_SCLK_MMC0_A 111 67 #define CLK_DIV_SCLK_MMC2_B 112 68 #define CLK_DIV_SCLK_MMC2_A 113 69 #define CLK_DIV_SCLK_SPI1_B 114 70 #define CLK_DIV_SCLK_SPI1_A 115 71 #define CLK_DIV_SCLK_SPI0_B 116 72 #define CLK_DIV_SCLK_SPI0_A 117 73 #define CLK_DIV_SCLK_SPI2_B 118 74 #define CLK_DIV_SCLK_SPI2_A 119 75 #define CLK_DIV_SCLK_UART2 120 76 #define CLK_DIV_SCLK_UART1 121 77 #define CLK_DIV_SCLK_UART0 122 78 #define CLK_DIV_SCLK_SPI4_B 123 79 #define CLK_DIV_SCLK_SPI4_A 124 80 #define CLK_DIV_SCLK_SPI3_B 125 81 #define CLK_DIV_SCLK_SPI3_A 126 82 83 #define CLK_ACLK_PERIC_66 200 84 #define CLK_ACLK_PERIS_66 201 85 #define CLK_ACLK_FSYS_200 202 86 #define CLK_SCLK_MMC2_FSYS 203 87 #define CLK_SCLK_MMC1_FSYS 204 88 #define CLK_SCLK_MMC0_FSYS 205 89 #define CLK_SCLK_SPI4_PERIC 206 90 #define CLK_SCLK_SPI3_PERIC 207 91 #define CLK_SCLK_UART2_PERIC 208 92 #define CLK_SCLK_UART1_PERIC 209 93 #define CLK_SCLK_UART0_PERIC 210 94 #define CLK_SCLK_SPI2_PERIC 211 95 #define CLK_SCLK_SPI1_PERIC 212 96 #define CLK_SCLK_SPI0_PERIC 213 97 98 #define TOP_NR_CLK 214 99 100 /* CMU_CPIF */ 101 #define CLK_FOUT_MPHY_PLL 1 102 103 #define CLK_MOUT_MPHY_PLL 2 104 105 #define CLK_DIV_SCLK_MPHY 10 106 107 #define CLK_SCLK_MPHY_PLL 11 108 #define CLK_SCLK_UFS_MPHY 11 109 110 #define CPIF_NR_CLK 12 111 112 /* CMU_MIF */ 113 #define CLK_FOUT_MEM0_PLL 1 114 #define CLK_FOUT_MEM1_PLL 2 115 #define CLK_FOUT_BUS_PLL 3 116 #define CLK_FOUT_MFC_PLL 4 117 118 #define MIF_NR_CLK 5 119 120 /* CMU_PERIC */ 121 #define CLK_PCLK_SPI2 1 122 #define CLK_PCLK_SPI1 2 123 #define CLK_PCLK_SPI0 3 124 #define CLK_PCLK_UART2 4 125 #define CLK_PCLK_UART1 5 126 #define CLK_PCLK_UART0 6 127 #define CLK_PCLK_HSI2C3 7 128 #define CLK_PCLK_HSI2C2 8 129 #define CLK_PCLK_HSI2C1 9 130 #define CLK_PCLK_HSI2C0 10 131 #define CLK_PCLK_I2C7 11 132 #define CLK_PCLK_I2C6 12 133 #define CLK_PCLK_I2C5 13 134 #define CLK_PCLK_I2C4 14 135 #define CLK_PCLK_I2C3 15 136 #define CLK_PCLK_I2C2 16 137 #define CLK_PCLK_I2C1 17 138 #define CLK_PCLK_I2C0 18 139 #define CLK_PCLK_SPI4 19 140 #define CLK_PCLK_SPI3 20 141 #define CLK_PCLK_HSI2C11 21 142 #define CLK_PCLK_HSI2C10 22 143 #define CLK_PCLK_HSI2C9 23 144 #define CLK_PCLK_HSI2C8 24 145 #define CLK_PCLK_HSI2C7 25 146 #define CLK_PCLK_HSI2C6 26 147 #define CLK_PCLK_HSI2C5 27 148 #define CLK_PCLK_HSI2C4 28 149 #define CLK_SCLK_SPI4 29 150 #define CLK_SCLK_SPI3 30 151 #define CLK_SCLK_SPI2 31 152 #define CLK_SCLK_SPI1 32 153 #define CLK_SCLK_SPI0 33 154 #define CLK_SCLK_UART2 34 155 #define CLK_SCLK_UART1 35 156 #define CLK_SCLK_UART0 36 157 158 #define PERIC_NR_CLK 37 159 160 /* CMU_PERIS */ 161 #define CLK_PCLK_HPM_APBIF 1 162 #define CLK_PCLK_TMU1_APBIF 2 163 #define CLK_PCLK_TMU0_APBIF 3 164 #define CLK_PCLK_PMU_PERIS 4 165 #define CLK_PCLK_SYSREG_PERIS 5 166 #define CLK_PCLK_CMU_TOP_APBIF 6 167 #define CLK_PCLK_WDT_APOLLO 7 168 #define CLK_PCLK_WDT_ATLAS 8 169 #define CLK_PCLK_MCT 9 170 #define CLK_PCLK_HDMI_CEC 10 171 172 #define PERIS_NR_CLK 11 173 174 /* CMU_FSYS */ 175 #define CLK_MOUT_ACLK_FSYS_200_USER 1 176 #define CLK_MOUT_SCLK_MMC2_USER 2 177 #define CLK_MOUT_SCLK_MMC1_USER 3 178 #define CLK_MOUT_SCLK_MMC0_USER 4 179 180 #define CLK_ACLK_PCIE 50 181 #define CLK_ACLK_PDMA1 51 182 #define CLK_ACLK_TSI 52 183 #define CLK_ACLK_MMC2 53 184 #define CLK_ACLK_MMC1 54 185 #define CLK_ACLK_MMC0 55 186 #define CLK_ACLK_UFS 56 187 #define CLK_ACLK_USBHOST20 57 188 #define CLK_ACLK_USBHOST30 58 189 #define CLK_ACLK_USBDRD30 59 190 #define CLK_ACLK_PDMA0 60 191 #define CLK_SCLK_MMC2 61 192 #define CLK_SCLK_MMC1 62 193 #define CLK_SCLK_MMC0 63 194 #define CLK_PDMA1 64 195 #define CLK_PDMA0 65 196 197 #define FSYS_NR_CLK 66 198 199 #endif /* _DT_BINDINGS_CLOCK_EXYNOS5433_H */ 200