#
4ce84f4d |
| 24-May-2019 |
Jose Abreu <Jose.Abreu@synopsys.com> |
net: stmmac: dwmac4/5: Add MAC loopback support
In preparation for the addition of stmmac selftests we implement the MAC loopback callback in dwmac4/5 cores.
Signed-off-by: Jose Abreu <joabreu@syno
net: stmmac: dwmac4/5: Add MAC loopback support
In preparation for the addition of stmmac selftests we implement the MAC loopback callback in dwmac4/5 cores.
Signed-off-by: Jose Abreu <joabreu@synopsys.com> Cc: Joao Pinto <jpinto@synopsys.com> Cc: David S. Miller <davem@davemloft.net> Cc: Giuseppe Cavallaro <peppe.cavallaro@st.com> Cc: Alexandre Torgue <alexandre.torgue@st.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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Revision tags: v5.1.4, v5.1.3, v5.1.2, v5.1.1, v5.0.14, v5.1, v5.0.13, v5.0.12, v5.0.11, v5.0.10, v5.0.9, v5.0.8, v5.0.7, v5.0.6, v5.0.5, v5.0.4, v5.0.3, v4.19.29, v5.0.2, v4.19.28, v5.0.1, v4.19.27, v5.0, v4.19.26, v4.19.25, v4.19.24, v4.19.23, v4.19.22, v4.19.21, v4.19.20, v4.19.19, v4.19.18, v4.19.17, v4.19.16, v4.19.15, v4.19.14, v4.19.13, v4.19.12, v4.19.11, v4.19.10, v4.19.9, v4.19.8, v4.19.7, v4.19.6, v4.19.5, v4.19.4, v4.18.20, v4.19.3, v4.18.19, v4.19.2, v4.18.18, v4.18.17, v4.19.1, v4.19, v4.18.16, v4.18.15, v4.18.14, v4.18.13, v4.18.12, v4.18.11, v4.18.10, v4.18.9, v4.18.7, v4.18.6, v4.18.5, v4.17.18, v4.18.4, v4.18.3, v4.17.17, v4.18.2, v4.17.16, v4.17.15, v4.18.1, v4.18, v4.17.14, v4.17.13, v4.17.12, v4.17.11, v4.17.10, v4.17.9, v4.17.8, v4.17.7, v4.17.6, v4.17.5, v4.17.4, v4.17.3, v4.17.2, v4.17.1, v4.17 |
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#
9a8a02c9 |
| 31-May-2018 |
Jose Abreu <Jose.Abreu@synopsys.com> |
net: stmmac: Add Flexible PPS support
This adds support for Flexible PPS output (which is equivalent to per_out output of PTP subsystem).
Tested using an oscilloscope and the following commands:
1
net: stmmac: Add Flexible PPS support
This adds support for Flexible PPS output (which is equivalent to per_out output of PTP subsystem).
Tested using an oscilloscope and the following commands:
1) Start PTP4L: # ptp4l -A -4 -H -m -i eth0 & 2) Set Flexible PPS frequency: # echo <idx> <ts> <tns> <ps> <pns> > /sys/class/ptp/ptpX/period
Where, ts/tns is start time and ps/pns is period time, and ptpX is ptp of eth0.
Signed-off-by: Jose Abreu <joabreu@synopsys.com> Cc: David S. Miller <davem@davemloft.net> Cc: Joao Pinto <jpinto@synopsys.com> Cc: Vitor Soares <soares@synopsys.com> Cc: Giuseppe Cavallaro <peppe.cavallaro@st.com> Cc: Alexandre Torgue <alexandre.torgue@st.com> Cc: Richard Cochran <richardcochran@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
4dbbe8dd |
| 04-May-2018 |
Jose Abreu <Jose.Abreu@synopsys.com> |
net: stmmac: Add support for U32 TC filter using Flexible RX Parser
This adds support for U32 filter by using an HW only feature called Flexible RX Parser. This allow us to match any given packet fi
net: stmmac: Add support for U32 TC filter using Flexible RX Parser
This adds support for U32 filter by using an HW only feature called Flexible RX Parser. This allow us to match any given packet field with a pattern and accept/reject or even route the packet to a specific DMA channel.
Right now we only support acception or rejection of frame and we only support simple rules. Though, the Parser has the flexibility of jumping to specific rules as an if condition so complex rules can be established.
This is only supported in GMAC5.10+.
The following commands can be used to test this code:
1) Setup an ingress qdisk: # tc qdisc add dev eth0 handle ffff: ingress
2) Setup a filter (e.g. filter by IP): # tc filter add dev eth0 parent ffff: protocol ip u32 match ip \ src 192.168.0.3 skip_sw action drop
In every tests performed we always used the "skip_sw" flag to make sure only the RX Parser was involved.
Signed-off-by: Jose Abreu <joabreu@synopsys.com> Cc: David S. Miller <davem@davemloft.net> Cc: Joao Pinto <jpinto@synopsys.com> Cc: Vitor Soares <soares@synopsys.com> Cc: Giuseppe Cavallaro <peppe.cavallaro@st.com> Cc: Alexandre Torgue <alexandre.torgue@st.com> Cc: Jakub Kicinski <kubakici@wp.pl> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
5f0456b4 |
| 23-Apr-2018 |
Jose Abreu <Jose.Abreu@synopsys.com> |
net: stmmac: Implement logic to automatically select HW Interface
Move all the core version detection to a common place ("hwif.c") and implement a table which can be used to lookup the correct callb
net: stmmac: Implement logic to automatically select HW Interface
Move all the core version detection to a common place ("hwif.c") and implement a table which can be used to lookup the correct callbacks for each IP version.
This simplifies the initialization flow of each IP version and eases future implementation of new IP versions.
Signed-off-by: Jose Abreu <joabreu@synopsys.com> Cc: David S. Miller <davem@davemloft.net> Cc: Joao Pinto <jpinto@synopsys.com> Cc: Vitor Soares <soares@synopsys.com> Cc: Giuseppe Cavallaro <peppe.cavallaro@st.com> Cc: Alexandre Torgue <alexandre.torgue@st.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
565020aa |
| 18-Apr-2018 |
Jose Abreu <Jose.Abreu@synopsys.com> |
net: stmmac: Disable ACS Feature for GMAC >= 4
ACS Feature is currently enabled for GMAC >= 4 but the llc_snap status is never checked in descriptor rx_status callback. This will cause stmmac to alw
net: stmmac: Disable ACS Feature for GMAC >= 4
ACS Feature is currently enabled for GMAC >= 4 but the llc_snap status is never checked in descriptor rx_status callback. This will cause stmmac to always strip packets even that ACS feature is already stripping them.
Lets be safe and disable the ACS feature for GMAC >= 4 and always strip the packets for this GMAC version.
Fixes: 477286b53f55 ("stmmac: add GMAC4 core support") Signed-off-by: Jose Abreu <joabreu@synopsys.com> Cc: David S. Miller <davem@davemloft.net> Cc: Joao Pinto <jpinto@synopsys.com> Cc: Giuseppe Cavallaro <peppe.cavallaro@st.com> Cc: Alexandre Torgue <alexandre.torgue@st.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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Revision tags: v4.16 |
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#
8bf993a5 |
| 29-Mar-2018 |
Jose Abreu <Jose.Abreu@synopsys.com> |
net: stmmac: Add support for DWMAC5 and implement Safety Features
This adds initial suport for DWMAC5 and implements the Automotive Safety Package which is available from core version 5.10.
The Aut
net: stmmac: Add support for DWMAC5 and implement Safety Features
This adds initial suport for DWMAC5 and implements the Automotive Safety Package which is available from core version 5.10.
The Automotive Safety Pacakge (also called Safety Features) offers us with error protection in the core by implementing ECC Protection in memories, on-chip data path parity protection, FSM parity and timeout protection and Application/CSR interface timeout protection.
In case of an uncorrectable error we call stmmac_global_err() and reconfigure the whole core.
Signed-off-by: Jose Abreu <joabreu@synopsys.com> Cc: David S. Miller <davem@davemloft.net> Cc: Joao Pinto <jpinto@synopsys.com> Cc: Giuseppe Cavallaro <peppe.cavallaro@st.com> Cc: Alexandre Torgue <alexandre.torgue@st.com> Cc: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
e879b7ab |
| 09-Feb-2018 |
Niklas Cassel <niklas.cassel@axis.com> |
net: stmmac: rename GMAC_INT_DEFAULT_MASK for dwmac4
GMAC_INT_DEFAULT_MASK is written to the interrupt enable register. In previous versions of the IP (e.g. dwmac1000), this register was instead an
net: stmmac: rename GMAC_INT_DEFAULT_MASK for dwmac4
GMAC_INT_DEFAULT_MASK is written to the interrupt enable register. In previous versions of the IP (e.g. dwmac1000), this register was instead an interrupt mask register. To improve clarity and reflect reality, rename GMAC_INT_DEFAULT_MASK to GMAC_INT_DEFAULT_ENABLE.
Signed-off-by: Niklas Cassel <niklas.cassel@axis.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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Revision tags: v4.15, v4.13.16 |
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#
4497478c |
| 14-Nov-2017 |
Niklas Cassel <niklas.cassel@axis.com> |
net: stmmac: fix LPI transitioning for dwmac4
The LPI transitioning logic in stmmac_main uses priv->tx_path_in_lpi_mode to enter/exit LPI.
However, priv->tx_path_in_lpi_mode is assigned using the r
net: stmmac: fix LPI transitioning for dwmac4
The LPI transitioning logic in stmmac_main uses priv->tx_path_in_lpi_mode to enter/exit LPI.
However, priv->tx_path_in_lpi_mode is assigned using the return value from host_irq_status().
So for dwmac4, priv->tx_path_in_lpi_mode was always false, so stmmac_tx_clean() would always try to put us in eee mode, and stmmac_xmit() would never take us out of eee mode.
To fix this, make host_irq_status() read and return the LPI irq status also for dwmac4.
This also increments the existing LPI counters, so that ethtool --statistics shows LPI transitions also for dwmac4.
For dwmac1000, irqs are enabled/disabled using the register named "Interrupt Mask Register", and thus setting a bit disables that specific irq.
For dwmac4 the matching register is named "MAC_Interrupt_Enable", and thus setting a bit enables that specific irq.
Looking at dwmac1000_core.c, the irqs that are always enabled are: LPI and PMT.
Looking at dwmac4_core.c, the irqs that are always enabled are: PMT.
To be able to read the LPI irq status, we need to enable the LPI irq also for dwmac4.
Signed-off-by: Niklas Cassel <niklas.cassel@axis.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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Revision tags: v4.14 |
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#
a0daae13 |
| 13-Oct-2017 |
Jose Abreu <Jose.Abreu@synopsys.com> |
net: stmmac: Disable flow ctrl for RX AVB queues and really enable TX AVB queues
Flow control must be disabled for AVB enabled queues and TX AVB queues must be enabled by setting BIT(2) of TXQEN.
C
net: stmmac: Disable flow ctrl for RX AVB queues and really enable TX AVB queues
Flow control must be disabled for AVB enabled queues and TX AVB queues must be enabled by setting BIT(2) of TXQEN.
Correct this by passing the queue mode to DMA callbacks and by checking in these functions wether we are in AVB performing the necessary adjustments.
Signed-off-by: Jose Abreu <joabreu@synopsys.com> Cc: David S. Miller <davem@davemloft.net> Cc: Joao Pinto <jpinto@synopsys.com> Cc: Giuseppe Cavallaro <peppe.cavallaro@st.com> Cc: Alexandre Torgue <alexandre.torgue@st.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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Revision tags: v4.13.5, v4.13, v4.12, v4.10.17, v4.10.16, v4.10.15, v4.10.14, v4.10.13, v4.10.12, v4.10.11, v4.10.10, v4.10.9, v4.10.8, v4.10.7, v4.10.6, v4.10.5, v4.10.4 |
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#
abe80fdc |
| 17-Mar-2017 |
Joao Pinto <Joao.Pinto@synopsys.com> |
net: stmmac: RX queue routing configuration
This patch adds the configuration of RX queues' routing.
Signed-off-by: Joao Pinto <jpinto@synopsys.com> Signed-off-by: David S. Miller <davem@davemloft.
net: stmmac: RX queue routing configuration
This patch adds the configuration of RX queues' routing.
Signed-off-by: Joao Pinto <jpinto@synopsys.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
a8f5102a |
| 17-Mar-2017 |
Joao Pinto <Joao.Pinto@synopsys.com> |
net: stmmac: TX and RX queue priority configuration
This patch adds the configuration of RX and TX queues' priority.
Signed-off-by: Joao Pinto <jpinto@synopsys.com> Signed-off-by: David S. Miller <
net: stmmac: TX and RX queue priority configuration
This patch adds the configuration of RX and TX queues' priority.
Signed-off-by: Joao Pinto <jpinto@synopsys.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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Revision tags: v4.10.3, v4.10.2 |
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#
19d91873 |
| 10-Mar-2017 |
Joao Pinto <Joao.Pinto@synopsys.com> |
net: stmmac: configuration of CBS in case of a TX AVB queue
This patch adds the configuration of the AVB Credit-Based Shaper.
Signed-off-by: Joao Pinto <jpinto@synopsys.com> Signed-off-by: David S.
net: stmmac: configuration of CBS in case of a TX AVB queue
This patch adds the configuration of the AVB Credit-Based Shaper.
Signed-off-by: Joao Pinto <jpinto@synopsys.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
8f71a88d |
| 10-Mar-2017 |
Joao Pinto <Joao.Pinto@synopsys.com> |
net: stmmac: prepare irq_status for mtl
This patch prepares mac irq status treatment for multiple queues.
Signed-off-by: Joao Pinto <jpinto@synopsys.com> Signed-off-by: David S. Miller <davem@davem
net: stmmac: prepare irq_status for mtl
This patch prepares mac irq status treatment for multiple queues.
Signed-off-by: Joao Pinto <jpinto@synopsys.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
d43042f4 |
| 10-Mar-2017 |
Joao Pinto <Joao.Pinto@synopsys.com> |
net: stmmac: mapping mtl rx to dma channel
This patch adds the functionality of RX queue to dma channel mapping based on configuration.
Signed-off-by: Joao Pinto <jpinto@synopsys.com> Signed-off-by
net: stmmac: mapping mtl rx to dma channel
This patch adds the functionality of RX queue to dma channel mapping based on configuration.
Signed-off-by: Joao Pinto <jpinto@synopsys.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
6a3a7193 |
| 10-Mar-2017 |
Joao Pinto <Joao.Pinto@synopsys.com> |
net: stmmac: configure tx queue weight
This patch adds TX queues weight programming.
Signed-off-by: Joao Pinto <jpinto@synopsys.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
d0a9c9f9 |
| 10-Mar-2017 |
Joao Pinto <Joao.Pinto@synopsys.com> |
net: stmmac: configure mtl rx and tx algorithms
This patch adds the RX and TX scheduling algorithms programming. It introduces the multiple queues configuration function (stmmac_mtl_configuration) i
net: stmmac: configure mtl rx and tx algorithms
This patch adds the RX and TX scheduling algorithms programming. It introduces the multiple queues configuration function (stmmac_mtl_configuration) in stmmac_main.
Signed-off-by: Joao Pinto <jpinto@synopsys.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
e6ea2d16 |
| 10-Mar-2017 |
Thierry Reding <treding@nvidia.com> |
net: stmmac: dwc-qos: Add Tegra186 support
The NVIDIA Tegra186 SoC contains an instance of the Synopsys DWC ethernet QOS IP core. The binding that it uses is slightly different from existing ones be
net: stmmac: dwc-qos: Add Tegra186 support
The NVIDIA Tegra186 SoC contains an instance of the Synopsys DWC ethernet QOS IP core. The binding that it uses is slightly different from existing ones because of the integration (clocks, resets, ...).
Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
356b7557 |
| 10-Mar-2017 |
Thierry Reding <treding@nvidia.com> |
net: stmmac: Program RX queue size and flow control
Program the receive queue size based on the RX FIFO size and enable hardware flow control for large FIFOs.
Signed-off-by: Thierry Reding <treding
net: stmmac: Program RX queue size and flow control
Program the receive queue size based on the RX FIFO size and enable hardware flow control for large FIFOs.
Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
11fbf811 |
| 10-Mar-2017 |
Thierry Reding <treding@nvidia.com> |
net: stmmac: Parse FIFO sizes from feature registers
New version of this core encode the FIFO sizes in one of the feature registers. Use these sizes as default, but still allow device tree to overri
net: stmmac: Parse FIFO sizes from feature registers
New version of this core encode the FIFO sizes in one of the feature registers. Use these sizes as default, but still allow device tree to override them for backwards compatibility.
Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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Revision tags: v4.10.1, v4.10 |
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#
b4b7b772 |
| 09-Jan-2017 |
jpinto <Joao.Pinto@synopsys.com> |
stmmac: adding DT parameter for LPI tx clock gating
This patch adds a new parameter to the stmmac DT: snps,en-tx-lpi-clockgating. It was ported from synopsys/dwc_eth_qos.c and it is useful if lpi tx
stmmac: adding DT parameter for LPI tx clock gating
This patch adds a new parameter to the stmmac DT: snps,en-tx-lpi-clockgating. It was ported from synopsys/dwc_eth_qos.c and it is useful if lpi tx clock gating is needed by stmmac users also.
Signed-off-by: Joao Pinto <jpinto@synopsys.com> Tested-by: Niklas Cassel <niklas.cassel@axis.com> Reviewed-by: Lars Persson <larper@axis.com> Acked-by: Alexandre TORGUE <alexandre.torgue@st.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
afbb1674 |
| 29-Dec-2016 |
jpinto <Joao.Pinto@synopsys.com> |
stmmac: adding EEE to GMAC4
This patch adds Energy Efficiency Ethernet to GMAC4.
Signed-off-by: Joao Pinto <jpinto@synopsys.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
9eb12474 |
| 28-Dec-2016 |
jpinto <Joao.Pinto@synopsys.com> |
stmmac: enable rx queues
When the hardware is synthesized with multiple queues, all queues are disabled for default. This patch adds the rx queues configuration. This patch was successfully tested i
stmmac: enable rx queues
When the hardware is synthesized with multiple queues, all queues are disabled for default. This patch adds the rx queues configuration. This patch was successfully tested in a Synopsys QoS Reference design.
Signed-off-by: Joao Pinto <jpinto@synopsys.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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Revision tags: v4.9 |
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#
436feafe |
| 24-Nov-2016 |
Niklas Cassel <niklas.cassel@axis.com> |
net: stmmac: enable tx queue 0 for gmac4 IPs synthesized with multiple TX queues
The dwmac4 IP can synthesized with 1-8 number of tx queues. On an IP synthesized with DWC_EQOS_NUM_TXQ > 1, all txque
net: stmmac: enable tx queue 0 for gmac4 IPs synthesized with multiple TX queues
The dwmac4 IP can synthesized with 1-8 number of tx queues. On an IP synthesized with DWC_EQOS_NUM_TXQ > 1, all txqueues are disabled by default. For these IPs, the bitfield TXQEN is R/W.
Always enable tx queue 0. The write will have no effect on IPs synthesized with DWC_EQOS_NUM_TXQ == 1.
The driver does still not utilize more than one tx queue in the IP.
Signed-off-by: Niklas Cassel <niklas.cassel@axis.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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Revision tags: openbmc-4.4-20161121-1, v4.4.33, v4.4.32, v4.4.31, v4.4.30, v4.4.29, v4.4.28, v4.4.27, v4.7.10, openbmc-4.4-20161021-1, v4.7.9, v4.4.26, v4.7.8, v4.4.25, v4.4.24, v4.7.7, v4.8, v4.4.23, v4.7.6, v4.7.5, v4.4.22, v4.4.21, v4.7.4, v4.7.3, v4.4.20, v4.7.2, v4.4.19, openbmc-4.4-20160819-1, v4.7.1, v4.4.18, v4.4.17, openbmc-4.4-20160804-1, v4.4.16, v4.7, openbmc-4.4-20160722-1, openbmc-20160722-1, openbmc-20160713-1, v4.4.15, v4.6.4, v4.6.3, v4.4.14 |
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#
3fe5cadb |
| 24-Jun-2016 |
Giuseppe CAVALLARO <peppe.cavallaro@st.com> |
drivers: net: stmmac: rework core ISR to better manage PCS and PMT
By default, all gmac cores disable the PCS block and always enable the PMT.
Note that this is done in a different way by 3.x and 4
drivers: net: stmmac: rework core ISR to better manage PCS and PMT
By default, all gmac cores disable the PCS block and always enable the PMT.
Note that this is done in a different way by 3.x and 4.x cores.
With this rework, PCS and PMT interrupt masks can be driven by parameters now moved inside the mac_device_info structure and the settings follow what the HW capability register reports.
Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
70523e63 |
| 24-Jun-2016 |
Giuseppe CAVALLARO <peppe.cavallaro@st.com> |
drivers: net: stmmac: reworking the PCS code.
The 3.xx and 4.xx synopsys gmacs have a very similar PCS embedded module and they share almost the same registers: for example: AN_Control, AN_Status,
drivers: net: stmmac: reworking the PCS code.
The 3.xx and 4.xx synopsys gmacs have a very similar PCS embedded module and they share almost the same registers: for example: AN_Control, AN_Status, AN_Advertisement, AN_Link_Partner_Ability, AN_Expansion, TBI_Extended_Status.
Just the RGMII/SMII Control/Status register differs.
So This patch aims to reorganize and enhance the PCS support. It removes the existent support from the dwmac1000/dwmac4_core.c moving basic PCS functions inside a new file called: stmmac_pcs.h.
The patch also reviews the available APIs to be better shared among different hardware and easily enhanced to support new features.
Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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