1 /*
2  * DWMAC4 Header file.
3  *
4  * Copyright (C) 2015  STMicroelectronics Ltd
5  *
6  * This program is free software; you can redistribute it and/or modify it
7  * under the terms and conditions of the GNU General Public License,
8  * version 2, as published by the Free Software Foundation.
9  *
10  * Author: Alexandre Torgue <alexandre.torgue@st.com>
11  */
12 
13 #ifndef __DWMAC4_H__
14 #define __DWMAC4_H__
15 
16 #include "common.h"
17 
18 /*  MAC registers */
19 #define GMAC_CONFIG			0x00000000
20 #define GMAC_PACKET_FILTER		0x00000008
21 #define GMAC_HASH_TAB_0_31		0x00000010
22 #define GMAC_HASH_TAB_32_63		0x00000014
23 #define GMAC_RX_FLOW_CTRL		0x00000090
24 #define GMAC_QX_TX_FLOW_CTRL(x)		(0x70 + x * 4)
25 #define GMAC_RXQ_CTRL0			0x000000a0
26 #define GMAC_INT_STATUS			0x000000b0
27 #define GMAC_INT_EN			0x000000b4
28 #define GMAC_PCS_BASE			0x000000e0
29 #define GMAC_PHYIF_CONTROL_STATUS	0x000000f8
30 #define GMAC_PMT			0x000000c0
31 #define GMAC_VERSION			0x00000110
32 #define GMAC_DEBUG			0x00000114
33 #define GMAC_HW_FEATURE0		0x0000011c
34 #define GMAC_HW_FEATURE1		0x00000120
35 #define GMAC_HW_FEATURE2		0x00000124
36 #define GMAC_MDIO_ADDR			0x00000200
37 #define GMAC_MDIO_DATA			0x00000204
38 #define GMAC_ADDR_HIGH(reg)		(0x300 + reg * 8)
39 #define GMAC_ADDR_LOW(reg)		(0x304 + reg * 8)
40 
41 /* MAC Packet Filtering */
42 #define GMAC_PACKET_FILTER_PR		BIT(0)
43 #define GMAC_PACKET_FILTER_HMC		BIT(2)
44 #define GMAC_PACKET_FILTER_PM		BIT(4)
45 
46 #define GMAC_MAX_PERFECT_ADDRESSES	128
47 
48 /* MAC RX Queue Enable */
49 #define GMAC_RX_QUEUE_CLEAR(queue)	~(GENMASK(1, 0) << ((queue) * 2))
50 #define GMAC_RX_AV_QUEUE_ENABLE(queue)	BIT((queue) * 2)
51 #define GMAC_RX_DCB_QUEUE_ENABLE(queue)	BIT(((queue) * 2) + 1)
52 
53 /* MAC Flow Control RX */
54 #define GMAC_RX_FLOW_CTRL_RFE		BIT(0)
55 
56 /* MAC Flow Control TX */
57 #define GMAC_TX_FLOW_CTRL_TFE		BIT(1)
58 #define GMAC_TX_FLOW_CTRL_PT_SHIFT	16
59 
60 /*  MAC Interrupt bitmap*/
61 #define GMAC_INT_RGSMIIS		BIT(0)
62 #define GMAC_INT_PCS_LINK		BIT(1)
63 #define GMAC_INT_PCS_ANE		BIT(2)
64 #define GMAC_INT_PCS_PHYIS		BIT(3)
65 #define GMAC_INT_PMT_EN			BIT(4)
66 #define GMAC_INT_LPI_EN			BIT(5)
67 
68 #define	GMAC_PCS_IRQ_DEFAULT	(GMAC_INT_RGSMIIS | GMAC_INT_PCS_LINK |	\
69 				 GMAC_INT_PCS_ANE)
70 
71 #define	GMAC_INT_DEFAULT_MASK	GMAC_INT_PMT_EN
72 
73 enum dwmac4_irq_status {
74 	time_stamp_irq = 0x00001000,
75 	mmc_rx_csum_offload_irq = 0x00000800,
76 	mmc_tx_irq = 0x00000400,
77 	mmc_rx_irq = 0x00000200,
78 	mmc_irq = 0x00000100,
79 	pmt_irq = 0x00000010,
80 };
81 
82 /* MAC PMT bitmap */
83 enum power_event {
84 	pointer_reset =	0x80000000,
85 	global_unicast = 0x00000200,
86 	wake_up_rx_frame = 0x00000040,
87 	magic_frame = 0x00000020,
88 	wake_up_frame_en = 0x00000004,
89 	magic_pkt_en = 0x00000002,
90 	power_down = 0x00000001,
91 };
92 
93 /* MAC Debug bitmap */
94 #define GMAC_DEBUG_TFCSTS_MASK		GENMASK(18, 17)
95 #define GMAC_DEBUG_TFCSTS_SHIFT		17
96 #define GMAC_DEBUG_TFCSTS_IDLE		0
97 #define GMAC_DEBUG_TFCSTS_WAIT		1
98 #define GMAC_DEBUG_TFCSTS_GEN_PAUSE	2
99 #define GMAC_DEBUG_TFCSTS_XFER		3
100 #define GMAC_DEBUG_TPESTS		BIT(16)
101 #define GMAC_DEBUG_RFCFCSTS_MASK	GENMASK(2, 1)
102 #define GMAC_DEBUG_RFCFCSTS_SHIFT	1
103 #define GMAC_DEBUG_RPESTS		BIT(0)
104 
105 /* MAC config */
106 #define GMAC_CONFIG_IPC			BIT(27)
107 #define GMAC_CONFIG_2K			BIT(22)
108 #define GMAC_CONFIG_ACS			BIT(20)
109 #define GMAC_CONFIG_BE			BIT(18)
110 #define GMAC_CONFIG_JD			BIT(17)
111 #define GMAC_CONFIG_JE			BIT(16)
112 #define GMAC_CONFIG_PS			BIT(15)
113 #define GMAC_CONFIG_FES			BIT(14)
114 #define GMAC_CONFIG_DM			BIT(13)
115 #define GMAC_CONFIG_DCRS		BIT(9)
116 #define GMAC_CONFIG_TE			BIT(1)
117 #define GMAC_CONFIG_RE			BIT(0)
118 
119 /* MAC HW features0 bitmap */
120 #define GMAC_HW_FEAT_ADDMAC		BIT(18)
121 #define GMAC_HW_FEAT_RXCOESEL		BIT(16)
122 #define GMAC_HW_FEAT_TXCOSEL		BIT(14)
123 #define GMAC_HW_FEAT_EEESEL		BIT(13)
124 #define GMAC_HW_FEAT_TSSEL		BIT(12)
125 #define GMAC_HW_FEAT_MMCSEL		BIT(8)
126 #define GMAC_HW_FEAT_MGKSEL		BIT(7)
127 #define GMAC_HW_FEAT_RWKSEL		BIT(6)
128 #define GMAC_HW_FEAT_SMASEL		BIT(5)
129 #define GMAC_HW_FEAT_VLHASH		BIT(4)
130 #define GMAC_HW_FEAT_PCSSEL		BIT(3)
131 #define GMAC_HW_FEAT_HDSEL		BIT(2)
132 #define GMAC_HW_FEAT_GMIISEL		BIT(1)
133 #define GMAC_HW_FEAT_MIISEL		BIT(0)
134 
135 /* MAC HW features1 bitmap */
136 #define GMAC_HW_FEAT_AVSEL		BIT(20)
137 #define GMAC_HW_TSOEN			BIT(18)
138 
139 /* MAC HW features2 bitmap */
140 #define GMAC_HW_FEAT_TXCHCNT		GENMASK(21, 18)
141 #define GMAC_HW_FEAT_RXCHCNT		GENMASK(15, 12)
142 #define GMAC_HW_FEAT_TXQCNT		GENMASK(9, 6)
143 #define GMAC_HW_FEAT_RXQCNT		GENMASK(3, 0)
144 
145 /* MAC HW ADDR regs */
146 #define GMAC_HI_DCS			GENMASK(18, 16)
147 #define GMAC_HI_DCS_SHIFT		16
148 #define GMAC_HI_REG_AE			BIT(31)
149 
150 /*  MTL registers */
151 #define MTL_INT_STATUS			0x00000c20
152 #define MTL_INT_Q0			BIT(0)
153 
154 #define MTL_CHAN_BASE_ADDR		0x00000d00
155 #define MTL_CHAN_BASE_OFFSET		0x40
156 #define MTL_CHANX_BASE_ADDR(x)		(MTL_CHAN_BASE_ADDR + \
157 					(x * MTL_CHAN_BASE_OFFSET))
158 
159 #define MTL_CHAN_TX_OP_MODE(x)		MTL_CHANX_BASE_ADDR(x)
160 #define MTL_CHAN_TX_DEBUG(x)		(MTL_CHANX_BASE_ADDR(x) + 0x8)
161 #define MTL_CHAN_INT_CTRL(x)		(MTL_CHANX_BASE_ADDR(x) + 0x2c)
162 #define MTL_CHAN_RX_OP_MODE(x)		(MTL_CHANX_BASE_ADDR(x) + 0x30)
163 #define MTL_CHAN_RX_DEBUG(x)		(MTL_CHANX_BASE_ADDR(x) + 0x38)
164 
165 #define MTL_OP_MODE_RSF			BIT(5)
166 #define MTL_OP_MODE_TXQEN		BIT(3)
167 #define MTL_OP_MODE_TSF			BIT(1)
168 
169 #define MTL_OP_MODE_TQS_MASK		GENMASK(24, 16)
170 
171 #define MTL_OP_MODE_TTC_MASK		0x70
172 #define MTL_OP_MODE_TTC_SHIFT		4
173 
174 #define MTL_OP_MODE_TTC_32		0
175 #define MTL_OP_MODE_TTC_64		(1 << MTL_OP_MODE_TTC_SHIFT)
176 #define MTL_OP_MODE_TTC_96		(2 << MTL_OP_MODE_TTC_SHIFT)
177 #define MTL_OP_MODE_TTC_128		(3 << MTL_OP_MODE_TTC_SHIFT)
178 #define MTL_OP_MODE_TTC_192		(4 << MTL_OP_MODE_TTC_SHIFT)
179 #define MTL_OP_MODE_TTC_256		(5 << MTL_OP_MODE_TTC_SHIFT)
180 #define MTL_OP_MODE_TTC_384		(6 << MTL_OP_MODE_TTC_SHIFT)
181 #define MTL_OP_MODE_TTC_512		(7 << MTL_OP_MODE_TTC_SHIFT)
182 
183 #define MTL_OP_MODE_RTC_MASK		0x18
184 #define MTL_OP_MODE_RTC_SHIFT		3
185 
186 #define MTL_OP_MODE_RTC_32		(1 << MTL_OP_MODE_RTC_SHIFT)
187 #define MTL_OP_MODE_RTC_64		0
188 #define MTL_OP_MODE_RTC_96		(2 << MTL_OP_MODE_RTC_SHIFT)
189 #define MTL_OP_MODE_RTC_128		(3 << MTL_OP_MODE_RTC_SHIFT)
190 
191 /*  MTL debug */
192 #define MTL_DEBUG_TXSTSFSTS		BIT(5)
193 #define MTL_DEBUG_TXFSTS		BIT(4)
194 #define MTL_DEBUG_TWCSTS		BIT(3)
195 
196 /* MTL debug: Tx FIFO Read Controller Status */
197 #define MTL_DEBUG_TRCSTS_MASK		GENMASK(2, 1)
198 #define MTL_DEBUG_TRCSTS_SHIFT		1
199 #define MTL_DEBUG_TRCSTS_IDLE		0
200 #define MTL_DEBUG_TRCSTS_READ		1
201 #define MTL_DEBUG_TRCSTS_TXW		2
202 #define MTL_DEBUG_TRCSTS_WRITE		3
203 #define MTL_DEBUG_TXPAUSED		BIT(0)
204 
205 /* MAC debug: GMII or MII Transmit Protocol Engine Status */
206 #define MTL_DEBUG_RXFSTS_MASK		GENMASK(5, 4)
207 #define MTL_DEBUG_RXFSTS_SHIFT		4
208 #define MTL_DEBUG_RXFSTS_EMPTY		0
209 #define MTL_DEBUG_RXFSTS_BT		1
210 #define MTL_DEBUG_RXFSTS_AT		2
211 #define MTL_DEBUG_RXFSTS_FULL		3
212 #define MTL_DEBUG_RRCSTS_MASK		GENMASK(2, 1)
213 #define MTL_DEBUG_RRCSTS_SHIFT		1
214 #define MTL_DEBUG_RRCSTS_IDLE		0
215 #define MTL_DEBUG_RRCSTS_RDATA		1
216 #define MTL_DEBUG_RRCSTS_RSTAT		2
217 #define MTL_DEBUG_RRCSTS_FLUSH		3
218 #define MTL_DEBUG_RWCSTS		BIT(0)
219 
220 /*  MTL interrupt */
221 #define MTL_RX_OVERFLOW_INT_EN		BIT(24)
222 #define MTL_RX_OVERFLOW_INT		BIT(16)
223 
224 /* Default operating mode of the MAC */
225 #define GMAC_CORE_INIT (GMAC_CONFIG_JD | GMAC_CONFIG_PS | GMAC_CONFIG_ACS | \
226 			GMAC_CONFIG_BE | GMAC_CONFIG_DCRS)
227 
228 /* To dump the core regs excluding  the Address Registers */
229 #define	GMAC_REG_NUM	132
230 
231 /*  MTL debug */
232 #define MTL_DEBUG_TXSTSFSTS		BIT(5)
233 #define MTL_DEBUG_TXFSTS		BIT(4)
234 #define MTL_DEBUG_TWCSTS		BIT(3)
235 
236 /* MTL debug: Tx FIFO Read Controller Status */
237 #define MTL_DEBUG_TRCSTS_MASK		GENMASK(2, 1)
238 #define MTL_DEBUG_TRCSTS_SHIFT		1
239 #define MTL_DEBUG_TRCSTS_IDLE		0
240 #define MTL_DEBUG_TRCSTS_READ		1
241 #define MTL_DEBUG_TRCSTS_TXW		2
242 #define MTL_DEBUG_TRCSTS_WRITE		3
243 #define MTL_DEBUG_TXPAUSED		BIT(0)
244 
245 /* MAC debug: GMII or MII Transmit Protocol Engine Status */
246 #define MTL_DEBUG_RXFSTS_MASK		GENMASK(5, 4)
247 #define MTL_DEBUG_RXFSTS_SHIFT		4
248 #define MTL_DEBUG_RXFSTS_EMPTY		0
249 #define MTL_DEBUG_RXFSTS_BT		1
250 #define MTL_DEBUG_RXFSTS_AT		2
251 #define MTL_DEBUG_RXFSTS_FULL		3
252 #define MTL_DEBUG_RRCSTS_MASK		GENMASK(2, 1)
253 #define MTL_DEBUG_RRCSTS_SHIFT		1
254 #define MTL_DEBUG_RRCSTS_IDLE		0
255 #define MTL_DEBUG_RRCSTS_RDATA		1
256 #define MTL_DEBUG_RRCSTS_RSTAT		2
257 #define MTL_DEBUG_RRCSTS_FLUSH		3
258 #define MTL_DEBUG_RWCSTS		BIT(0)
259 
260 /* SGMII/RGMII status register */
261 #define GMAC_PHYIF_CTRLSTATUS_TC		BIT(0)
262 #define GMAC_PHYIF_CTRLSTATUS_LUD		BIT(1)
263 #define GMAC_PHYIF_CTRLSTATUS_SMIDRXS		BIT(4)
264 #define GMAC_PHYIF_CTRLSTATUS_LNKMOD		BIT(16)
265 #define GMAC_PHYIF_CTRLSTATUS_SPEED		GENMASK(18, 17)
266 #define GMAC_PHYIF_CTRLSTATUS_SPEED_SHIFT	17
267 #define GMAC_PHYIF_CTRLSTATUS_LNKSTS		BIT(19)
268 #define GMAC_PHYIF_CTRLSTATUS_JABTO		BIT(20)
269 #define GMAC_PHYIF_CTRLSTATUS_FALSECARDET	BIT(21)
270 /* LNKMOD */
271 #define GMAC_PHYIF_CTRLSTATUS_LNKMOD_MASK	0x1
272 /* LNKSPEED */
273 #define GMAC_PHYIF_CTRLSTATUS_SPEED_125		0x2
274 #define GMAC_PHYIF_CTRLSTATUS_SPEED_25		0x1
275 #define GMAC_PHYIF_CTRLSTATUS_SPEED_2_5		0x0
276 
277 extern const struct stmmac_dma_ops dwmac4_dma_ops;
278 extern const struct stmmac_dma_ops dwmac410_dma_ops;
279 #endif /* __DWMAC4_H__ */
280