1 /* 2 * DWMAC4 Header file. 3 * 4 * Copyright (C) 2015 STMicroelectronics Ltd 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2, as published by the Free Software Foundation. 9 * 10 * Author: Alexandre Torgue <alexandre.torgue@st.com> 11 */ 12 13 #ifndef __DWMAC4_H__ 14 #define __DWMAC4_H__ 15 16 #include "common.h" 17 18 /* MAC registers */ 19 #define GMAC_CONFIG 0x00000000 20 #define GMAC_PACKET_FILTER 0x00000008 21 #define GMAC_HASH_TAB_0_31 0x00000010 22 #define GMAC_HASH_TAB_32_63 0x00000014 23 #define GMAC_RX_FLOW_CTRL 0x00000090 24 #define GMAC_QX_TX_FLOW_CTRL(x) (0x70 + x * 4) 25 #define GMAC_INT_STATUS 0x000000b0 26 #define GMAC_INT_EN 0x000000b4 27 #define GMAC_PCS_BASE 0x000000e0 28 #define GMAC_PHYIF_CONTROL_STATUS 0x000000f8 29 #define GMAC_PMT 0x000000c0 30 #define GMAC_VERSION 0x00000110 31 #define GMAC_DEBUG 0x00000114 32 #define GMAC_HW_FEATURE0 0x0000011c 33 #define GMAC_HW_FEATURE1 0x00000120 34 #define GMAC_HW_FEATURE2 0x00000124 35 #define GMAC_MDIO_ADDR 0x00000200 36 #define GMAC_MDIO_DATA 0x00000204 37 #define GMAC_ADDR_HIGH(reg) (0x300 + reg * 8) 38 #define GMAC_ADDR_LOW(reg) (0x304 + reg * 8) 39 40 /* MAC Packet Filtering */ 41 #define GMAC_PACKET_FILTER_PR BIT(0) 42 #define GMAC_PACKET_FILTER_HMC BIT(2) 43 #define GMAC_PACKET_FILTER_PM BIT(4) 44 45 #define GMAC_MAX_PERFECT_ADDRESSES 128 46 47 /* MAC Flow Control RX */ 48 #define GMAC_RX_FLOW_CTRL_RFE BIT(0) 49 50 /* MAC Flow Control TX */ 51 #define GMAC_TX_FLOW_CTRL_TFE BIT(1) 52 #define GMAC_TX_FLOW_CTRL_PT_SHIFT 16 53 54 /* MAC Interrupt bitmap*/ 55 #define GMAC_INT_PMT_EN BIT(4) 56 #define GMAC_INT_LPI_EN BIT(5) 57 58 enum dwmac4_irq_status { 59 time_stamp_irq = 0x00001000, 60 mmc_rx_csum_offload_irq = 0x00000800, 61 mmc_tx_irq = 0x00000400, 62 mmc_rx_irq = 0x00000200, 63 mmc_irq = 0x00000100, 64 pmt_irq = 0x00000010, 65 }; 66 67 /* MAC PMT bitmap */ 68 enum power_event { 69 pointer_reset = 0x80000000, 70 global_unicast = 0x00000200, 71 wake_up_rx_frame = 0x00000040, 72 magic_frame = 0x00000020, 73 wake_up_frame_en = 0x00000004, 74 magic_pkt_en = 0x00000002, 75 power_down = 0x00000001, 76 }; 77 78 /* MAC Debug bitmap */ 79 #define GMAC_DEBUG_TFCSTS_MASK GENMASK(18, 17) 80 #define GMAC_DEBUG_TFCSTS_SHIFT 17 81 #define GMAC_DEBUG_TFCSTS_IDLE 0 82 #define GMAC_DEBUG_TFCSTS_WAIT 1 83 #define GMAC_DEBUG_TFCSTS_GEN_PAUSE 2 84 #define GMAC_DEBUG_TFCSTS_XFER 3 85 #define GMAC_DEBUG_TPESTS BIT(16) 86 #define GMAC_DEBUG_RFCFCSTS_MASK GENMASK(2, 1) 87 #define GMAC_DEBUG_RFCFCSTS_SHIFT 1 88 #define GMAC_DEBUG_RPESTS BIT(0) 89 90 /* MAC config */ 91 #define GMAC_CONFIG_IPC BIT(27) 92 #define GMAC_CONFIG_2K BIT(22) 93 #define GMAC_CONFIG_ACS BIT(20) 94 #define GMAC_CONFIG_BE BIT(18) 95 #define GMAC_CONFIG_JD BIT(17) 96 #define GMAC_CONFIG_JE BIT(16) 97 #define GMAC_CONFIG_PS BIT(15) 98 #define GMAC_CONFIG_FES BIT(14) 99 #define GMAC_CONFIG_DM BIT(13) 100 #define GMAC_CONFIG_DCRS BIT(9) 101 #define GMAC_CONFIG_TE BIT(1) 102 #define GMAC_CONFIG_RE BIT(0) 103 104 /* MAC HW features0 bitmap */ 105 #define GMAC_HW_FEAT_ADDMAC BIT(18) 106 #define GMAC_HW_FEAT_RXCOESEL BIT(16) 107 #define GMAC_HW_FEAT_TXCOSEL BIT(14) 108 #define GMAC_HW_FEAT_EEESEL BIT(13) 109 #define GMAC_HW_FEAT_TSSEL BIT(12) 110 #define GMAC_HW_FEAT_MMCSEL BIT(8) 111 #define GMAC_HW_FEAT_MGKSEL BIT(7) 112 #define GMAC_HW_FEAT_RWKSEL BIT(6) 113 #define GMAC_HW_FEAT_SMASEL BIT(5) 114 #define GMAC_HW_FEAT_VLHASH BIT(4) 115 #define GMAC_HW_FEAT_PCSSEL BIT(3) 116 #define GMAC_HW_FEAT_HDSEL BIT(2) 117 #define GMAC_HW_FEAT_GMIISEL BIT(1) 118 #define GMAC_HW_FEAT_MIISEL BIT(0) 119 120 /* MAC HW features1 bitmap */ 121 #define GMAC_HW_FEAT_AVSEL BIT(20) 122 #define GMAC_HW_TSOEN BIT(18) 123 124 /* MAC HW features2 bitmap */ 125 #define GMAC_HW_FEAT_TXCHCNT GENMASK(21, 18) 126 #define GMAC_HW_FEAT_RXCHCNT GENMASK(15, 12) 127 128 /* MAC HW ADDR regs */ 129 #define GMAC_HI_DCS GENMASK(18, 16) 130 #define GMAC_HI_DCS_SHIFT 16 131 #define GMAC_HI_REG_AE BIT(31) 132 133 /* MTL registers */ 134 #define MTL_INT_STATUS 0x00000c20 135 #define MTL_INT_Q0 BIT(0) 136 137 #define MTL_CHAN_BASE_ADDR 0x00000d00 138 #define MTL_CHAN_BASE_OFFSET 0x40 139 #define MTL_CHANX_BASE_ADDR(x) (MTL_CHAN_BASE_ADDR + \ 140 (x * MTL_CHAN_BASE_OFFSET)) 141 142 #define MTL_CHAN_TX_OP_MODE(x) MTL_CHANX_BASE_ADDR(x) 143 #define MTL_CHAN_TX_DEBUG(x) (MTL_CHANX_BASE_ADDR(x) + 0x8) 144 #define MTL_CHAN_INT_CTRL(x) (MTL_CHANX_BASE_ADDR(x) + 0x2c) 145 #define MTL_CHAN_RX_OP_MODE(x) (MTL_CHANX_BASE_ADDR(x) + 0x30) 146 #define MTL_CHAN_RX_DEBUG(x) (MTL_CHANX_BASE_ADDR(x) + 0x38) 147 148 #define MTL_OP_MODE_RSF BIT(5) 149 #define MTL_OP_MODE_TSF BIT(1) 150 151 #define MTL_OP_MODE_TTC_MASK 0x70 152 #define MTL_OP_MODE_TTC_SHIFT 4 153 154 #define MTL_OP_MODE_TTC_32 0 155 #define MTL_OP_MODE_TTC_64 (1 << MTL_OP_MODE_TTC_SHIFT) 156 #define MTL_OP_MODE_TTC_96 (2 << MTL_OP_MODE_TTC_SHIFT) 157 #define MTL_OP_MODE_TTC_128 (3 << MTL_OP_MODE_TTC_SHIFT) 158 #define MTL_OP_MODE_TTC_192 (4 << MTL_OP_MODE_TTC_SHIFT) 159 #define MTL_OP_MODE_TTC_256 (5 << MTL_OP_MODE_TTC_SHIFT) 160 #define MTL_OP_MODE_TTC_384 (6 << MTL_OP_MODE_TTC_SHIFT) 161 #define MTL_OP_MODE_TTC_512 (7 << MTL_OP_MODE_TTC_SHIFT) 162 163 #define MTL_OP_MODE_RTC_MASK 0x18 164 #define MTL_OP_MODE_RTC_SHIFT 3 165 166 #define MTL_OP_MODE_RTC_32 (1 << MTL_OP_MODE_RTC_SHIFT) 167 #define MTL_OP_MODE_RTC_64 0 168 #define MTL_OP_MODE_RTC_96 (2 << MTL_OP_MODE_RTC_SHIFT) 169 #define MTL_OP_MODE_RTC_128 (3 << MTL_OP_MODE_RTC_SHIFT) 170 171 /* MTL debug */ 172 #define MTL_DEBUG_TXSTSFSTS BIT(5) 173 #define MTL_DEBUG_TXFSTS BIT(4) 174 #define MTL_DEBUG_TWCSTS BIT(3) 175 176 /* MTL debug: Tx FIFO Read Controller Status */ 177 #define MTL_DEBUG_TRCSTS_MASK GENMASK(2, 1) 178 #define MTL_DEBUG_TRCSTS_SHIFT 1 179 #define MTL_DEBUG_TRCSTS_IDLE 0 180 #define MTL_DEBUG_TRCSTS_READ 1 181 #define MTL_DEBUG_TRCSTS_TXW 2 182 #define MTL_DEBUG_TRCSTS_WRITE 3 183 #define MTL_DEBUG_TXPAUSED BIT(0) 184 185 /* MAC debug: GMII or MII Transmit Protocol Engine Status */ 186 #define MTL_DEBUG_RXFSTS_MASK GENMASK(5, 4) 187 #define MTL_DEBUG_RXFSTS_SHIFT 4 188 #define MTL_DEBUG_RXFSTS_EMPTY 0 189 #define MTL_DEBUG_RXFSTS_BT 1 190 #define MTL_DEBUG_RXFSTS_AT 2 191 #define MTL_DEBUG_RXFSTS_FULL 3 192 #define MTL_DEBUG_RRCSTS_MASK GENMASK(2, 1) 193 #define MTL_DEBUG_RRCSTS_SHIFT 1 194 #define MTL_DEBUG_RRCSTS_IDLE 0 195 #define MTL_DEBUG_RRCSTS_RDATA 1 196 #define MTL_DEBUG_RRCSTS_RSTAT 2 197 #define MTL_DEBUG_RRCSTS_FLUSH 3 198 #define MTL_DEBUG_RWCSTS BIT(0) 199 200 /* MTL interrupt */ 201 #define MTL_RX_OVERFLOW_INT_EN BIT(24) 202 #define MTL_RX_OVERFLOW_INT BIT(16) 203 204 /* Default operating mode of the MAC */ 205 #define GMAC_CORE_INIT (GMAC_CONFIG_JD | GMAC_CONFIG_PS | GMAC_CONFIG_ACS | \ 206 GMAC_CONFIG_BE | GMAC_CONFIG_DCRS) 207 208 /* To dump the core regs excluding the Address Registers */ 209 #define GMAC_REG_NUM 132 210 211 /* MTL debug */ 212 #define MTL_DEBUG_TXSTSFSTS BIT(5) 213 #define MTL_DEBUG_TXFSTS BIT(4) 214 #define MTL_DEBUG_TWCSTS BIT(3) 215 216 /* MTL debug: Tx FIFO Read Controller Status */ 217 #define MTL_DEBUG_TRCSTS_MASK GENMASK(2, 1) 218 #define MTL_DEBUG_TRCSTS_SHIFT 1 219 #define MTL_DEBUG_TRCSTS_IDLE 0 220 #define MTL_DEBUG_TRCSTS_READ 1 221 #define MTL_DEBUG_TRCSTS_TXW 2 222 #define MTL_DEBUG_TRCSTS_WRITE 3 223 #define MTL_DEBUG_TXPAUSED BIT(0) 224 225 /* MAC debug: GMII or MII Transmit Protocol Engine Status */ 226 #define MTL_DEBUG_RXFSTS_MASK GENMASK(5, 4) 227 #define MTL_DEBUG_RXFSTS_SHIFT 4 228 #define MTL_DEBUG_RXFSTS_EMPTY 0 229 #define MTL_DEBUG_RXFSTS_BT 1 230 #define MTL_DEBUG_RXFSTS_AT 2 231 #define MTL_DEBUG_RXFSTS_FULL 3 232 #define MTL_DEBUG_RRCSTS_MASK GENMASK(2, 1) 233 #define MTL_DEBUG_RRCSTS_SHIFT 1 234 #define MTL_DEBUG_RRCSTS_IDLE 0 235 #define MTL_DEBUG_RRCSTS_RDATA 1 236 #define MTL_DEBUG_RRCSTS_RSTAT 2 237 #define MTL_DEBUG_RRCSTS_FLUSH 3 238 #define MTL_DEBUG_RWCSTS BIT(0) 239 240 /* SGMII/RGMII status register */ 241 #define GMAC_PHYIF_CTRLSTATUS_TC BIT(0) 242 #define GMAC_PHYIF_CTRLSTATUS_LUD BIT(1) 243 #define GMAC_PHYIF_CTRLSTATUS_SMIDRXS BIT(4) 244 #define GMAC_PHYIF_CTRLSTATUS_LNKMOD BIT(16) 245 #define GMAC_PHYIF_CTRLSTATUS_SPEED GENMASK(18, 17) 246 #define GMAC_PHYIF_CTRLSTATUS_SPEED_SHIFT 17 247 #define GMAC_PHYIF_CTRLSTATUS_LNKSTS BIT(19) 248 #define GMAC_PHYIF_CTRLSTATUS_JABTO BIT(20) 249 #define GMAC_PHYIF_CTRLSTATUS_FALSECARDET BIT(21) 250 /* LNKMOD */ 251 #define GMAC_PHYIF_CTRLSTATUS_LNKMOD_MASK 0x1 252 /* LNKSPEED */ 253 #define GMAC_PHYIF_CTRLSTATUS_SPEED_125 0x2 254 #define GMAC_PHYIF_CTRLSTATUS_SPEED_25 0x1 255 #define GMAC_PHYIF_CTRLSTATUS_SPEED_2_5 0x0 256 257 extern const struct stmmac_dma_ops dwmac4_dma_ops; 258 extern const struct stmmac_dma_ops dwmac410_dma_ops; 259 #endif /* __DWMAC4_H__ */ 260