1 /* 2 * DWMAC4 Header file. 3 * 4 * Copyright (C) 2015 STMicroelectronics Ltd 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2, as published by the Free Software Foundation. 9 * 10 * Author: Alexandre Torgue <alexandre.torgue@st.com> 11 */ 12 13 #ifndef __DWMAC4_H__ 14 #define __DWMAC4_H__ 15 16 #include "common.h" 17 18 /* MAC registers */ 19 #define GMAC_CONFIG 0x00000000 20 #define GMAC_PACKET_FILTER 0x00000008 21 #define GMAC_HASH_TAB_0_31 0x00000010 22 #define GMAC_HASH_TAB_32_63 0x00000014 23 #define GMAC_RX_FLOW_CTRL 0x00000090 24 #define GMAC_QX_TX_FLOW_CTRL(x) (0x70 + x * 4) 25 #define GMAC_RXQ_CTRL0 0x000000a0 26 #define GMAC_INT_STATUS 0x000000b0 27 #define GMAC_INT_EN 0x000000b4 28 #define GMAC_PCS_BASE 0x000000e0 29 #define GMAC_PHYIF_CONTROL_STATUS 0x000000f8 30 #define GMAC_PMT 0x000000c0 31 #define GMAC_VERSION 0x00000110 32 #define GMAC_DEBUG 0x00000114 33 #define GMAC_HW_FEATURE0 0x0000011c 34 #define GMAC_HW_FEATURE1 0x00000120 35 #define GMAC_HW_FEATURE2 0x00000124 36 #define GMAC_MDIO_ADDR 0x00000200 37 #define GMAC_MDIO_DATA 0x00000204 38 #define GMAC_ADDR_HIGH(reg) (0x300 + reg * 8) 39 #define GMAC_ADDR_LOW(reg) (0x304 + reg * 8) 40 41 /* MAC Packet Filtering */ 42 #define GMAC_PACKET_FILTER_PR BIT(0) 43 #define GMAC_PACKET_FILTER_HMC BIT(2) 44 #define GMAC_PACKET_FILTER_PM BIT(4) 45 46 #define GMAC_MAX_PERFECT_ADDRESSES 128 47 48 /* MAC RX Queue Enable */ 49 #define GMAC_RX_QUEUE_CLEAR(queue) ~(GENMASK(1, 0) << ((queue) * 2)) 50 #define GMAC_RX_AV_QUEUE_ENABLE(queue) BIT((queue) * 2) 51 #define GMAC_RX_DCB_QUEUE_ENABLE(queue) BIT(((queue) * 2) + 1) 52 53 /* MAC Flow Control RX */ 54 #define GMAC_RX_FLOW_CTRL_RFE BIT(0) 55 56 /* MAC Flow Control TX */ 57 #define GMAC_TX_FLOW_CTRL_TFE BIT(1) 58 #define GMAC_TX_FLOW_CTRL_PT_SHIFT 16 59 60 /* MAC Interrupt bitmap*/ 61 #define GMAC_INT_RGSMIIS BIT(0) 62 #define GMAC_INT_PCS_LINK BIT(1) 63 #define GMAC_INT_PCS_ANE BIT(2) 64 #define GMAC_INT_PCS_PHYIS BIT(3) 65 #define GMAC_INT_PMT_EN BIT(4) 66 #define GMAC_INT_LPI_EN BIT(5) 67 68 #define GMAC_PCS_IRQ_DEFAULT (GMAC_INT_RGSMIIS | GMAC_INT_PCS_LINK | \ 69 GMAC_INT_PCS_ANE) 70 71 #define GMAC_INT_DEFAULT_MASK GMAC_INT_PMT_EN 72 73 enum dwmac4_irq_status { 74 time_stamp_irq = 0x00001000, 75 mmc_rx_csum_offload_irq = 0x00000800, 76 mmc_tx_irq = 0x00000400, 77 mmc_rx_irq = 0x00000200, 78 mmc_irq = 0x00000100, 79 pmt_irq = 0x00000010, 80 }; 81 82 /* MAC PMT bitmap */ 83 enum power_event { 84 pointer_reset = 0x80000000, 85 global_unicast = 0x00000200, 86 wake_up_rx_frame = 0x00000040, 87 magic_frame = 0x00000020, 88 wake_up_frame_en = 0x00000004, 89 magic_pkt_en = 0x00000002, 90 power_down = 0x00000001, 91 }; 92 93 /* Energy Efficient Ethernet (EEE) for GMAC4 94 * 95 * LPI status, timer and control register offset 96 */ 97 #define GMAC4_LPI_CTRL_STATUS 0xd0 98 #define GMAC4_LPI_TIMER_CTRL 0xd4 99 100 /* LPI control and status defines */ 101 #define GMAC4_LPI_CTRL_STATUS_LPITXA BIT(19) /* Enable LPI TX Automate */ 102 #define GMAC4_LPI_CTRL_STATUS_PLS BIT(17) /* PHY Link Status */ 103 #define GMAC4_LPI_CTRL_STATUS_LPIEN BIT(16) /* LPI Enable */ 104 105 /* MAC Debug bitmap */ 106 #define GMAC_DEBUG_TFCSTS_MASK GENMASK(18, 17) 107 #define GMAC_DEBUG_TFCSTS_SHIFT 17 108 #define GMAC_DEBUG_TFCSTS_IDLE 0 109 #define GMAC_DEBUG_TFCSTS_WAIT 1 110 #define GMAC_DEBUG_TFCSTS_GEN_PAUSE 2 111 #define GMAC_DEBUG_TFCSTS_XFER 3 112 #define GMAC_DEBUG_TPESTS BIT(16) 113 #define GMAC_DEBUG_RFCFCSTS_MASK GENMASK(2, 1) 114 #define GMAC_DEBUG_RFCFCSTS_SHIFT 1 115 #define GMAC_DEBUG_RPESTS BIT(0) 116 117 /* MAC config */ 118 #define GMAC_CONFIG_IPC BIT(27) 119 #define GMAC_CONFIG_2K BIT(22) 120 #define GMAC_CONFIG_ACS BIT(20) 121 #define GMAC_CONFIG_BE BIT(18) 122 #define GMAC_CONFIG_JD BIT(17) 123 #define GMAC_CONFIG_JE BIT(16) 124 #define GMAC_CONFIG_PS BIT(15) 125 #define GMAC_CONFIG_FES BIT(14) 126 #define GMAC_CONFIG_DM BIT(13) 127 #define GMAC_CONFIG_DCRS BIT(9) 128 #define GMAC_CONFIG_TE BIT(1) 129 #define GMAC_CONFIG_RE BIT(0) 130 131 /* MAC HW features0 bitmap */ 132 #define GMAC_HW_FEAT_ADDMAC BIT(18) 133 #define GMAC_HW_FEAT_RXCOESEL BIT(16) 134 #define GMAC_HW_FEAT_TXCOSEL BIT(14) 135 #define GMAC_HW_FEAT_EEESEL BIT(13) 136 #define GMAC_HW_FEAT_TSSEL BIT(12) 137 #define GMAC_HW_FEAT_MMCSEL BIT(8) 138 #define GMAC_HW_FEAT_MGKSEL BIT(7) 139 #define GMAC_HW_FEAT_RWKSEL BIT(6) 140 #define GMAC_HW_FEAT_SMASEL BIT(5) 141 #define GMAC_HW_FEAT_VLHASH BIT(4) 142 #define GMAC_HW_FEAT_PCSSEL BIT(3) 143 #define GMAC_HW_FEAT_HDSEL BIT(2) 144 #define GMAC_HW_FEAT_GMIISEL BIT(1) 145 #define GMAC_HW_FEAT_MIISEL BIT(0) 146 147 /* MAC HW features1 bitmap */ 148 #define GMAC_HW_FEAT_AVSEL BIT(20) 149 #define GMAC_HW_TSOEN BIT(18) 150 151 /* MAC HW features2 bitmap */ 152 #define GMAC_HW_FEAT_TXCHCNT GENMASK(21, 18) 153 #define GMAC_HW_FEAT_RXCHCNT GENMASK(15, 12) 154 #define GMAC_HW_FEAT_TXQCNT GENMASK(9, 6) 155 #define GMAC_HW_FEAT_RXQCNT GENMASK(3, 0) 156 157 /* MAC HW ADDR regs */ 158 #define GMAC_HI_DCS GENMASK(18, 16) 159 #define GMAC_HI_DCS_SHIFT 16 160 #define GMAC_HI_REG_AE BIT(31) 161 162 /* MTL registers */ 163 #define MTL_INT_STATUS 0x00000c20 164 #define MTL_INT_Q0 BIT(0) 165 166 #define MTL_CHAN_BASE_ADDR 0x00000d00 167 #define MTL_CHAN_BASE_OFFSET 0x40 168 #define MTL_CHANX_BASE_ADDR(x) (MTL_CHAN_BASE_ADDR + \ 169 (x * MTL_CHAN_BASE_OFFSET)) 170 171 #define MTL_CHAN_TX_OP_MODE(x) MTL_CHANX_BASE_ADDR(x) 172 #define MTL_CHAN_TX_DEBUG(x) (MTL_CHANX_BASE_ADDR(x) + 0x8) 173 #define MTL_CHAN_INT_CTRL(x) (MTL_CHANX_BASE_ADDR(x) + 0x2c) 174 #define MTL_CHAN_RX_OP_MODE(x) (MTL_CHANX_BASE_ADDR(x) + 0x30) 175 #define MTL_CHAN_RX_DEBUG(x) (MTL_CHANX_BASE_ADDR(x) + 0x38) 176 177 #define MTL_OP_MODE_RSF BIT(5) 178 #define MTL_OP_MODE_TXQEN BIT(3) 179 #define MTL_OP_MODE_TSF BIT(1) 180 181 #define MTL_OP_MODE_TQS_MASK GENMASK(24, 16) 182 183 #define MTL_OP_MODE_TTC_MASK 0x70 184 #define MTL_OP_MODE_TTC_SHIFT 4 185 186 #define MTL_OP_MODE_TTC_32 0 187 #define MTL_OP_MODE_TTC_64 (1 << MTL_OP_MODE_TTC_SHIFT) 188 #define MTL_OP_MODE_TTC_96 (2 << MTL_OP_MODE_TTC_SHIFT) 189 #define MTL_OP_MODE_TTC_128 (3 << MTL_OP_MODE_TTC_SHIFT) 190 #define MTL_OP_MODE_TTC_192 (4 << MTL_OP_MODE_TTC_SHIFT) 191 #define MTL_OP_MODE_TTC_256 (5 << MTL_OP_MODE_TTC_SHIFT) 192 #define MTL_OP_MODE_TTC_384 (6 << MTL_OP_MODE_TTC_SHIFT) 193 #define MTL_OP_MODE_TTC_512 (7 << MTL_OP_MODE_TTC_SHIFT) 194 195 #define MTL_OP_MODE_RTC_MASK 0x18 196 #define MTL_OP_MODE_RTC_SHIFT 3 197 198 #define MTL_OP_MODE_RTC_32 (1 << MTL_OP_MODE_RTC_SHIFT) 199 #define MTL_OP_MODE_RTC_64 0 200 #define MTL_OP_MODE_RTC_96 (2 << MTL_OP_MODE_RTC_SHIFT) 201 #define MTL_OP_MODE_RTC_128 (3 << MTL_OP_MODE_RTC_SHIFT) 202 203 /* MTL debug */ 204 #define MTL_DEBUG_TXSTSFSTS BIT(5) 205 #define MTL_DEBUG_TXFSTS BIT(4) 206 #define MTL_DEBUG_TWCSTS BIT(3) 207 208 /* MTL debug: Tx FIFO Read Controller Status */ 209 #define MTL_DEBUG_TRCSTS_MASK GENMASK(2, 1) 210 #define MTL_DEBUG_TRCSTS_SHIFT 1 211 #define MTL_DEBUG_TRCSTS_IDLE 0 212 #define MTL_DEBUG_TRCSTS_READ 1 213 #define MTL_DEBUG_TRCSTS_TXW 2 214 #define MTL_DEBUG_TRCSTS_WRITE 3 215 #define MTL_DEBUG_TXPAUSED BIT(0) 216 217 /* MAC debug: GMII or MII Transmit Protocol Engine Status */ 218 #define MTL_DEBUG_RXFSTS_MASK GENMASK(5, 4) 219 #define MTL_DEBUG_RXFSTS_SHIFT 4 220 #define MTL_DEBUG_RXFSTS_EMPTY 0 221 #define MTL_DEBUG_RXFSTS_BT 1 222 #define MTL_DEBUG_RXFSTS_AT 2 223 #define MTL_DEBUG_RXFSTS_FULL 3 224 #define MTL_DEBUG_RRCSTS_MASK GENMASK(2, 1) 225 #define MTL_DEBUG_RRCSTS_SHIFT 1 226 #define MTL_DEBUG_RRCSTS_IDLE 0 227 #define MTL_DEBUG_RRCSTS_RDATA 1 228 #define MTL_DEBUG_RRCSTS_RSTAT 2 229 #define MTL_DEBUG_RRCSTS_FLUSH 3 230 #define MTL_DEBUG_RWCSTS BIT(0) 231 232 /* MTL interrupt */ 233 #define MTL_RX_OVERFLOW_INT_EN BIT(24) 234 #define MTL_RX_OVERFLOW_INT BIT(16) 235 236 /* Default operating mode of the MAC */ 237 #define GMAC_CORE_INIT (GMAC_CONFIG_JD | GMAC_CONFIG_PS | GMAC_CONFIG_ACS | \ 238 GMAC_CONFIG_BE | GMAC_CONFIG_DCRS) 239 240 /* To dump the core regs excluding the Address Registers */ 241 #define GMAC_REG_NUM 132 242 243 /* MTL debug */ 244 #define MTL_DEBUG_TXSTSFSTS BIT(5) 245 #define MTL_DEBUG_TXFSTS BIT(4) 246 #define MTL_DEBUG_TWCSTS BIT(3) 247 248 /* MTL debug: Tx FIFO Read Controller Status */ 249 #define MTL_DEBUG_TRCSTS_MASK GENMASK(2, 1) 250 #define MTL_DEBUG_TRCSTS_SHIFT 1 251 #define MTL_DEBUG_TRCSTS_IDLE 0 252 #define MTL_DEBUG_TRCSTS_READ 1 253 #define MTL_DEBUG_TRCSTS_TXW 2 254 #define MTL_DEBUG_TRCSTS_WRITE 3 255 #define MTL_DEBUG_TXPAUSED BIT(0) 256 257 /* MAC debug: GMII or MII Transmit Protocol Engine Status */ 258 #define MTL_DEBUG_RXFSTS_MASK GENMASK(5, 4) 259 #define MTL_DEBUG_RXFSTS_SHIFT 4 260 #define MTL_DEBUG_RXFSTS_EMPTY 0 261 #define MTL_DEBUG_RXFSTS_BT 1 262 #define MTL_DEBUG_RXFSTS_AT 2 263 #define MTL_DEBUG_RXFSTS_FULL 3 264 #define MTL_DEBUG_RRCSTS_MASK GENMASK(2, 1) 265 #define MTL_DEBUG_RRCSTS_SHIFT 1 266 #define MTL_DEBUG_RRCSTS_IDLE 0 267 #define MTL_DEBUG_RRCSTS_RDATA 1 268 #define MTL_DEBUG_RRCSTS_RSTAT 2 269 #define MTL_DEBUG_RRCSTS_FLUSH 3 270 #define MTL_DEBUG_RWCSTS BIT(0) 271 272 /* SGMII/RGMII status register */ 273 #define GMAC_PHYIF_CTRLSTATUS_TC BIT(0) 274 #define GMAC_PHYIF_CTRLSTATUS_LUD BIT(1) 275 #define GMAC_PHYIF_CTRLSTATUS_SMIDRXS BIT(4) 276 #define GMAC_PHYIF_CTRLSTATUS_LNKMOD BIT(16) 277 #define GMAC_PHYIF_CTRLSTATUS_SPEED GENMASK(18, 17) 278 #define GMAC_PHYIF_CTRLSTATUS_SPEED_SHIFT 17 279 #define GMAC_PHYIF_CTRLSTATUS_LNKSTS BIT(19) 280 #define GMAC_PHYIF_CTRLSTATUS_JABTO BIT(20) 281 #define GMAC_PHYIF_CTRLSTATUS_FALSECARDET BIT(21) 282 /* LNKMOD */ 283 #define GMAC_PHYIF_CTRLSTATUS_LNKMOD_MASK 0x1 284 /* LNKSPEED */ 285 #define GMAC_PHYIF_CTRLSTATUS_SPEED_125 0x2 286 #define GMAC_PHYIF_CTRLSTATUS_SPEED_25 0x1 287 #define GMAC_PHYIF_CTRLSTATUS_SPEED_2_5 0x0 288 289 extern const struct stmmac_dma_ops dwmac4_dma_ops; 290 extern const struct stmmac_dma_ops dwmac410_dma_ops; 291 #endif /* __DWMAC4_H__ */ 292