1 /*
2  * DWMAC4 Header file.
3  *
4  * Copyright (C) 2015  STMicroelectronics Ltd
5  *
6  * This program is free software; you can redistribute it and/or modify it
7  * under the terms and conditions of the GNU General Public License,
8  * version 2, as published by the Free Software Foundation.
9  *
10  * Author: Alexandre Torgue <alexandre.torgue@st.com>
11  */
12 
13 #ifndef __DWMAC4_H__
14 #define __DWMAC4_H__
15 
16 #include "common.h"
17 
18 /*  MAC registers */
19 #define GMAC_CONFIG			0x00000000
20 #define GMAC_PACKET_FILTER		0x00000008
21 #define GMAC_HASH_TAB_0_31		0x00000010
22 #define GMAC_HASH_TAB_32_63		0x00000014
23 #define GMAC_RX_FLOW_CTRL		0x00000090
24 #define GMAC_QX_TX_FLOW_CTRL(x)		(0x70 + x * 4)
25 #define GMAC_TXQ_PRTY_MAP0		0x98
26 #define GMAC_TXQ_PRTY_MAP1		0x9C
27 #define GMAC_RXQ_CTRL0			0x000000a0
28 #define GMAC_RXQ_CTRL1			0x000000a4
29 #define GMAC_RXQ_CTRL2			0x000000a8
30 #define GMAC_RXQ_CTRL3			0x000000ac
31 #define GMAC_INT_STATUS			0x000000b0
32 #define GMAC_INT_EN			0x000000b4
33 #define GMAC_1US_TIC_COUNTER		0x000000dc
34 #define GMAC_PCS_BASE			0x000000e0
35 #define GMAC_PHYIF_CONTROL_STATUS	0x000000f8
36 #define GMAC_PMT			0x000000c0
37 #define GMAC_DEBUG			0x00000114
38 #define GMAC_HW_FEATURE0		0x0000011c
39 #define GMAC_HW_FEATURE1		0x00000120
40 #define GMAC_HW_FEATURE2		0x00000124
41 #define GMAC_HW_FEATURE3		0x00000128
42 #define GMAC_MDIO_ADDR			0x00000200
43 #define GMAC_MDIO_DATA			0x00000204
44 #define GMAC_ADDR_HIGH(reg)		(0x300 + reg * 8)
45 #define GMAC_ADDR_LOW(reg)		(0x304 + reg * 8)
46 
47 /* RX Queues Routing */
48 #define GMAC_RXQCTRL_AVCPQ_MASK		GENMASK(2, 0)
49 #define GMAC_RXQCTRL_AVCPQ_SHIFT	0
50 #define GMAC_RXQCTRL_PTPQ_MASK		GENMASK(6, 4)
51 #define GMAC_RXQCTRL_PTPQ_SHIFT		4
52 #define GMAC_RXQCTRL_DCBCPQ_MASK	GENMASK(10, 8)
53 #define GMAC_RXQCTRL_DCBCPQ_SHIFT	8
54 #define GMAC_RXQCTRL_UPQ_MASK		GENMASK(14, 12)
55 #define GMAC_RXQCTRL_UPQ_SHIFT		12
56 #define GMAC_RXQCTRL_MCBCQ_MASK		GENMASK(18, 16)
57 #define GMAC_RXQCTRL_MCBCQ_SHIFT	16
58 #define GMAC_RXQCTRL_MCBCQEN		BIT(20)
59 #define GMAC_RXQCTRL_MCBCQEN_SHIFT	20
60 #define GMAC_RXQCTRL_TACPQE		BIT(21)
61 #define GMAC_RXQCTRL_TACPQE_SHIFT	21
62 
63 /* MAC Packet Filtering */
64 #define GMAC_PACKET_FILTER_PR		BIT(0)
65 #define GMAC_PACKET_FILTER_HMC		BIT(2)
66 #define GMAC_PACKET_FILTER_PM		BIT(4)
67 
68 #define GMAC_MAX_PERFECT_ADDRESSES	128
69 
70 /* MAC RX Queue Enable */
71 #define GMAC_RX_QUEUE_CLEAR(queue)	~(GENMASK(1, 0) << ((queue) * 2))
72 #define GMAC_RX_AV_QUEUE_ENABLE(queue)	BIT((queue) * 2)
73 #define GMAC_RX_DCB_QUEUE_ENABLE(queue)	BIT(((queue) * 2) + 1)
74 
75 /* MAC Flow Control RX */
76 #define GMAC_RX_FLOW_CTRL_RFE		BIT(0)
77 
78 /* RX Queues Priorities */
79 #define GMAC_RXQCTRL_PSRQX_MASK(x)	GENMASK(7 + ((x) * 8), 0 + ((x) * 8))
80 #define GMAC_RXQCTRL_PSRQX_SHIFT(x)	((x) * 8)
81 
82 /* TX Queues Priorities */
83 #define GMAC_TXQCTRL_PSTQX_MASK(x)	GENMASK(7 + ((x) * 8), 0 + ((x) * 8))
84 #define GMAC_TXQCTRL_PSTQX_SHIFT(x)	((x) * 8)
85 
86 /* MAC Flow Control TX */
87 #define GMAC_TX_FLOW_CTRL_TFE		BIT(1)
88 #define GMAC_TX_FLOW_CTRL_PT_SHIFT	16
89 
90 /*  MAC Interrupt bitmap*/
91 #define GMAC_INT_RGSMIIS		BIT(0)
92 #define GMAC_INT_PCS_LINK		BIT(1)
93 #define GMAC_INT_PCS_ANE		BIT(2)
94 #define GMAC_INT_PCS_PHYIS		BIT(3)
95 #define GMAC_INT_PMT_EN			BIT(4)
96 #define GMAC_INT_LPI_EN			BIT(5)
97 
98 #define	GMAC_PCS_IRQ_DEFAULT	(GMAC_INT_RGSMIIS | GMAC_INT_PCS_LINK |	\
99 				 GMAC_INT_PCS_ANE)
100 
101 #define	GMAC_INT_DEFAULT_ENABLE	(GMAC_INT_PMT_EN | GMAC_INT_LPI_EN)
102 
103 enum dwmac4_irq_status {
104 	time_stamp_irq = 0x00001000,
105 	mmc_rx_csum_offload_irq = 0x00000800,
106 	mmc_tx_irq = 0x00000400,
107 	mmc_rx_irq = 0x00000200,
108 	mmc_irq = 0x00000100,
109 	lpi_irq = 0x00000020,
110 	pmt_irq = 0x00000010,
111 };
112 
113 /* MAC PMT bitmap */
114 enum power_event {
115 	pointer_reset =	0x80000000,
116 	global_unicast = 0x00000200,
117 	wake_up_rx_frame = 0x00000040,
118 	magic_frame = 0x00000020,
119 	wake_up_frame_en = 0x00000004,
120 	magic_pkt_en = 0x00000002,
121 	power_down = 0x00000001,
122 };
123 
124 /* Energy Efficient Ethernet (EEE) for GMAC4
125  *
126  * LPI status, timer and control register offset
127  */
128 #define GMAC4_LPI_CTRL_STATUS	0xd0
129 #define GMAC4_LPI_TIMER_CTRL	0xd4
130 
131 /* LPI control and status defines */
132 #define GMAC4_LPI_CTRL_STATUS_LPITCSE	BIT(21)	/* LPI Tx Clock Stop Enable */
133 #define GMAC4_LPI_CTRL_STATUS_LPITXA	BIT(19)	/* Enable LPI TX Automate */
134 #define GMAC4_LPI_CTRL_STATUS_PLS	BIT(17) /* PHY Link Status */
135 #define GMAC4_LPI_CTRL_STATUS_LPIEN	BIT(16)	/* LPI Enable */
136 #define GMAC4_LPI_CTRL_STATUS_RLPIEX	BIT(3) /* Receive LPI Exit */
137 #define GMAC4_LPI_CTRL_STATUS_RLPIEN	BIT(2) /* Receive LPI Entry */
138 #define GMAC4_LPI_CTRL_STATUS_TLPIEX	BIT(1) /* Transmit LPI Exit */
139 #define GMAC4_LPI_CTRL_STATUS_TLPIEN	BIT(0) /* Transmit LPI Entry */
140 
141 /* MAC Debug bitmap */
142 #define GMAC_DEBUG_TFCSTS_MASK		GENMASK(18, 17)
143 #define GMAC_DEBUG_TFCSTS_SHIFT		17
144 #define GMAC_DEBUG_TFCSTS_IDLE		0
145 #define GMAC_DEBUG_TFCSTS_WAIT		1
146 #define GMAC_DEBUG_TFCSTS_GEN_PAUSE	2
147 #define GMAC_DEBUG_TFCSTS_XFER		3
148 #define GMAC_DEBUG_TPESTS		BIT(16)
149 #define GMAC_DEBUG_RFCFCSTS_MASK	GENMASK(2, 1)
150 #define GMAC_DEBUG_RFCFCSTS_SHIFT	1
151 #define GMAC_DEBUG_RPESTS		BIT(0)
152 
153 /* MAC config */
154 #define GMAC_CONFIG_IPC			BIT(27)
155 #define GMAC_CONFIG_2K			BIT(22)
156 #define GMAC_CONFIG_ACS			BIT(20)
157 #define GMAC_CONFIG_BE			BIT(18)
158 #define GMAC_CONFIG_JD			BIT(17)
159 #define GMAC_CONFIG_JE			BIT(16)
160 #define GMAC_CONFIG_PS			BIT(15)
161 #define GMAC_CONFIG_FES			BIT(14)
162 #define GMAC_CONFIG_DM			BIT(13)
163 #define GMAC_CONFIG_DCRS		BIT(9)
164 #define GMAC_CONFIG_TE			BIT(1)
165 #define GMAC_CONFIG_RE			BIT(0)
166 
167 /* MAC HW features0 bitmap */
168 #define GMAC_HW_FEAT_ADDMAC		BIT(18)
169 #define GMAC_HW_FEAT_RXCOESEL		BIT(16)
170 #define GMAC_HW_FEAT_TXCOSEL		BIT(14)
171 #define GMAC_HW_FEAT_EEESEL		BIT(13)
172 #define GMAC_HW_FEAT_TSSEL		BIT(12)
173 #define GMAC_HW_FEAT_MMCSEL		BIT(8)
174 #define GMAC_HW_FEAT_MGKSEL		BIT(7)
175 #define GMAC_HW_FEAT_RWKSEL		BIT(6)
176 #define GMAC_HW_FEAT_SMASEL		BIT(5)
177 #define GMAC_HW_FEAT_VLHASH		BIT(4)
178 #define GMAC_HW_FEAT_PCSSEL		BIT(3)
179 #define GMAC_HW_FEAT_HDSEL		BIT(2)
180 #define GMAC_HW_FEAT_GMIISEL		BIT(1)
181 #define GMAC_HW_FEAT_MIISEL		BIT(0)
182 
183 /* MAC HW features1 bitmap */
184 #define GMAC_HW_FEAT_AVSEL		BIT(20)
185 #define GMAC_HW_TSOEN			BIT(18)
186 #define GMAC_HW_TXFIFOSIZE		GENMASK(10, 6)
187 #define GMAC_HW_RXFIFOSIZE		GENMASK(4, 0)
188 
189 /* MAC HW features2 bitmap */
190 #define GMAC_HW_FEAT_PPSOUTNUM		GENMASK(26, 24)
191 #define GMAC_HW_FEAT_TXCHCNT		GENMASK(21, 18)
192 #define GMAC_HW_FEAT_RXCHCNT		GENMASK(15, 12)
193 #define GMAC_HW_FEAT_TXQCNT		GENMASK(9, 6)
194 #define GMAC_HW_FEAT_RXQCNT		GENMASK(3, 0)
195 
196 /* MAC HW features3 bitmap */
197 #define GMAC_HW_FEAT_ASP		GENMASK(29, 28)
198 #define GMAC_HW_FEAT_FRPES		GENMASK(14, 13)
199 #define GMAC_HW_FEAT_FRPBS		GENMASK(12, 11)
200 #define GMAC_HW_FEAT_FRPSEL		BIT(10)
201 
202 /* MAC HW ADDR regs */
203 #define GMAC_HI_DCS			GENMASK(18, 16)
204 #define GMAC_HI_DCS_SHIFT		16
205 #define GMAC_HI_REG_AE			BIT(31)
206 
207 /*  MTL registers */
208 #define MTL_OPERATION_MODE		0x00000c00
209 #define MTL_FRPE			BIT(15)
210 #define MTL_OPERATION_SCHALG_MASK	GENMASK(6, 5)
211 #define MTL_OPERATION_SCHALG_WRR	(0x0 << 5)
212 #define MTL_OPERATION_SCHALG_WFQ	(0x1 << 5)
213 #define MTL_OPERATION_SCHALG_DWRR	(0x2 << 5)
214 #define MTL_OPERATION_SCHALG_SP		(0x3 << 5)
215 #define MTL_OPERATION_RAA		BIT(2)
216 #define MTL_OPERATION_RAA_SP		(0x0 << 2)
217 #define MTL_OPERATION_RAA_WSP		(0x1 << 2)
218 
219 #define MTL_INT_STATUS			0x00000c20
220 #define MTL_INT_QX(x)			BIT(x)
221 
222 #define MTL_RXQ_DMA_MAP0		0x00000c30 /* queue 0 to 3 */
223 #define MTL_RXQ_DMA_MAP1		0x00000c34 /* queue 4 to 7 */
224 #define MTL_RXQ_DMA_Q04MDMACH_MASK	GENMASK(3, 0)
225 #define MTL_RXQ_DMA_Q04MDMACH(x)	((x) << 0)
226 #define MTL_RXQ_DMA_QXMDMACH_MASK(x)	GENMASK(11 + (8 * ((x) - 1)), 8 * (x))
227 #define MTL_RXQ_DMA_QXMDMACH(chan, q)	((chan) << (8 * (q)))
228 
229 #define MTL_CHAN_BASE_ADDR		0x00000d00
230 #define MTL_CHAN_BASE_OFFSET		0x40
231 #define MTL_CHANX_BASE_ADDR(x)		(MTL_CHAN_BASE_ADDR + \
232 					(x * MTL_CHAN_BASE_OFFSET))
233 
234 #define MTL_CHAN_TX_OP_MODE(x)		MTL_CHANX_BASE_ADDR(x)
235 #define MTL_CHAN_TX_DEBUG(x)		(MTL_CHANX_BASE_ADDR(x) + 0x8)
236 #define MTL_CHAN_INT_CTRL(x)		(MTL_CHANX_BASE_ADDR(x) + 0x2c)
237 #define MTL_CHAN_RX_OP_MODE(x)		(MTL_CHANX_BASE_ADDR(x) + 0x30)
238 #define MTL_CHAN_RX_DEBUG(x)		(MTL_CHANX_BASE_ADDR(x) + 0x38)
239 
240 #define MTL_OP_MODE_RSF			BIT(5)
241 #define MTL_OP_MODE_TXQEN_MASK		GENMASK(3, 2)
242 #define MTL_OP_MODE_TXQEN_AV		BIT(2)
243 #define MTL_OP_MODE_TXQEN		BIT(3)
244 #define MTL_OP_MODE_TSF			BIT(1)
245 
246 #define MTL_OP_MODE_TQS_MASK		GENMASK(24, 16)
247 #define MTL_OP_MODE_TQS_SHIFT		16
248 
249 #define MTL_OP_MODE_TTC_MASK		0x70
250 #define MTL_OP_MODE_TTC_SHIFT		4
251 
252 #define MTL_OP_MODE_TTC_32		0
253 #define MTL_OP_MODE_TTC_64		(1 << MTL_OP_MODE_TTC_SHIFT)
254 #define MTL_OP_MODE_TTC_96		(2 << MTL_OP_MODE_TTC_SHIFT)
255 #define MTL_OP_MODE_TTC_128		(3 << MTL_OP_MODE_TTC_SHIFT)
256 #define MTL_OP_MODE_TTC_192		(4 << MTL_OP_MODE_TTC_SHIFT)
257 #define MTL_OP_MODE_TTC_256		(5 << MTL_OP_MODE_TTC_SHIFT)
258 #define MTL_OP_MODE_TTC_384		(6 << MTL_OP_MODE_TTC_SHIFT)
259 #define MTL_OP_MODE_TTC_512		(7 << MTL_OP_MODE_TTC_SHIFT)
260 
261 #define MTL_OP_MODE_RQS_MASK		GENMASK(29, 20)
262 #define MTL_OP_MODE_RQS_SHIFT		20
263 
264 #define MTL_OP_MODE_RFD_MASK		GENMASK(19, 14)
265 #define MTL_OP_MODE_RFD_SHIFT		14
266 
267 #define MTL_OP_MODE_RFA_MASK		GENMASK(13, 8)
268 #define MTL_OP_MODE_RFA_SHIFT		8
269 
270 #define MTL_OP_MODE_EHFC		BIT(7)
271 
272 #define MTL_OP_MODE_RTC_MASK		0x18
273 #define MTL_OP_MODE_RTC_SHIFT		3
274 
275 #define MTL_OP_MODE_RTC_32		(1 << MTL_OP_MODE_RTC_SHIFT)
276 #define MTL_OP_MODE_RTC_64		0
277 #define MTL_OP_MODE_RTC_96		(2 << MTL_OP_MODE_RTC_SHIFT)
278 #define MTL_OP_MODE_RTC_128		(3 << MTL_OP_MODE_RTC_SHIFT)
279 
280 /* MTL ETS Control register */
281 #define MTL_ETS_CTRL_BASE_ADDR		0x00000d10
282 #define MTL_ETS_CTRL_BASE_OFFSET	0x40
283 #define MTL_ETSX_CTRL_BASE_ADDR(x)	(MTL_ETS_CTRL_BASE_ADDR + \
284 					((x) * MTL_ETS_CTRL_BASE_OFFSET))
285 
286 #define MTL_ETS_CTRL_CC			BIT(3)
287 #define MTL_ETS_CTRL_AVALG		BIT(2)
288 
289 /* MTL Queue Quantum Weight */
290 #define MTL_TXQ_WEIGHT_BASE_ADDR	0x00000d18
291 #define MTL_TXQ_WEIGHT_BASE_OFFSET	0x40
292 #define MTL_TXQX_WEIGHT_BASE_ADDR(x)	(MTL_TXQ_WEIGHT_BASE_ADDR + \
293 					((x) * MTL_TXQ_WEIGHT_BASE_OFFSET))
294 #define MTL_TXQ_WEIGHT_ISCQW_MASK	GENMASK(20, 0)
295 
296 /* MTL sendSlopeCredit register */
297 #define MTL_SEND_SLP_CRED_BASE_ADDR	0x00000d1c
298 #define MTL_SEND_SLP_CRED_OFFSET	0x40
299 #define MTL_SEND_SLP_CREDX_BASE_ADDR(x)	(MTL_SEND_SLP_CRED_BASE_ADDR + \
300 					((x) * MTL_SEND_SLP_CRED_OFFSET))
301 
302 #define MTL_SEND_SLP_CRED_SSC_MASK	GENMASK(13, 0)
303 
304 /* MTL hiCredit register */
305 #define MTL_HIGH_CRED_BASE_ADDR		0x00000d20
306 #define MTL_HIGH_CRED_OFFSET		0x40
307 #define MTL_HIGH_CREDX_BASE_ADDR(x)	(MTL_HIGH_CRED_BASE_ADDR + \
308 					((x) * MTL_HIGH_CRED_OFFSET))
309 
310 #define MTL_HIGH_CRED_HC_MASK		GENMASK(28, 0)
311 
312 /* MTL loCredit register */
313 #define MTL_LOW_CRED_BASE_ADDR		0x00000d24
314 #define MTL_LOW_CRED_OFFSET		0x40
315 #define MTL_LOW_CREDX_BASE_ADDR(x)	(MTL_LOW_CRED_BASE_ADDR + \
316 					((x) * MTL_LOW_CRED_OFFSET))
317 
318 #define MTL_HIGH_CRED_LC_MASK		GENMASK(28, 0)
319 
320 /*  MTL debug */
321 #define MTL_DEBUG_TXSTSFSTS		BIT(5)
322 #define MTL_DEBUG_TXFSTS		BIT(4)
323 #define MTL_DEBUG_TWCSTS		BIT(3)
324 
325 /* MTL debug: Tx FIFO Read Controller Status */
326 #define MTL_DEBUG_TRCSTS_MASK		GENMASK(2, 1)
327 #define MTL_DEBUG_TRCSTS_SHIFT		1
328 #define MTL_DEBUG_TRCSTS_IDLE		0
329 #define MTL_DEBUG_TRCSTS_READ		1
330 #define MTL_DEBUG_TRCSTS_TXW		2
331 #define MTL_DEBUG_TRCSTS_WRITE		3
332 #define MTL_DEBUG_TXPAUSED		BIT(0)
333 
334 /* MAC debug: GMII or MII Transmit Protocol Engine Status */
335 #define MTL_DEBUG_RXFSTS_MASK		GENMASK(5, 4)
336 #define MTL_DEBUG_RXFSTS_SHIFT		4
337 #define MTL_DEBUG_RXFSTS_EMPTY		0
338 #define MTL_DEBUG_RXFSTS_BT		1
339 #define MTL_DEBUG_RXFSTS_AT		2
340 #define MTL_DEBUG_RXFSTS_FULL		3
341 #define MTL_DEBUG_RRCSTS_MASK		GENMASK(2, 1)
342 #define MTL_DEBUG_RRCSTS_SHIFT		1
343 #define MTL_DEBUG_RRCSTS_IDLE		0
344 #define MTL_DEBUG_RRCSTS_RDATA		1
345 #define MTL_DEBUG_RRCSTS_RSTAT		2
346 #define MTL_DEBUG_RRCSTS_FLUSH		3
347 #define MTL_DEBUG_RWCSTS		BIT(0)
348 
349 /*  MTL interrupt */
350 #define MTL_RX_OVERFLOW_INT_EN		BIT(24)
351 #define MTL_RX_OVERFLOW_INT		BIT(16)
352 
353 /* Default operating mode of the MAC */
354 #define GMAC_CORE_INIT (GMAC_CONFIG_JD | GMAC_CONFIG_PS | \
355 			GMAC_CONFIG_BE | GMAC_CONFIG_DCRS)
356 
357 /* To dump the core regs excluding  the Address Registers */
358 #define	GMAC_REG_NUM	132
359 
360 /*  MTL debug */
361 #define MTL_DEBUG_TXSTSFSTS		BIT(5)
362 #define MTL_DEBUG_TXFSTS		BIT(4)
363 #define MTL_DEBUG_TWCSTS		BIT(3)
364 
365 /* MTL debug: Tx FIFO Read Controller Status */
366 #define MTL_DEBUG_TRCSTS_MASK		GENMASK(2, 1)
367 #define MTL_DEBUG_TRCSTS_SHIFT		1
368 #define MTL_DEBUG_TRCSTS_IDLE		0
369 #define MTL_DEBUG_TRCSTS_READ		1
370 #define MTL_DEBUG_TRCSTS_TXW		2
371 #define MTL_DEBUG_TRCSTS_WRITE		3
372 #define MTL_DEBUG_TXPAUSED		BIT(0)
373 
374 /* MAC debug: GMII or MII Transmit Protocol Engine Status */
375 #define MTL_DEBUG_RXFSTS_MASK		GENMASK(5, 4)
376 #define MTL_DEBUG_RXFSTS_SHIFT		4
377 #define MTL_DEBUG_RXFSTS_EMPTY		0
378 #define MTL_DEBUG_RXFSTS_BT		1
379 #define MTL_DEBUG_RXFSTS_AT		2
380 #define MTL_DEBUG_RXFSTS_FULL		3
381 #define MTL_DEBUG_RRCSTS_MASK		GENMASK(2, 1)
382 #define MTL_DEBUG_RRCSTS_SHIFT		1
383 #define MTL_DEBUG_RRCSTS_IDLE		0
384 #define MTL_DEBUG_RRCSTS_RDATA		1
385 #define MTL_DEBUG_RRCSTS_RSTAT		2
386 #define MTL_DEBUG_RRCSTS_FLUSH		3
387 #define MTL_DEBUG_RWCSTS		BIT(0)
388 
389 /* SGMII/RGMII status register */
390 #define GMAC_PHYIF_CTRLSTATUS_TC		BIT(0)
391 #define GMAC_PHYIF_CTRLSTATUS_LUD		BIT(1)
392 #define GMAC_PHYIF_CTRLSTATUS_SMIDRXS		BIT(4)
393 #define GMAC_PHYIF_CTRLSTATUS_LNKMOD		BIT(16)
394 #define GMAC_PHYIF_CTRLSTATUS_SPEED		GENMASK(18, 17)
395 #define GMAC_PHYIF_CTRLSTATUS_SPEED_SHIFT	17
396 #define GMAC_PHYIF_CTRLSTATUS_LNKSTS		BIT(19)
397 #define GMAC_PHYIF_CTRLSTATUS_JABTO		BIT(20)
398 #define GMAC_PHYIF_CTRLSTATUS_FALSECARDET	BIT(21)
399 /* LNKMOD */
400 #define GMAC_PHYIF_CTRLSTATUS_LNKMOD_MASK	0x1
401 /* LNKSPEED */
402 #define GMAC_PHYIF_CTRLSTATUS_SPEED_125		0x2
403 #define GMAC_PHYIF_CTRLSTATUS_SPEED_25		0x1
404 #define GMAC_PHYIF_CTRLSTATUS_SPEED_2_5		0x0
405 
406 extern const struct stmmac_dma_ops dwmac4_dma_ops;
407 extern const struct stmmac_dma_ops dwmac410_dma_ops;
408 #endif /* __DWMAC4_H__ */
409