1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include "amdgpu.h" 25 #include "gfxhub_v2_1.h" 26 27 #include "gc/gc_10_3_0_offset.h" 28 #include "gc/gc_10_3_0_sh_mask.h" 29 #include "gc/gc_10_3_0_default.h" 30 #include "navi10_enum.h" 31 32 #include "soc15_common.h" 33 34 static uint32_t gfxhub_v2_1_get_invalidate_req(unsigned int vmid, 35 uint32_t flush_type) 36 { 37 u32 req = 0; 38 39 /* invalidate using legacy mode on vmid*/ 40 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, 41 PER_VMID_INVALIDATE_REQ, 1 << vmid); 42 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type); 43 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1); 44 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1); 45 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1); 46 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1); 47 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1); 48 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, 49 CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0); 50 51 return req; 52 } 53 54 static void 55 gfxhub_v2_1_print_l2_protection_fault_status(struct amdgpu_device *adev, 56 uint32_t status) 57 { 58 dev_err(adev->dev, 59 "GCVM_L2_PROTECTION_FAULT_STATUS:0x%08X\n", 60 status); 61 dev_err(adev->dev, "\t Faulty UTCL2 client ID: 0x%lx\n", 62 REG_GET_FIELD(status, 63 GCVM_L2_PROTECTION_FAULT_STATUS, CID)); 64 dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n", 65 REG_GET_FIELD(status, 66 GCVM_L2_PROTECTION_FAULT_STATUS, MORE_FAULTS)); 67 dev_err(adev->dev, "\t WALKER_ERROR: 0x%lx\n", 68 REG_GET_FIELD(status, 69 GCVM_L2_PROTECTION_FAULT_STATUS, WALKER_ERROR)); 70 dev_err(adev->dev, "\t PERMISSION_FAULTS: 0x%lx\n", 71 REG_GET_FIELD(status, 72 GCVM_L2_PROTECTION_FAULT_STATUS, PERMISSION_FAULTS)); 73 dev_err(adev->dev, "\t MAPPING_ERROR: 0x%lx\n", 74 REG_GET_FIELD(status, 75 GCVM_L2_PROTECTION_FAULT_STATUS, MAPPING_ERROR)); 76 dev_err(adev->dev, "\t RW: 0x%lx\n", 77 REG_GET_FIELD(status, 78 GCVM_L2_PROTECTION_FAULT_STATUS, RW)); 79 } 80 81 u64 gfxhub_v2_1_get_fb_location(struct amdgpu_device *adev) 82 { 83 u64 base = RREG32_SOC15(GC, 0, mmGCMC_VM_FB_LOCATION_BASE); 84 85 base &= GCMC_VM_FB_LOCATION_BASE__FB_BASE_MASK; 86 base <<= 24; 87 88 return base; 89 } 90 91 u64 gfxhub_v2_1_get_mc_fb_offset(struct amdgpu_device *adev) 92 { 93 return (u64)RREG32_SOC15(GC, 0, mmGCMC_VM_FB_OFFSET) << 24; 94 } 95 96 void gfxhub_v2_1_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid, 97 uint64_t page_table_base) 98 { 99 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0]; 100 101 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, 102 hub->ctx_addr_distance * vmid, 103 lower_32_bits(page_table_base)); 104 105 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, 106 hub->ctx_addr_distance * vmid, 107 upper_32_bits(page_table_base)); 108 } 109 110 static void gfxhub_v2_1_init_gart_aperture_regs(struct amdgpu_device *adev) 111 { 112 uint64_t pt_base = amdgpu_gmc_pd_addr(adev->gart.bo); 113 114 gfxhub_v2_1_setup_vm_pt_regs(adev, 0, pt_base); 115 116 WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, 117 (u32)(adev->gmc.gart_start >> 12)); 118 WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, 119 (u32)(adev->gmc.gart_start >> 44)); 120 121 WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, 122 (u32)(adev->gmc.gart_end >> 12)); 123 WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, 124 (u32)(adev->gmc.gart_end >> 44)); 125 } 126 127 static void gfxhub_v2_1_init_system_aperture_regs(struct amdgpu_device *adev) 128 { 129 uint64_t value; 130 131 /* Disable AGP. */ 132 WREG32_SOC15(GC, 0, mmGCMC_VM_AGP_BASE, 0); 133 WREG32_SOC15(GC, 0, mmGCMC_VM_AGP_TOP, 0); 134 WREG32_SOC15(GC, 0, mmGCMC_VM_AGP_BOT, 0x00FFFFFF); 135 136 /* Program the system aperture low logical page number. */ 137 WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_LOW_ADDR, 138 adev->gmc.vram_start >> 18); 139 WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_HIGH_ADDR, 140 adev->gmc.vram_end >> 18); 141 142 /* Set default page address. */ 143 value = adev->vram_scratch.gpu_addr - adev->gmc.vram_start 144 + adev->vm_manager.vram_base_offset; 145 WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, 146 (u32)(value >> 12)); 147 WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, 148 (u32)(value >> 44)); 149 150 /* Program "protection fault". */ 151 WREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32, 152 (u32)(adev->dummy_page_addr >> 12)); 153 WREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32, 154 (u32)((u64)adev->dummy_page_addr >> 44)); 155 156 WREG32_FIELD15(GC, 0, GCVM_L2_PROTECTION_FAULT_CNTL2, 157 ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1); 158 } 159 160 161 static void gfxhub_v2_1_init_tlb_regs(struct amdgpu_device *adev) 162 { 163 uint32_t tmp; 164 165 /* Setup TLB control */ 166 tmp = RREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL); 167 168 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); 169 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3); 170 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, 171 ENABLE_ADVANCED_DRIVER_MODEL, 1); 172 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, 173 SYSTEM_APERTURE_UNMAPPED_ACCESS, 0); 174 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0); 175 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, 176 MTYPE, MTYPE_UC); /* UC, uncached */ 177 178 WREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL, tmp); 179 } 180 181 static void gfxhub_v2_1_init_cache_regs(struct amdgpu_device *adev) 182 { 183 uint32_t tmp; 184 185 /* Setup L2 cache */ 186 tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_CNTL); 187 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_CACHE, 1); 188 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0); 189 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, 190 ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1); 191 /* XXX for emulation, Refer to closed source code.*/ 192 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, 193 L2_PDE0_CACHE_TAG_GENERATION_MODE, 0); 194 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0); 195 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1); 196 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0); 197 WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL, tmp); 198 199 tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_CNTL2); 200 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); 201 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); 202 WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL2, tmp); 203 204 tmp = mmGCVM_L2_CNTL3_DEFAULT; 205 if (adev->gmc.translate_further) { 206 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 12); 207 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, 208 L2_CACHE_BIGK_FRAGMENT_SIZE, 9); 209 } else { 210 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 9); 211 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, 212 L2_CACHE_BIGK_FRAGMENT_SIZE, 6); 213 } 214 WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL3, tmp); 215 216 tmp = mmGCVM_L2_CNTL4_DEFAULT; 217 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0); 218 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0); 219 WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL4, tmp); 220 221 tmp = mmGCVM_L2_CNTL5_DEFAULT; 222 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL5, L2_CACHE_SMALLK_FRAGMENT_SIZE, 0); 223 WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL5, tmp); 224 } 225 226 static void gfxhub_v2_1_enable_system_domain(struct amdgpu_device *adev) 227 { 228 uint32_t tmp; 229 230 tmp = RREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_CNTL); 231 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); 232 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0); 233 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, 234 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0); 235 WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_CNTL, tmp); 236 } 237 238 static void gfxhub_v2_1_disable_identity_aperture(struct amdgpu_device *adev) 239 { 240 WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32, 241 0xFFFFFFFF); 242 WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32, 243 0x0000000F); 244 245 WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32, 246 0); 247 WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32, 248 0); 249 250 WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32, 0); 251 WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32, 0); 252 253 } 254 255 static void gfxhub_v2_1_setup_vmid_config(struct amdgpu_device *adev) 256 { 257 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0]; 258 int i; 259 uint32_t tmp; 260 261 for (i = 0; i <= 14; i++) { 262 tmp = RREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_CNTL, i); 263 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1); 264 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 265 adev->vm_manager.num_level); 266 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, 267 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 268 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, 269 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 270 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, 271 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 272 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, 273 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 274 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, 275 READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 276 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, 277 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 278 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, 279 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 280 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, 281 PAGE_TABLE_BLOCK_SIZE, 282 adev->vm_manager.block_size - 9); 283 /* Send no-retry XNACK on fault to suppress VM fault storm. */ 284 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, 285 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 286 !amdgpu_noretry); 287 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_CNTL, 288 i * hub->ctx_distance, tmp); 289 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32, 290 i * hub->ctx_addr_distance, 0); 291 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32, 292 i * hub->ctx_addr_distance, 0); 293 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32, 294 i * hub->ctx_addr_distance, 295 lower_32_bits(adev->vm_manager.max_pfn - 1)); 296 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32, 297 i * hub->ctx_addr_distance, 298 upper_32_bits(adev->vm_manager.max_pfn - 1)); 299 } 300 } 301 302 static void gfxhub_v2_1_program_invalidation(struct amdgpu_device *adev) 303 { 304 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0]; 305 unsigned i; 306 307 for (i = 0 ; i < 18; ++i) { 308 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32, 309 i * hub->eng_addr_distance, 0xffffffff); 310 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_ADDR_RANGE_HI32, 311 i * hub->eng_addr_distance, 0x1f); 312 } 313 } 314 315 int gfxhub_v2_1_gart_enable(struct amdgpu_device *adev) 316 { 317 if (amdgpu_sriov_vf(adev)) { 318 /* 319 * GCMC_VM_FB_LOCATION_BASE/TOP is NULL for VF, becuase they are 320 * VF copy registers so vbios post doesn't program them, for 321 * SRIOV driver need to program them 322 */ 323 WREG32_SOC15(GC, 0, mmGCMC_VM_FB_LOCATION_BASE, 324 adev->gmc.vram_start >> 24); 325 WREG32_SOC15(GC, 0, mmGCMC_VM_FB_LOCATION_TOP, 326 adev->gmc.vram_end >> 24); 327 } 328 329 /* GART Enable. */ 330 gfxhub_v2_1_init_gart_aperture_regs(adev); 331 gfxhub_v2_1_init_system_aperture_regs(adev); 332 gfxhub_v2_1_init_tlb_regs(adev); 333 gfxhub_v2_1_init_cache_regs(adev); 334 335 gfxhub_v2_1_enable_system_domain(adev); 336 gfxhub_v2_1_disable_identity_aperture(adev); 337 gfxhub_v2_1_setup_vmid_config(adev); 338 gfxhub_v2_1_program_invalidation(adev); 339 340 return 0; 341 } 342 343 void gfxhub_v2_1_gart_disable(struct amdgpu_device *adev) 344 { 345 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0]; 346 u32 tmp; 347 u32 i; 348 349 /* Disable all tables */ 350 for (i = 0; i < 16; i++) 351 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_CNTL, 352 i * hub->ctx_distance, 0); 353 354 /* Setup TLB control */ 355 tmp = RREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL); 356 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); 357 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, 358 ENABLE_ADVANCED_DRIVER_MODEL, 0); 359 WREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL, tmp); 360 361 /* Setup L2 cache */ 362 WREG32_FIELD15(GC, 0, GCVM_L2_CNTL, ENABLE_L2_CACHE, 0); 363 WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL3, 0); 364 } 365 366 /** 367 * gfxhub_v2_1_set_fault_enable_default - update GART/VM fault handling 368 * 369 * @adev: amdgpu_device pointer 370 * @value: true redirects VM faults to the default page 371 */ 372 void gfxhub_v2_1_set_fault_enable_default(struct amdgpu_device *adev, 373 bool value) 374 { 375 u32 tmp; 376 tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL); 377 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 378 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 379 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 380 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value); 381 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 382 PDE1_PROTECTION_FAULT_ENABLE_DEFAULT, value); 383 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 384 PDE2_PROTECTION_FAULT_ENABLE_DEFAULT, value); 385 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 386 TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT, 387 value); 388 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 389 NACK_PROTECTION_FAULT_ENABLE_DEFAULT, value); 390 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 391 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 392 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 393 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value); 394 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 395 READ_PROTECTION_FAULT_ENABLE_DEFAULT, value); 396 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 397 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 398 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 399 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 400 if (!value) { 401 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 402 CRASH_ON_NO_RETRY_FAULT, 1); 403 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 404 CRASH_ON_RETRY_FAULT, 1); 405 } 406 WREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL, tmp); 407 } 408 409 static const struct amdgpu_vmhub_funcs gfxhub_v2_1_vmhub_funcs = { 410 .print_l2_protection_fault_status = gfxhub_v2_1_print_l2_protection_fault_status, 411 .get_invalidate_req = gfxhub_v2_1_get_invalidate_req, 412 }; 413 414 void gfxhub_v2_1_init(struct amdgpu_device *adev) 415 { 416 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0]; 417 418 hub->ctx0_ptb_addr_lo32 = 419 SOC15_REG_OFFSET(GC, 0, 420 mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32); 421 hub->ctx0_ptb_addr_hi32 = 422 SOC15_REG_OFFSET(GC, 0, 423 mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32); 424 hub->vm_inv_eng0_sem = 425 SOC15_REG_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_SEM); 426 hub->vm_inv_eng0_req = 427 SOC15_REG_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_REQ); 428 hub->vm_inv_eng0_ack = 429 SOC15_REG_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_ACK); 430 hub->vm_context0_cntl = 431 SOC15_REG_OFFSET(GC, 0, mmGCVM_CONTEXT0_CNTL); 432 hub->vm_l2_pro_fault_status = 433 SOC15_REG_OFFSET(GC, 0, mmGCVM_L2_PROTECTION_FAULT_STATUS); 434 hub->vm_l2_pro_fault_cntl = 435 SOC15_REG_OFFSET(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL); 436 437 hub->ctx_distance = mmGCVM_CONTEXT1_CNTL - mmGCVM_CONTEXT0_CNTL; 438 hub->ctx_addr_distance = mmGCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 - 439 mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32; 440 hub->eng_distance = mmGCVM_INVALIDATE_ENG1_REQ - 441 mmGCVM_INVALIDATE_ENG0_REQ; 442 hub->eng_addr_distance = mmGCVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 - 443 mmGCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32; 444 445 hub->vm_cntx_cntl_vm_fault = GCVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 446 GCVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 447 GCVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 448 GCVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 449 GCVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 450 GCVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 451 GCVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK; 452 453 hub->vmhub_funcs = &gfxhub_v2_1_vmhub_funcs; 454 } 455 456 int gfxhub_v2_1_get_xgmi_info(struct amdgpu_device *adev) 457 { 458 u32 xgmi_lfb_cntl = RREG32_SOC15(GC, 0, mmGCMC_VM_XGMI_LFB_CNTL); 459 u32 max_region = 460 REG_GET_FIELD(xgmi_lfb_cntl, GCMC_VM_XGMI_LFB_CNTL, PF_MAX_REGION); 461 u32 max_num_physical_nodes = 0; 462 u32 max_physical_node_id = 0; 463 464 switch (adev->asic_type) { 465 case CHIP_SIENNA_CICHLID: 466 max_num_physical_nodes = 4; 467 max_physical_node_id = 3; 468 break; 469 default: 470 return -EINVAL; 471 } 472 473 /* PF_MAX_REGION=0 means xgmi is disabled */ 474 if (max_region) { 475 adev->gmc.xgmi.num_physical_nodes = max_region + 1; 476 if (adev->gmc.xgmi.num_physical_nodes > max_num_physical_nodes) 477 return -EINVAL; 478 479 adev->gmc.xgmi.physical_node_id = 480 REG_GET_FIELD(xgmi_lfb_cntl, GCMC_VM_XGMI_LFB_CNTL, PF_LFB_REGION); 481 if (adev->gmc.xgmi.physical_node_id > max_physical_node_id) 482 return -EINVAL; 483 484 adev->gmc.xgmi.node_segment_size = REG_GET_FIELD( 485 RREG32_SOC15(GC, 0, mmGCMC_VM_XGMI_LFB_SIZE), 486 GCMC_VM_XGMI_LFB_SIZE, PF_LFB_SIZE) << 24; 487 } 488 489 return 0; 490 } 491