1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include "amdgpu.h" 25 #include "gfxhub_v2_1.h" 26 27 #include "gc/gc_10_3_0_offset.h" 28 #include "gc/gc_10_3_0_sh_mask.h" 29 #include "gc/gc_10_3_0_default.h" 30 #include "navi10_enum.h" 31 32 #include "soc15_common.h" 33 34 static void 35 gfxhub_v2_1_print_l2_protection_fault_status(struct amdgpu_device *adev, 36 uint32_t status) 37 { 38 dev_err(adev->dev, 39 "GCVM_L2_PROTECTION_FAULT_STATUS:0x%08X\n", 40 status); 41 dev_err(adev->dev, "\t Faulty UTCL2 client ID: 0x%lx\n", 42 REG_GET_FIELD(status, 43 GCVM_L2_PROTECTION_FAULT_STATUS, CID)); 44 dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n", 45 REG_GET_FIELD(status, 46 GCVM_L2_PROTECTION_FAULT_STATUS, MORE_FAULTS)); 47 dev_err(adev->dev, "\t WALKER_ERROR: 0x%lx\n", 48 REG_GET_FIELD(status, 49 GCVM_L2_PROTECTION_FAULT_STATUS, WALKER_ERROR)); 50 dev_err(adev->dev, "\t PERMISSION_FAULTS: 0x%lx\n", 51 REG_GET_FIELD(status, 52 GCVM_L2_PROTECTION_FAULT_STATUS, PERMISSION_FAULTS)); 53 dev_err(adev->dev, "\t MAPPING_ERROR: 0x%lx\n", 54 REG_GET_FIELD(status, 55 GCVM_L2_PROTECTION_FAULT_STATUS, MAPPING_ERROR)); 56 dev_err(adev->dev, "\t RW: 0x%lx\n", 57 REG_GET_FIELD(status, 58 GCVM_L2_PROTECTION_FAULT_STATUS, RW)); 59 } 60 61 u64 gfxhub_v2_1_get_fb_location(struct amdgpu_device *adev) 62 { 63 u64 base = RREG32_SOC15(GC, 0, mmGCMC_VM_FB_LOCATION_BASE); 64 65 base &= GCMC_VM_FB_LOCATION_BASE__FB_BASE_MASK; 66 base <<= 24; 67 68 return base; 69 } 70 71 u64 gfxhub_v2_1_get_mc_fb_offset(struct amdgpu_device *adev) 72 { 73 return (u64)RREG32_SOC15(GC, 0, mmGCMC_VM_FB_OFFSET) << 24; 74 } 75 76 void gfxhub_v2_1_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid, 77 uint64_t page_table_base) 78 { 79 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0]; 80 81 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, 82 hub->ctx_addr_distance * vmid, 83 lower_32_bits(page_table_base)); 84 85 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, 86 hub->ctx_addr_distance * vmid, 87 upper_32_bits(page_table_base)); 88 } 89 90 static void gfxhub_v2_1_init_gart_aperture_regs(struct amdgpu_device *adev) 91 { 92 uint64_t pt_base = amdgpu_gmc_pd_addr(adev->gart.bo); 93 94 gfxhub_v2_1_setup_vm_pt_regs(adev, 0, pt_base); 95 96 WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, 97 (u32)(adev->gmc.gart_start >> 12)); 98 WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, 99 (u32)(adev->gmc.gart_start >> 44)); 100 101 WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, 102 (u32)(adev->gmc.gart_end >> 12)); 103 WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, 104 (u32)(adev->gmc.gart_end >> 44)); 105 } 106 107 static void gfxhub_v2_1_init_system_aperture_regs(struct amdgpu_device *adev) 108 { 109 uint64_t value; 110 111 /* Disable AGP. */ 112 WREG32_SOC15(GC, 0, mmGCMC_VM_AGP_BASE, 0); 113 WREG32_SOC15(GC, 0, mmGCMC_VM_AGP_TOP, 0); 114 WREG32_SOC15(GC, 0, mmGCMC_VM_AGP_BOT, 0x00FFFFFF); 115 116 /* Program the system aperture low logical page number. */ 117 WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_LOW_ADDR, 118 adev->gmc.vram_start >> 18); 119 WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_HIGH_ADDR, 120 adev->gmc.vram_end >> 18); 121 122 /* Set default page address. */ 123 value = adev->vram_scratch.gpu_addr - adev->gmc.vram_start 124 + adev->vm_manager.vram_base_offset; 125 WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, 126 (u32)(value >> 12)); 127 WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, 128 (u32)(value >> 44)); 129 130 /* Program "protection fault". */ 131 WREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32, 132 (u32)(adev->dummy_page_addr >> 12)); 133 WREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32, 134 (u32)((u64)adev->dummy_page_addr >> 44)); 135 136 WREG32_FIELD15(GC, 0, GCVM_L2_PROTECTION_FAULT_CNTL2, 137 ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1); 138 } 139 140 141 static void gfxhub_v2_1_init_tlb_regs(struct amdgpu_device *adev) 142 { 143 uint32_t tmp; 144 145 /* Setup TLB control */ 146 tmp = RREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL); 147 148 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); 149 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3); 150 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, 151 ENABLE_ADVANCED_DRIVER_MODEL, 1); 152 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, 153 SYSTEM_APERTURE_UNMAPPED_ACCESS, 0); 154 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0); 155 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, 156 MTYPE, MTYPE_UC); /* UC, uncached */ 157 158 WREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL, tmp); 159 } 160 161 static void gfxhub_v2_1_init_cache_regs(struct amdgpu_device *adev) 162 { 163 uint32_t tmp; 164 165 /* Setup L2 cache */ 166 tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_CNTL); 167 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_CACHE, 1); 168 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0); 169 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, 170 ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1); 171 /* XXX for emulation, Refer to closed source code.*/ 172 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, 173 L2_PDE0_CACHE_TAG_GENERATION_MODE, 0); 174 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0); 175 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1); 176 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0); 177 WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL, tmp); 178 179 tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_CNTL2); 180 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); 181 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); 182 WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL2, tmp); 183 184 tmp = mmGCVM_L2_CNTL3_DEFAULT; 185 if (adev->gmc.translate_further) { 186 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 12); 187 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, 188 L2_CACHE_BIGK_FRAGMENT_SIZE, 9); 189 } else { 190 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 9); 191 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, 192 L2_CACHE_BIGK_FRAGMENT_SIZE, 6); 193 } 194 WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL3, tmp); 195 196 tmp = mmGCVM_L2_CNTL4_DEFAULT; 197 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0); 198 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0); 199 WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL4, tmp); 200 201 tmp = mmGCVM_L2_CNTL5_DEFAULT; 202 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL5, L2_CACHE_SMALLK_FRAGMENT_SIZE, 0); 203 WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL5, tmp); 204 } 205 206 static void gfxhub_v2_1_enable_system_domain(struct amdgpu_device *adev) 207 { 208 uint32_t tmp; 209 210 tmp = RREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_CNTL); 211 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); 212 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0); 213 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, 214 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0); 215 WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_CNTL, tmp); 216 } 217 218 static void gfxhub_v2_1_disable_identity_aperture(struct amdgpu_device *adev) 219 { 220 WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32, 221 0xFFFFFFFF); 222 WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32, 223 0x0000000F); 224 225 WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32, 226 0); 227 WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32, 228 0); 229 230 WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32, 0); 231 WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32, 0); 232 233 } 234 235 static void gfxhub_v2_1_setup_vmid_config(struct amdgpu_device *adev) 236 { 237 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0]; 238 int i; 239 uint32_t tmp; 240 241 for (i = 0; i <= 14; i++) { 242 tmp = RREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_CNTL, i); 243 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1); 244 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 245 adev->vm_manager.num_level); 246 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, 247 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 248 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, 249 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 250 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, 251 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 252 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, 253 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 254 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, 255 READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 256 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, 257 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 258 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, 259 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 260 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, 261 PAGE_TABLE_BLOCK_SIZE, 262 adev->vm_manager.block_size - 9); 263 /* Send no-retry XNACK on fault to suppress VM fault storm. */ 264 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, 265 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 266 !amdgpu_noretry); 267 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_CNTL, 268 i * hub->ctx_distance, tmp); 269 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32, 270 i * hub->ctx_addr_distance, 0); 271 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32, 272 i * hub->ctx_addr_distance, 0); 273 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32, 274 i * hub->ctx_addr_distance, 275 lower_32_bits(adev->vm_manager.max_pfn - 1)); 276 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32, 277 i * hub->ctx_addr_distance, 278 upper_32_bits(adev->vm_manager.max_pfn - 1)); 279 } 280 } 281 282 static void gfxhub_v2_1_program_invalidation(struct amdgpu_device *adev) 283 { 284 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0]; 285 unsigned i; 286 287 for (i = 0 ; i < 18; ++i) { 288 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32, 289 i * hub->eng_addr_distance, 0xffffffff); 290 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_ADDR_RANGE_HI32, 291 i * hub->eng_addr_distance, 0x1f); 292 } 293 } 294 295 int gfxhub_v2_1_gart_enable(struct amdgpu_device *adev) 296 { 297 if (amdgpu_sriov_vf(adev)) { 298 /* 299 * GCMC_VM_FB_LOCATION_BASE/TOP is NULL for VF, becuase they are 300 * VF copy registers so vbios post doesn't program them, for 301 * SRIOV driver need to program them 302 */ 303 WREG32_SOC15(GC, 0, mmGCMC_VM_FB_LOCATION_BASE, 304 adev->gmc.vram_start >> 24); 305 WREG32_SOC15(GC, 0, mmGCMC_VM_FB_LOCATION_TOP, 306 adev->gmc.vram_end >> 24); 307 } 308 309 /* GART Enable. */ 310 gfxhub_v2_1_init_gart_aperture_regs(adev); 311 gfxhub_v2_1_init_system_aperture_regs(adev); 312 gfxhub_v2_1_init_tlb_regs(adev); 313 gfxhub_v2_1_init_cache_regs(adev); 314 315 gfxhub_v2_1_enable_system_domain(adev); 316 gfxhub_v2_1_disable_identity_aperture(adev); 317 gfxhub_v2_1_setup_vmid_config(adev); 318 gfxhub_v2_1_program_invalidation(adev); 319 320 return 0; 321 } 322 323 void gfxhub_v2_1_gart_disable(struct amdgpu_device *adev) 324 { 325 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0]; 326 u32 tmp; 327 u32 i; 328 329 /* Disable all tables */ 330 for (i = 0; i < 16; i++) 331 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_CNTL, 332 i * hub->ctx_distance, 0); 333 334 /* Setup TLB control */ 335 tmp = RREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL); 336 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); 337 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, 338 ENABLE_ADVANCED_DRIVER_MODEL, 0); 339 WREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL, tmp); 340 341 /* Setup L2 cache */ 342 WREG32_FIELD15(GC, 0, GCVM_L2_CNTL, ENABLE_L2_CACHE, 0); 343 WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL3, 0); 344 } 345 346 /** 347 * gfxhub_v2_1_set_fault_enable_default - update GART/VM fault handling 348 * 349 * @adev: amdgpu_device pointer 350 * @value: true redirects VM faults to the default page 351 */ 352 void gfxhub_v2_1_set_fault_enable_default(struct amdgpu_device *adev, 353 bool value) 354 { 355 u32 tmp; 356 tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL); 357 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 358 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 359 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 360 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value); 361 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 362 PDE1_PROTECTION_FAULT_ENABLE_DEFAULT, value); 363 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 364 PDE2_PROTECTION_FAULT_ENABLE_DEFAULT, value); 365 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 366 TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT, 367 value); 368 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 369 NACK_PROTECTION_FAULT_ENABLE_DEFAULT, value); 370 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 371 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 372 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 373 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value); 374 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 375 READ_PROTECTION_FAULT_ENABLE_DEFAULT, value); 376 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 377 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 378 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 379 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 380 if (!value) { 381 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 382 CRASH_ON_NO_RETRY_FAULT, 1); 383 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 384 CRASH_ON_RETRY_FAULT, 1); 385 } 386 WREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL, tmp); 387 } 388 389 static const struct amdgpu_vmhub_funcs gfxhub_v2_1_vmhub_funcs = { 390 .print_l2_protection_fault_status = gfxhub_v2_1_print_l2_protection_fault_status, 391 }; 392 393 void gfxhub_v2_1_init(struct amdgpu_device *adev) 394 { 395 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0]; 396 397 hub->ctx0_ptb_addr_lo32 = 398 SOC15_REG_OFFSET(GC, 0, 399 mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32); 400 hub->ctx0_ptb_addr_hi32 = 401 SOC15_REG_OFFSET(GC, 0, 402 mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32); 403 hub->vm_inv_eng0_sem = 404 SOC15_REG_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_SEM); 405 hub->vm_inv_eng0_req = 406 SOC15_REG_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_REQ); 407 hub->vm_inv_eng0_ack = 408 SOC15_REG_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_ACK); 409 hub->vm_context0_cntl = 410 SOC15_REG_OFFSET(GC, 0, mmGCVM_CONTEXT0_CNTL); 411 hub->vm_l2_pro_fault_status = 412 SOC15_REG_OFFSET(GC, 0, mmGCVM_L2_PROTECTION_FAULT_STATUS); 413 hub->vm_l2_pro_fault_cntl = 414 SOC15_REG_OFFSET(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL); 415 416 hub->ctx_distance = mmGCVM_CONTEXT1_CNTL - mmGCVM_CONTEXT0_CNTL; 417 hub->ctx_addr_distance = mmGCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 - 418 mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32; 419 hub->eng_distance = mmGCVM_INVALIDATE_ENG1_REQ - 420 mmGCVM_INVALIDATE_ENG0_REQ; 421 hub->eng_addr_distance = mmGCVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 - 422 mmGCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32; 423 424 hub->vm_cntx_cntl_vm_fault = GCVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 425 GCVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 426 GCVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 427 GCVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 428 GCVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 429 GCVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 430 GCVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK; 431 432 hub->vmhub_funcs = &gfxhub_v2_1_vmhub_funcs; 433 } 434 435 int gfxhub_v2_1_get_xgmi_info(struct amdgpu_device *adev) 436 { 437 u32 xgmi_lfb_cntl = RREG32_SOC15(GC, 0, mmGCMC_VM_XGMI_LFB_CNTL); 438 u32 max_region = 439 REG_GET_FIELD(xgmi_lfb_cntl, GCMC_VM_XGMI_LFB_CNTL, PF_MAX_REGION); 440 u32 max_num_physical_nodes = 0; 441 u32 max_physical_node_id = 0; 442 443 switch (adev->asic_type) { 444 case CHIP_SIENNA_CICHLID: 445 max_num_physical_nodes = 4; 446 max_physical_node_id = 3; 447 break; 448 default: 449 return -EINVAL; 450 } 451 452 /* PF_MAX_REGION=0 means xgmi is disabled */ 453 if (max_region) { 454 adev->gmc.xgmi.num_physical_nodes = max_region + 1; 455 if (adev->gmc.xgmi.num_physical_nodes > max_num_physical_nodes) 456 return -EINVAL; 457 458 adev->gmc.xgmi.physical_node_id = 459 REG_GET_FIELD(xgmi_lfb_cntl, GCMC_VM_XGMI_LFB_CNTL, PF_LFB_REGION); 460 if (adev->gmc.xgmi.physical_node_id > max_physical_node_id) 461 return -EINVAL; 462 463 adev->gmc.xgmi.node_segment_size = REG_GET_FIELD( 464 RREG32_SOC15(GC, 0, mmGCMC_VM_XGMI_LFB_SIZE), 465 GCMC_VM_XGMI_LFB_SIZE, PF_LFB_SIZE) << 24; 466 } 467 468 return 0; 469 } 470