1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include "amdgpu.h" 25 #include "gfxhub_v2_1.h" 26 27 #include "gc/gc_10_3_0_offset.h" 28 #include "gc/gc_10_3_0_sh_mask.h" 29 #include "gc/gc_10_3_0_default.h" 30 #include "navi10_enum.h" 31 32 #include "soc15_common.h" 33 34 #define mmGCUTCL2_HARVEST_BYPASS_GROUPS_YELLOW_CARP 0x16f8 35 #define mmGCUTCL2_HARVEST_BYPASS_GROUPS_YELLOW_CARP_BASE_IDX 0 36 37 static const char *gfxhub_client_ids[] = { 38 "CB/DB", 39 "Reserved", 40 "GE1", 41 "GE2", 42 "CPF", 43 "CPC", 44 "CPG", 45 "RLC", 46 "TCP", 47 "SQC (inst)", 48 "SQC (data)", 49 "SQG", 50 "Reserved", 51 "SDMA0", 52 "SDMA1", 53 "GCR", 54 "SDMA2", 55 "SDMA3", 56 }; 57 58 static uint32_t gfxhub_v2_1_get_invalidate_req(unsigned int vmid, 59 uint32_t flush_type) 60 { 61 u32 req = 0; 62 63 /* invalidate using legacy mode on vmid*/ 64 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, 65 PER_VMID_INVALIDATE_REQ, 1 << vmid); 66 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type); 67 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1); 68 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1); 69 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1); 70 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1); 71 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1); 72 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, 73 CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0); 74 75 return req; 76 } 77 78 static void 79 gfxhub_v2_1_print_l2_protection_fault_status(struct amdgpu_device *adev, 80 uint32_t status) 81 { 82 u32 cid = REG_GET_FIELD(status, 83 GCVM_L2_PROTECTION_FAULT_STATUS, CID); 84 85 dev_err(adev->dev, 86 "GCVM_L2_PROTECTION_FAULT_STATUS:0x%08X\n", 87 status); 88 dev_err(adev->dev, "\t Faulty UTCL2 client ID: %s (0x%x)\n", 89 cid >= ARRAY_SIZE(gfxhub_client_ids) ? "unknown" : gfxhub_client_ids[cid], 90 cid); 91 dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n", 92 REG_GET_FIELD(status, 93 GCVM_L2_PROTECTION_FAULT_STATUS, MORE_FAULTS)); 94 dev_err(adev->dev, "\t WALKER_ERROR: 0x%lx\n", 95 REG_GET_FIELD(status, 96 GCVM_L2_PROTECTION_FAULT_STATUS, WALKER_ERROR)); 97 dev_err(adev->dev, "\t PERMISSION_FAULTS: 0x%lx\n", 98 REG_GET_FIELD(status, 99 GCVM_L2_PROTECTION_FAULT_STATUS, PERMISSION_FAULTS)); 100 dev_err(adev->dev, "\t MAPPING_ERROR: 0x%lx\n", 101 REG_GET_FIELD(status, 102 GCVM_L2_PROTECTION_FAULT_STATUS, MAPPING_ERROR)); 103 dev_err(adev->dev, "\t RW: 0x%lx\n", 104 REG_GET_FIELD(status, 105 GCVM_L2_PROTECTION_FAULT_STATUS, RW)); 106 } 107 108 static u64 gfxhub_v2_1_get_fb_location(struct amdgpu_device *adev) 109 { 110 u64 base = RREG32_SOC15(GC, 0, mmGCMC_VM_FB_LOCATION_BASE); 111 112 base &= GCMC_VM_FB_LOCATION_BASE__FB_BASE_MASK; 113 base <<= 24; 114 115 return base; 116 } 117 118 static u64 gfxhub_v2_1_get_mc_fb_offset(struct amdgpu_device *adev) 119 { 120 return (u64)RREG32_SOC15(GC, 0, mmGCMC_VM_FB_OFFSET) << 24; 121 } 122 123 static void gfxhub_v2_1_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid, 124 uint64_t page_table_base) 125 { 126 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0]; 127 128 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, 129 hub->ctx_addr_distance * vmid, 130 lower_32_bits(page_table_base)); 131 132 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, 133 hub->ctx_addr_distance * vmid, 134 upper_32_bits(page_table_base)); 135 } 136 137 static void gfxhub_v2_1_init_gart_aperture_regs(struct amdgpu_device *adev) 138 { 139 uint64_t pt_base = amdgpu_gmc_pd_addr(adev->gart.bo); 140 141 gfxhub_v2_1_setup_vm_pt_regs(adev, 0, pt_base); 142 143 WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, 144 (u32)(adev->gmc.gart_start >> 12)); 145 WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, 146 (u32)(adev->gmc.gart_start >> 44)); 147 148 WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, 149 (u32)(adev->gmc.gart_end >> 12)); 150 WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, 151 (u32)(adev->gmc.gart_end >> 44)); 152 } 153 154 static void gfxhub_v2_1_init_system_aperture_regs(struct amdgpu_device *adev) 155 { 156 uint64_t value; 157 158 /* Program the AGP BAR */ 159 WREG32_SOC15(GC, 0, mmGCMC_VM_AGP_BASE, 0); 160 WREG32_SOC15(GC, 0, mmGCMC_VM_AGP_BOT, adev->gmc.agp_start >> 24); 161 WREG32_SOC15(GC, 0, mmGCMC_VM_AGP_TOP, adev->gmc.agp_end >> 24); 162 163 /* Program the system aperture low logical page number. */ 164 WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_LOW_ADDR, 165 min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18); 166 WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_HIGH_ADDR, 167 max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18); 168 169 /* Set default page address. */ 170 value = amdgpu_gmc_vram_mc2pa(adev, adev->vram_scratch.gpu_addr); 171 WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, 172 (u32)(value >> 12)); 173 WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, 174 (u32)(value >> 44)); 175 176 /* Program "protection fault". */ 177 WREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32, 178 (u32)(adev->dummy_page_addr >> 12)); 179 WREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32, 180 (u32)((u64)adev->dummy_page_addr >> 44)); 181 182 WREG32_FIELD15(GC, 0, GCVM_L2_PROTECTION_FAULT_CNTL2, 183 ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1); 184 } 185 186 187 static void gfxhub_v2_1_init_tlb_regs(struct amdgpu_device *adev) 188 { 189 uint32_t tmp; 190 191 /* Setup TLB control */ 192 tmp = RREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL); 193 194 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); 195 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3); 196 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, 197 ENABLE_ADVANCED_DRIVER_MODEL, 1); 198 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, 199 SYSTEM_APERTURE_UNMAPPED_ACCESS, 0); 200 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0); 201 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, 202 MTYPE, MTYPE_UC); /* UC, uncached */ 203 204 WREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL, tmp); 205 } 206 207 static void gfxhub_v2_1_init_cache_regs(struct amdgpu_device *adev) 208 { 209 uint32_t tmp; 210 211 /* These registers are not accessible to VF-SRIOV. 212 * The PF will program them instead. 213 */ 214 if (amdgpu_sriov_vf(adev)) 215 return; 216 217 /* Setup L2 cache */ 218 tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_CNTL); 219 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_CACHE, 1); 220 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0); 221 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, 222 ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1); 223 /* XXX for emulation, Refer to closed source code.*/ 224 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, 225 L2_PDE0_CACHE_TAG_GENERATION_MODE, 0); 226 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0); 227 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1); 228 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0); 229 WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL, tmp); 230 231 tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_CNTL2); 232 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); 233 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); 234 WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL2, tmp); 235 236 tmp = mmGCVM_L2_CNTL3_DEFAULT; 237 if (adev->gmc.translate_further) { 238 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 12); 239 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, 240 L2_CACHE_BIGK_FRAGMENT_SIZE, 9); 241 } else { 242 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 9); 243 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, 244 L2_CACHE_BIGK_FRAGMENT_SIZE, 6); 245 } 246 WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL3, tmp); 247 248 tmp = mmGCVM_L2_CNTL4_DEFAULT; 249 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0); 250 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0); 251 WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL4, tmp); 252 253 tmp = mmGCVM_L2_CNTL5_DEFAULT; 254 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL5, L2_CACHE_SMALLK_FRAGMENT_SIZE, 0); 255 WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL5, tmp); 256 } 257 258 static void gfxhub_v2_1_enable_system_domain(struct amdgpu_device *adev) 259 { 260 uint32_t tmp; 261 262 tmp = RREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_CNTL); 263 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); 264 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0); 265 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, 266 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0); 267 WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_CNTL, tmp); 268 } 269 270 static void gfxhub_v2_1_disable_identity_aperture(struct amdgpu_device *adev) 271 { 272 /* These registers are not accessible to VF-SRIOV. 273 * The PF will program them instead. 274 */ 275 if (amdgpu_sriov_vf(adev)) 276 return; 277 278 WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32, 279 0xFFFFFFFF); 280 WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32, 281 0x0000000F); 282 283 WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32, 284 0); 285 WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32, 286 0); 287 288 WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32, 0); 289 WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32, 0); 290 291 } 292 293 static void gfxhub_v2_1_setup_vmid_config(struct amdgpu_device *adev) 294 { 295 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0]; 296 int i; 297 uint32_t tmp; 298 299 for (i = 0; i <= 14; i++) { 300 tmp = RREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_CNTL, i); 301 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1); 302 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 303 adev->vm_manager.num_level); 304 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, 305 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 306 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, 307 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 308 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, 309 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 310 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, 311 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 312 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, 313 READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 314 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, 315 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 316 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, 317 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 318 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, 319 PAGE_TABLE_BLOCK_SIZE, 320 adev->vm_manager.block_size - 9); 321 /* Send no-retry XNACK on fault to suppress VM fault storm. */ 322 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, 323 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 324 !adev->gmc.noretry); 325 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_CNTL, 326 i * hub->ctx_distance, tmp); 327 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32, 328 i * hub->ctx_addr_distance, 0); 329 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32, 330 i * hub->ctx_addr_distance, 0); 331 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32, 332 i * hub->ctx_addr_distance, 333 lower_32_bits(adev->vm_manager.max_pfn - 1)); 334 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32, 335 i * hub->ctx_addr_distance, 336 upper_32_bits(adev->vm_manager.max_pfn - 1)); 337 } 338 } 339 340 static void gfxhub_v2_1_program_invalidation(struct amdgpu_device *adev) 341 { 342 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0]; 343 unsigned i; 344 345 for (i = 0 ; i < 18; ++i) { 346 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32, 347 i * hub->eng_addr_distance, 0xffffffff); 348 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_ADDR_RANGE_HI32, 349 i * hub->eng_addr_distance, 0x1f); 350 } 351 } 352 353 static int gfxhub_v2_1_gart_enable(struct amdgpu_device *adev) 354 { 355 if (amdgpu_sriov_vf(adev)) { 356 /* 357 * GCMC_VM_FB_LOCATION_BASE/TOP is NULL for VF, becuase they are 358 * VF copy registers so vbios post doesn't program them, for 359 * SRIOV driver need to program them 360 */ 361 WREG32_SOC15(GC, 0, mmGCMC_VM_FB_LOCATION_BASE, 362 adev->gmc.vram_start >> 24); 363 WREG32_SOC15(GC, 0, mmGCMC_VM_FB_LOCATION_TOP, 364 adev->gmc.vram_end >> 24); 365 } 366 367 /* GART Enable. */ 368 gfxhub_v2_1_init_gart_aperture_regs(adev); 369 gfxhub_v2_1_init_system_aperture_regs(adev); 370 gfxhub_v2_1_init_tlb_regs(adev); 371 gfxhub_v2_1_init_cache_regs(adev); 372 373 gfxhub_v2_1_enable_system_domain(adev); 374 gfxhub_v2_1_disable_identity_aperture(adev); 375 gfxhub_v2_1_setup_vmid_config(adev); 376 gfxhub_v2_1_program_invalidation(adev); 377 378 return 0; 379 } 380 381 static void gfxhub_v2_1_gart_disable(struct amdgpu_device *adev) 382 { 383 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0]; 384 u32 tmp; 385 u32 i; 386 387 /* Disable all tables */ 388 for (i = 0; i < 16; i++) 389 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_CNTL, 390 i * hub->ctx_distance, 0); 391 392 /* Setup TLB control */ 393 tmp = RREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL); 394 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); 395 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, 396 ENABLE_ADVANCED_DRIVER_MODEL, 0); 397 WREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL, tmp); 398 399 /* Setup L2 cache */ 400 WREG32_FIELD15(GC, 0, GCVM_L2_CNTL, ENABLE_L2_CACHE, 0); 401 WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL3, 0); 402 } 403 404 /** 405 * gfxhub_v2_1_set_fault_enable_default - update GART/VM fault handling 406 * 407 * @adev: amdgpu_device pointer 408 * @value: true redirects VM faults to the default page 409 */ 410 static void gfxhub_v2_1_set_fault_enable_default(struct amdgpu_device *adev, 411 bool value) 412 { 413 u32 tmp; 414 415 /* These registers are not accessible to VF-SRIOV. 416 * The PF will program them instead. 417 */ 418 if (amdgpu_sriov_vf(adev)) 419 return; 420 421 tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL); 422 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 423 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 424 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 425 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value); 426 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 427 PDE1_PROTECTION_FAULT_ENABLE_DEFAULT, value); 428 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 429 PDE2_PROTECTION_FAULT_ENABLE_DEFAULT, value); 430 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 431 TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT, 432 value); 433 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 434 NACK_PROTECTION_FAULT_ENABLE_DEFAULT, value); 435 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 436 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 437 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 438 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value); 439 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 440 READ_PROTECTION_FAULT_ENABLE_DEFAULT, value); 441 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 442 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 443 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 444 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 445 if (!value) { 446 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 447 CRASH_ON_NO_RETRY_FAULT, 1); 448 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 449 CRASH_ON_RETRY_FAULT, 1); 450 } 451 WREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL, tmp); 452 } 453 454 static const struct amdgpu_vmhub_funcs gfxhub_v2_1_vmhub_funcs = { 455 .print_l2_protection_fault_status = gfxhub_v2_1_print_l2_protection_fault_status, 456 .get_invalidate_req = gfxhub_v2_1_get_invalidate_req, 457 }; 458 459 static void gfxhub_v2_1_init(struct amdgpu_device *adev) 460 { 461 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0]; 462 463 hub->ctx0_ptb_addr_lo32 = 464 SOC15_REG_OFFSET(GC, 0, 465 mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32); 466 hub->ctx0_ptb_addr_hi32 = 467 SOC15_REG_OFFSET(GC, 0, 468 mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32); 469 hub->vm_inv_eng0_sem = 470 SOC15_REG_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_SEM); 471 hub->vm_inv_eng0_req = 472 SOC15_REG_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_REQ); 473 hub->vm_inv_eng0_ack = 474 SOC15_REG_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_ACK); 475 hub->vm_context0_cntl = 476 SOC15_REG_OFFSET(GC, 0, mmGCVM_CONTEXT0_CNTL); 477 hub->vm_l2_pro_fault_status = 478 SOC15_REG_OFFSET(GC, 0, mmGCVM_L2_PROTECTION_FAULT_STATUS); 479 hub->vm_l2_pro_fault_cntl = 480 SOC15_REG_OFFSET(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL); 481 482 hub->ctx_distance = mmGCVM_CONTEXT1_CNTL - mmGCVM_CONTEXT0_CNTL; 483 hub->ctx_addr_distance = mmGCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 - 484 mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32; 485 hub->eng_distance = mmGCVM_INVALIDATE_ENG1_REQ - 486 mmGCVM_INVALIDATE_ENG0_REQ; 487 hub->eng_addr_distance = mmGCVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 - 488 mmGCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32; 489 490 hub->vm_cntx_cntl_vm_fault = GCVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 491 GCVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 492 GCVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 493 GCVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 494 GCVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 495 GCVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 496 GCVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK; 497 498 hub->vmhub_funcs = &gfxhub_v2_1_vmhub_funcs; 499 } 500 501 static int gfxhub_v2_1_get_xgmi_info(struct amdgpu_device *adev) 502 { 503 u32 xgmi_lfb_cntl = RREG32_SOC15(GC, 0, mmGCMC_VM_XGMI_LFB_CNTL); 504 u32 max_region = 505 REG_GET_FIELD(xgmi_lfb_cntl, GCMC_VM_XGMI_LFB_CNTL, PF_MAX_REGION); 506 u32 max_num_physical_nodes = 0; 507 u32 max_physical_node_id = 0; 508 509 switch (adev->ip_versions[XGMI_HWIP]) { 510 case IP_VERSION(4, 8, 0): 511 max_num_physical_nodes = 4; 512 max_physical_node_id = 3; 513 break; 514 default: 515 return -EINVAL; 516 } 517 518 /* PF_MAX_REGION=0 means xgmi is disabled */ 519 if (max_region) { 520 adev->gmc.xgmi.num_physical_nodes = max_region + 1; 521 if (adev->gmc.xgmi.num_physical_nodes > max_num_physical_nodes) 522 return -EINVAL; 523 524 adev->gmc.xgmi.physical_node_id = 525 REG_GET_FIELD(xgmi_lfb_cntl, GCMC_VM_XGMI_LFB_CNTL, PF_LFB_REGION); 526 if (adev->gmc.xgmi.physical_node_id > max_physical_node_id) 527 return -EINVAL; 528 529 adev->gmc.xgmi.node_segment_size = REG_GET_FIELD( 530 RREG32_SOC15(GC, 0, mmGCMC_VM_XGMI_LFB_SIZE), 531 GCMC_VM_XGMI_LFB_SIZE, PF_LFB_SIZE) << 24; 532 } 533 534 return 0; 535 } 536 537 static void gfxhub_v2_1_utcl2_harvest(struct amdgpu_device *adev) 538 { 539 int i; 540 u32 tmp = 0, disabled_sa = 0; 541 u32 efuse_setting, vbios_setting; 542 543 u32 max_sa_mask = amdgpu_gfx_create_bitmask( 544 adev->gfx.config.max_sh_per_se * 545 adev->gfx.config.max_shader_engines); 546 547 if (adev->ip_versions[GC_HWIP] == IP_VERSION(10, 3, 3)) { 548 /* Get SA disabled bitmap from eFuse setting */ 549 efuse_setting = RREG32_SOC15(GC, 0, mmCC_GC_SA_UNIT_DISABLE); 550 efuse_setting &= CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK; 551 efuse_setting >>= CC_GC_SA_UNIT_DISABLE__SA_DISABLE__SHIFT; 552 553 /* Get SA disabled bitmap from VBIOS setting */ 554 vbios_setting = RREG32_SOC15(GC, 0, mmGC_USER_SA_UNIT_DISABLE); 555 vbios_setting &= GC_USER_SA_UNIT_DISABLE__SA_DISABLE_MASK; 556 vbios_setting >>= GC_USER_SA_UNIT_DISABLE__SA_DISABLE__SHIFT; 557 558 disabled_sa |= efuse_setting | vbios_setting; 559 /* Make sure not to report harvested SAs beyond the max SA count */ 560 disabled_sa &= max_sa_mask; 561 562 for (i = 0; disabled_sa > 0; i++) { 563 if (disabled_sa & 1) 564 tmp |= 0x3 << (i * 2); 565 disabled_sa >>= 1; 566 } 567 disabled_sa = tmp; 568 569 WREG32_SOC15(GC, 0, mmGCUTCL2_HARVEST_BYPASS_GROUPS_YELLOW_CARP, disabled_sa); 570 } 571 } 572 573 const struct amdgpu_gfxhub_funcs gfxhub_v2_1_funcs = { 574 .get_fb_location = gfxhub_v2_1_get_fb_location, 575 .get_mc_fb_offset = gfxhub_v2_1_get_mc_fb_offset, 576 .setup_vm_pt_regs = gfxhub_v2_1_setup_vm_pt_regs, 577 .gart_enable = gfxhub_v2_1_gart_enable, 578 .gart_disable = gfxhub_v2_1_gart_disable, 579 .set_fault_enable_default = gfxhub_v2_1_set_fault_enable_default, 580 .init = gfxhub_v2_1_init, 581 .get_xgmi_info = gfxhub_v2_1_get_xgmi_info, 582 .utcl2_harvest = gfxhub_v2_1_utcl2_harvest, 583 }; 584