arm64: dts: marvell: Prepare the introduction of CP115

CP110 and CP115 are almost the same in terms of features and have a
very limited set of differences. Let's create an armada-cp11x.dtsi
file whi

arm64: dts: marvell: Prepare the introduction of CP115

CP110 and CP115 are almost the same in terms of features and have a
very limited set of differences. Let's create an armada-cp11x.dtsi
file which will be used to instantiate both CP110 and CP115
nodes.

The only changes between the two armada-cp11{0,x}.dtsi files are the
following naming in macros: s/CP110/CP11X/.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>

show more ...

arm64: dts: marvell: Fix CP110 NAND controller node multi-line comment alignment

Fix this tiny typo before renaming/changing this file.

Fixes: 72a3713fadfd ("arm64: dts: marvell: de-duplicate CP110

arm64: dts: marvell: Fix CP110 NAND controller node multi-line comment alignment

Fix this tiny typo before renaming/changing this file.

Fixes: 72a3713fadfd ("arm64: dts: marvell: de-duplicate CP110 description")
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>

show more ...

arm64: dts: marvell: Add 7k/8k per-port PHYs in SATA nodes

Fill-in the missing SATA phys/phy-names DT properties of Armada 7k/8k
based boards.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.co

arm64: dts: marvell: Add 7k/8k per-port PHYs in SATA nodes

Fill-in the missing SATA phys/phy-names DT properties of Armada 7k/8k
based boards.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>

show more ...

arm64: dts: marvell: Add CP110 COMPHY clocks

Declare the three clocks feeding the COMPHY block.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: Gregory CLEMENT <gregory.clem

arm64: dts: marvell: Add CP110 COMPHY clocks

Declare the three clocks feeding the COMPHY block.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>

show more ...

arm64: dts: marvell: add missing #interrupt-cells property

The GPIO interrupt controllers are missing their required
specified in DT.

Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
Review

arm64: dts: marvell: add missing #interrupt-cells property

The GPIO interrupt controllers are missing their required
specified in DT.

Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>

show more ...

arm64: dts: marvell: add interrupt support to cp110 thermal node

Add interrupt properties in the thermal node as well as a critical trip
point in the thermal-zone.

Signed-off-by: Miquel Raynal <miq

arm64: dts: marvell: add interrupt support to cp110 thermal node

Add interrupt properties in the thermal node as well as a critical trip
point in the thermal-zone.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Acked-by: Eduardo Valentin <edubezval@gmail.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>

show more ...

arm64: dts: marvell: add CP110 ICU SEI subnode

The ICU handles several interrupt groups, each of them being a subpart
of the ICU node.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Signe

arm64: dts: marvell: add CP110 ICU SEI subnode

The ICU handles several interrupt groups, each of them being a subpart
of the ICU node.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>

show more ...

arm64: dts: marvell: use new bindings for CP110 interrupts

Create an ICU subnode for the NSR interrupts. This subnode becomes the
CP110 interrupt parent, removing the need for the ICU_GRP_NSR parame

arm64: dts: marvell: use new bindings for CP110 interrupts

Create an ICU subnode for the NSR interrupts. This subnode becomes the
CP110 interrupt parent, removing the need for the ICU_GRP_NSR parameter.
Move all DT110 nodes to use these new bindings.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>

show more ...

arm64: dts: marvell: armada-cp110: describe more PPv2 interrupts

This patch describes 3 additional interrupts per PPv2 port. Those
interrupts will be used later in future versions of the Marvell PPv

arm64: dts: marvell: armada-cp110: describe more PPv2 interrupts

This patch describes 3 additional interrupts per PPv2 port. Those
interrupts will be used later in future versions of the Marvell PPv2
driver, and now the device tree description matches the hardware
capabilities.

Signed-off-by: Antoine Tenart <antoine.tenart@bootlin.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>

show more ...

arm64: dts: marvell: armada-cp110: change the PPv2 IRQ names

This patch changes the PPv2 IRQ names in the CP110 device tree to match
a corresponding change in the Marvell PPv2 driver. The reason thi

arm64: dts: marvell: armada-cp110: change the PPv2 IRQ names

This patch changes the PPv2 IRQ names in the CP110 device tree to match
a corresponding change in the Marvell PPv2 driver. The reason this was
updated is the IRQ where names after Tx/Rx interrupts, but this is not
true and can be configured. A following patch will add more of them and
the names wouldn't make sense.

Signed-off-by: Antoine Tenart <antoine.tenart@bootlin.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>

show more ...

arm64: dts: marvell: add thermal-zone node in cp110 DTSI file

Add a thermal-zone node and fill in all the sensors available in a
cp110 (only one in the thermal IP).

Signed-off-by: Miquel Raynal <mi

arm64: dts: marvell: add thermal-zone node in cp110 DTSI file

Add a thermal-zone node and fill in all the sensors available in a
cp110 (only one in the thermal IP).

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>

show more ...

arm64: dts: marvell: move AP806/CP110 thermal nodes into a new syscon

New bindings impose to declare the thermal IP from within a new syscon.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com

arm64: dts: marvell: move AP806/CP110 thermal nodes into a new syscon

New bindings impose to declare the thermal IP from within a new syscon.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>

show more ...

arm64: dts: marvell: armada-cp110: update the crypto engine compatible

New compatibles are now supported by the Inside Secure SafeXcel driver.
As they are more specific than the old ones, they shoul

arm64: dts: marvell: armada-cp110: update the crypto engine compatible

New compatibles are now supported by the Inside Secure SafeXcel driver.
As they are more specific than the old ones, they should be used
whenever possible. This patch updates the Marvell cp110 device tree
accordingly.

Signed-off-by: Antoine Tenart <antoine.tenart@bootlin.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>

show more ...

arm64: dts: marvell: fix CP110 ICU node size

ICU size in CP110 is not 0x10 but at least 0x440 bytes long (from the
specification).

Fixes: 6ef84a827c37 ("arm64: dts: marvell: enable GICP and ICU on

arm64: dts: marvell: fix CP110 ICU node size

ICU size in CP110 is not 0x10 but at least 0x440 bytes long (from the
specification).

Fixes: 6ef84a827c37 ("arm64: dts: marvell: enable GICP and ICU on Armada 7K/8K")
Cc: stable@vger.kernel.org
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>

show more ...

ARM64: dts: marvell: armada-cp110: Add mg_core_clk for ethernet node

Marvell PPv2.2 controller present on CP-110 need the extra "mg_core_clk"
clock to avoid system hangs when powering some network i

ARM64: dts: marvell: armada-cp110: Add mg_core_clk for ethernet node

Marvell PPv2.2 controller present on CP-110 need the extra "mg_core_clk"
clock to avoid system hangs when powering some network interfaces up.

This issue appeared after a recent clock rework on Armada 7K/8K platforms.

This commit adds the new clock and updates the documentation accordingly.

[gregory.clement: use the real first commit to fix and add the cc:stable
flag]
Fixes: e3af9f7c6ece ("RM64: dts: marvell: armada-cp110: Fix clock resources for various node")
Cc: <stable@vger.kernel.org>
Signed-off-by: Maxime Chevallier <maxime.chevallier@bootlin.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>

show more ...

ARM64: dts: marvell: armada-cp110: Add clocks for the xmdio node

The Marvell XSMI controller needs 3 clocks to operate correctly :
- The MG clock (clk 5)
- The MG Core clock (clk 6)
- The GOP clo

ARM64: dts: marvell: armada-cp110: Add clocks for the xmdio node

The Marvell XSMI controller needs 3 clocks to operate correctly :
- The MG clock (clk 5)
- The MG Core clock (clk 6)
- The GOP clock (clk 18)

This commit adds them, to avoid system hangs when using these
interfaces.

[gregory.clement: use the real first commit to fix and add the cc:stable
flag]
Fixes: f66b2aff46ea ("arm64: dts: marvell: add xmdio nodes for 7k/8k")
Cc: <stable@vger.kernel.org>
Signed-off-by: Maxime Chevallier <maxime.chevallier@bootlin.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>

show more ...

arm64: dts: marvell: mark CP110 ahci as dma-coherent

The hardware is clearly DMA coherent and not marking it as such leads
to cache coherency problems, at least with the OpenBSD kernel.

Signed-off-

arm64: dts: marvell: mark CP110 ahci as dma-coherent

The hardware is clearly DMA coherent and not marking it as such leads
to cache coherency problems, at least with the OpenBSD kernel.

Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>

show more ...

ARM64: dts: marvell: armada-cp110: Add registers clock for the PCIe nodes

This extra clock is needed to access the registers of the PCIe host
controller used on CP110 component of the Armada 7K/8K S

ARM64: dts: marvell: armada-cp110: Add registers clock for the PCIe nodes

This extra clock is needed to access the registers of the PCIe host
controller used on CP110 component of the Armada 7K/8K SoCs.

This follow the changes already made in the binding documentation (as
well as in the driver): "PCI: armada8k: Fix clock resource by adding
a register clock"

Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>

show more ...

ARM64: dts: marvell: armada-cp110: Add registers clock for the NAND node

This extra clock is needed to access the registers of the NAND controller
used on CP110 component of the Armada 7K/8K SoCs.

ARM64: dts: marvell: armada-cp110: Add registers clock for the NAND node

This extra clock is needed to access the registers of the NAND controller
used on CP110 component of the Armada 7K/8K SoCs.

This follow the changes already made in the binding documentation (as
well as in the driver): "mtd: nand: marvell: Fix clock resource by adding
a register clock"

Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>

show more ...

ARM64: dts: marvell: armada-cp110: Add registers clock for the crypto node

This extra clock is needed to access the registers of the safexcel EIP97
used on CP110 component of the Armada 7K/8K SoCs.

ARM64: dts: marvell: armada-cp110: Add registers clock for the crypto node

This extra clock is needed to access the registers of the safexcel EIP97
used on CP110 component of the Armada 7K/8K SoCs.

This follow the changes already made in the binding documentation (as
well as in the driver): "crypto: inside-secure - fix clock resource by
adding a register clock"

Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>

show more ...

ARM64: dts: marvell: armada-cp110: Add registers clock for the trng node

This extra clock is needed to access the registers of the harware RNG
used on CP110 component of the Armada 7K/8K SoCs.

This

ARM64: dts: marvell: armada-cp110: Add registers clock for the trng node

This extra clock is needed to access the registers of the harware RNG
used on CP110 component of the Armada 7K/8K SoCs.

This follow the changes already made in the binding documentation (as
well as in the driver): "hwrng: omap - Fix clock resource by adding a
register clock"

Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>

show more ...

ARM64: dts: marvell: armada-cp110: Add registers clock for XOR engine nodes

This extra clock is needed to access the registers of the XOR engine
controller used on CP110 component of the Armada 7K/8

ARM64: dts: marvell: armada-cp110: Add registers clock for XOR engine nodes

This extra clock is needed to access the registers of the XOR engine
controller used on CP110 component of the Armada 7K/8K SoCs.

This follow the changes already made in the binding documentation (as
well as in the driver): "dmaengine: mv_xor_v2: Fix clock resource by
adding a register clock"

Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>

show more ...

ARM64: dts: marvell: armada-cp110: Add registers clock for USB host nodes

This extra clock is needed to access the registers of the USB host
controller used on Armada 7K/8K SoCs.

This follow the ch

ARM64: dts: marvell: armada-cp110: Add registers clock for USB host nodes

This extra clock is needed to access the registers of the USB host
controller used on Armada 7K/8K SoCs.

This follow the changes already made in the binding documentation (as
well as in the driver): "usb: host: xhci-plat: Fix clock resource by
adding a register clock"

Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>

show more ...

ARM64: dts: marvell: armada-cp110: Add apb_pclk clock for the uart nodes

This extra clock is needed to access the registers of the UARTs used on
CP110 component of the Armada 7K/8K SoCs.

Signed-off

ARM64: dts: marvell: armada-cp110: Add apb_pclk clock for the uart nodes

This extra clock is needed to access the registers of the UARTs used on
CP110 component of the Armada 7K/8K SoCs.

Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>

show more ...

arm64: dts: marvell: use reworked NAND controller driver on Armada 7K

Use the new bindings of the reworked Marvell NAND controller driver.
Also adapt the nand controller node organization to disting

arm64: dts: marvell: use reworked NAND controller driver on Armada 7K

Use the new bindings of the reworked Marvell NAND controller driver.
Also adapt the nand controller node organization to distinguish which
property is relevant for the controller, and which one is NAND chip
specific. Expose the partitions as a subnode of the NAND chip.

Remove the 'marvell,nand-enable-arbiter' property, not needed anymore as
the driver activates the arbiter by default for all boards (either
needed or harmless).

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>

show more ...