1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (C) 2016 Marvell Technology Group Ltd. 4 * 5 * Device Tree file for Marvell Armada CP110. 6 */ 7 8#include <dt-bindings/interrupt-controller/mvebu-icu.h> 9#include <dt-bindings/thermal/thermal.h> 10 11#include "armada-common.dtsi" 12 13#define CP110_PCIEx_IO_BASE(iface) (CP110_PCIE_IO_BASE + (iface * 0x10000)) 14#define CP110_PCIEx_MEM_BASE(iface) (CP110_PCIE_MEM_BASE + (iface * 0x1000000)) 15#define CP110_PCIEx_CONF_BASE(iface) (CP110_PCIEx_MEM_BASE(iface) + 0xf00000) 16 17/ { 18 /* 19 * The contents of the node are defined below, in order to 20 * save one indentation level 21 */ 22 CP110_NAME: CP110_NAME { }; 23 24 /* 25 * CPs only have one sensor in the thermal IC. 26 * 27 * The cooling maps are empty as there are no cooling devices. 28 */ 29 thermal-zones { 30 CP110_LABEL(thermal_ic): CP110_NODE_NAME(thermal-ic) { 31 polling-delay-passive = <1000>; 32 polling-delay = <1000>; 33 34 thermal-sensors = <&CP110_LABEL(thermal) 0>; 35 36 trips { }; 37 cooling-maps { }; 38 }; 39 }; 40}; 41 42&CP110_NAME { 43 #address-cells = <2>; 44 #size-cells = <2>; 45 compatible = "simple-bus"; 46 interrupt-parent = <&CP110_LABEL(icu)>; 47 ranges; 48 49 config-space@CP110_BASE { 50 #address-cells = <1>; 51 #size-cells = <1>; 52 compatible = "simple-bus"; 53 ranges = <0x0 0x0 ADDRESSIFY(CP110_BASE) 0x2000000>; 54 55 CP110_LABEL(ethernet): ethernet@0 { 56 compatible = "marvell,armada-7k-pp22"; 57 reg = <0x0 0x100000>, <0x129000 0xb000>; 58 clocks = <&CP110_LABEL(clk) 1 3>, <&CP110_LABEL(clk) 1 9>, 59 <&CP110_LABEL(clk) 1 5>, <&CP110_LABEL(clk) 1 6>, 60 <&CP110_LABEL(clk) 1 18>; 61 clock-names = "pp_clk", "gop_clk", 62 "mg_clk", "mg_core_clk", "axi_clk"; 63 marvell,system-controller = <&CP110_LABEL(syscon0)>; 64 status = "disabled"; 65 dma-coherent; 66 67 CP110_LABEL(eth0): eth0 { 68 interrupts = <ICU_GRP_NSR 39 IRQ_TYPE_LEVEL_HIGH>, 69 <ICU_GRP_NSR 43 IRQ_TYPE_LEVEL_HIGH>, 70 <ICU_GRP_NSR 47 IRQ_TYPE_LEVEL_HIGH>, 71 <ICU_GRP_NSR 51 IRQ_TYPE_LEVEL_HIGH>, 72 <ICU_GRP_NSR 55 IRQ_TYPE_LEVEL_HIGH>, 73 <ICU_GRP_NSR 129 IRQ_TYPE_LEVEL_HIGH>; 74 interrupt-names = "hif0", "hif1", "hif2", 75 "hif3", "hif4", "link"; 76 port-id = <0>; 77 gop-port-id = <0>; 78 status = "disabled"; 79 }; 80 81 CP110_LABEL(eth1): eth1 { 82 interrupts = <ICU_GRP_NSR 40 IRQ_TYPE_LEVEL_HIGH>, 83 <ICU_GRP_NSR 44 IRQ_TYPE_LEVEL_HIGH>, 84 <ICU_GRP_NSR 48 IRQ_TYPE_LEVEL_HIGH>, 85 <ICU_GRP_NSR 52 IRQ_TYPE_LEVEL_HIGH>, 86 <ICU_GRP_NSR 56 IRQ_TYPE_LEVEL_HIGH>, 87 <ICU_GRP_NSR 128 IRQ_TYPE_LEVEL_HIGH>; 88 interrupt-names = "hif0", "hif1", "hif2", 89 "hif3", "hif4", "link"; 90 port-id = <1>; 91 gop-port-id = <2>; 92 status = "disabled"; 93 }; 94 95 CP110_LABEL(eth2): eth2 { 96 interrupts = <ICU_GRP_NSR 41 IRQ_TYPE_LEVEL_HIGH>, 97 <ICU_GRP_NSR 45 IRQ_TYPE_LEVEL_HIGH>, 98 <ICU_GRP_NSR 49 IRQ_TYPE_LEVEL_HIGH>, 99 <ICU_GRP_NSR 53 IRQ_TYPE_LEVEL_HIGH>, 100 <ICU_GRP_NSR 57 IRQ_TYPE_LEVEL_HIGH>, 101 <ICU_GRP_NSR 127 IRQ_TYPE_LEVEL_HIGH>; 102 interrupt-names = "hif0", "hif1", "hif2", 103 "hif3", "hif4", "link"; 104 port-id = <2>; 105 gop-port-id = <3>; 106 status = "disabled"; 107 }; 108 }; 109 110 CP110_LABEL(comphy): phy@120000 { 111 compatible = "marvell,comphy-cp110"; 112 reg = <0x120000 0x6000>; 113 marvell,system-controller = <&CP110_LABEL(syscon0)>; 114 #address-cells = <1>; 115 #size-cells = <0>; 116 117 CP110_LABEL(comphy0): phy@0 { 118 reg = <0>; 119 #phy-cells = <1>; 120 }; 121 122 CP110_LABEL(comphy1): phy@1 { 123 reg = <1>; 124 #phy-cells = <1>; 125 }; 126 127 CP110_LABEL(comphy2): phy@2 { 128 reg = <2>; 129 #phy-cells = <1>; 130 }; 131 132 CP110_LABEL(comphy3): phy@3 { 133 reg = <3>; 134 #phy-cells = <1>; 135 }; 136 137 CP110_LABEL(comphy4): phy@4 { 138 reg = <4>; 139 #phy-cells = <1>; 140 }; 141 142 CP110_LABEL(comphy5): phy@5 { 143 reg = <5>; 144 #phy-cells = <1>; 145 }; 146 }; 147 148 CP110_LABEL(mdio): mdio@12a200 { 149 #address-cells = <1>; 150 #size-cells = <0>; 151 compatible = "marvell,orion-mdio"; 152 reg = <0x12a200 0x10>; 153 clocks = <&CP110_LABEL(clk) 1 9>, <&CP110_LABEL(clk) 1 5>, 154 <&CP110_LABEL(clk) 1 6>, <&CP110_LABEL(clk) 1 18>; 155 status = "disabled"; 156 }; 157 158 CP110_LABEL(xmdio): mdio@12a600 { 159 #address-cells = <1>; 160 #size-cells = <0>; 161 compatible = "marvell,xmdio"; 162 reg = <0x12a600 0x10>; 163 clocks = <&CP110_LABEL(clk) 1 5>, 164 <&CP110_LABEL(clk) 1 6>, <&CP110_LABEL(clk) 1 18>; 165 status = "disabled"; 166 }; 167 168 CP110_LABEL(icu): interrupt-controller@1e0000 { 169 compatible = "marvell,cp110-icu"; 170 reg = <0x1e0000 0x440>; 171 #interrupt-cells = <3>; 172 interrupt-controller; 173 msi-parent = <&gicp>; 174 }; 175 176 CP110_LABEL(rtc): rtc@284000 { 177 compatible = "marvell,armada-8k-rtc"; 178 reg = <0x284000 0x20>, <0x284080 0x24>; 179 reg-names = "rtc", "rtc-soc"; 180 interrupts = <ICU_GRP_NSR 77 IRQ_TYPE_LEVEL_HIGH>; 181 }; 182 183 CP110_LABEL(syscon0): system-controller@440000 { 184 compatible = "syscon", "simple-mfd"; 185 reg = <0x440000 0x2000>; 186 187 CP110_LABEL(clk): clock { 188 compatible = "marvell,cp110-clock"; 189 #clock-cells = <2>; 190 }; 191 192 CP110_LABEL(gpio1): gpio@100 { 193 compatible = "marvell,armada-8k-gpio"; 194 offset = <0x100>; 195 ngpios = <32>; 196 gpio-controller; 197 #gpio-cells = <2>; 198 gpio-ranges = <&CP110_LABEL(pinctrl) 0 0 32>; 199 interrupt-controller; 200 interrupts = <ICU_GRP_NSR 86 IRQ_TYPE_LEVEL_HIGH>, 201 <ICU_GRP_NSR 85 IRQ_TYPE_LEVEL_HIGH>, 202 <ICU_GRP_NSR 84 IRQ_TYPE_LEVEL_HIGH>, 203 <ICU_GRP_NSR 83 IRQ_TYPE_LEVEL_HIGH>; 204 status = "disabled"; 205 }; 206 207 CP110_LABEL(gpio2): gpio@140 { 208 compatible = "marvell,armada-8k-gpio"; 209 offset = <0x140>; 210 ngpios = <31>; 211 gpio-controller; 212 #gpio-cells = <2>; 213 gpio-ranges = <&CP110_LABEL(pinctrl) 0 32 31>; 214 interrupt-controller; 215 interrupts = <ICU_GRP_NSR 82 IRQ_TYPE_LEVEL_HIGH>, 216 <ICU_GRP_NSR 81 IRQ_TYPE_LEVEL_HIGH>, 217 <ICU_GRP_NSR 80 IRQ_TYPE_LEVEL_HIGH>, 218 <ICU_GRP_NSR 79 IRQ_TYPE_LEVEL_HIGH>; 219 status = "disabled"; 220 }; 221 }; 222 223 CP110_LABEL(syscon1): system-controller@400000 { 224 compatible = "syscon", "simple-mfd"; 225 reg = <0x400000 0x1000>; 226 #address-cells = <1>; 227 #size-cells = <1>; 228 229 CP110_LABEL(thermal): thermal-sensor@70 { 230 compatible = "marvell,armada-cp110-thermal"; 231 reg = <0x70 0x10>; 232 #thermal-sensor-cells = <1>; 233 }; 234 }; 235 236 CP110_LABEL(usb3_0): usb3@500000 { 237 compatible = "marvell,armada-8k-xhci", 238 "generic-xhci"; 239 reg = <0x500000 0x4000>; 240 dma-coherent; 241 interrupts = <ICU_GRP_NSR 106 IRQ_TYPE_LEVEL_HIGH>; 242 clock-names = "core", "reg"; 243 clocks = <&CP110_LABEL(clk) 1 22>, 244 <&CP110_LABEL(clk) 1 16>; 245 status = "disabled"; 246 }; 247 248 CP110_LABEL(usb3_1): usb3@510000 { 249 compatible = "marvell,armada-8k-xhci", 250 "generic-xhci"; 251 reg = <0x510000 0x4000>; 252 dma-coherent; 253 interrupts = <ICU_GRP_NSR 105 IRQ_TYPE_LEVEL_HIGH>; 254 clock-names = "core", "reg"; 255 clocks = <&CP110_LABEL(clk) 1 23>, 256 <&CP110_LABEL(clk) 1 16>; 257 status = "disabled"; 258 }; 259 260 CP110_LABEL(sata0): sata@540000 { 261 compatible = "marvell,armada-8k-ahci", 262 "generic-ahci"; 263 reg = <0x540000 0x30000>; 264 dma-coherent; 265 interrupts = <ICU_GRP_NSR 107 IRQ_TYPE_LEVEL_HIGH>; 266 clocks = <&CP110_LABEL(clk) 1 15>, 267 <&CP110_LABEL(clk) 1 16>; 268 status = "disabled"; 269 }; 270 271 CP110_LABEL(xor0): xor@6a0000 { 272 compatible = "marvell,armada-7k-xor", "marvell,xor-v2"; 273 reg = <0x6a0000 0x1000>, <0x6b0000 0x1000>; 274 dma-coherent; 275 msi-parent = <&gic_v2m0>; 276 clock-names = "core", "reg"; 277 clocks = <&CP110_LABEL(clk) 1 8>, 278 <&CP110_LABEL(clk) 1 14>; 279 }; 280 281 CP110_LABEL(xor1): xor@6c0000 { 282 compatible = "marvell,armada-7k-xor", "marvell,xor-v2"; 283 reg = <0x6c0000 0x1000>, <0x6d0000 0x1000>; 284 dma-coherent; 285 msi-parent = <&gic_v2m0>; 286 clock-names = "core", "reg"; 287 clocks = <&CP110_LABEL(clk) 1 7>, 288 <&CP110_LABEL(clk) 1 14>; 289 }; 290 291 CP110_LABEL(spi0): spi@700600 { 292 compatible = "marvell,armada-380-spi"; 293 reg = <0x700600 0x50>; 294 #address-cells = <0x1>; 295 #size-cells = <0x0>; 296 clock-names = "core", "axi"; 297 clocks = <&CP110_LABEL(clk) 1 21>, 298 <&CP110_LABEL(clk) 1 17>; 299 status = "disabled"; 300 }; 301 302 CP110_LABEL(spi1): spi@700680 { 303 compatible = "marvell,armada-380-spi"; 304 reg = <0x700680 0x50>; 305 #address-cells = <1>; 306 #size-cells = <0>; 307 clock-names = "core", "axi"; 308 clocks = <&CP110_LABEL(clk) 1 21>, 309 <&CP110_LABEL(clk) 1 17>; 310 status = "disabled"; 311 }; 312 313 CP110_LABEL(i2c0): i2c@701000 { 314 compatible = "marvell,mv78230-i2c"; 315 reg = <0x701000 0x20>; 316 #address-cells = <1>; 317 #size-cells = <0>; 318 interrupts = <ICU_GRP_NSR 120 IRQ_TYPE_LEVEL_HIGH>; 319 clock-names = "core", "reg"; 320 clocks = <&CP110_LABEL(clk) 1 21>, 321 <&CP110_LABEL(clk) 1 17>; 322 status = "disabled"; 323 }; 324 325 CP110_LABEL(i2c1): i2c@701100 { 326 compatible = "marvell,mv78230-i2c"; 327 reg = <0x701100 0x20>; 328 #address-cells = <1>; 329 #size-cells = <0>; 330 interrupts = <ICU_GRP_NSR 121 IRQ_TYPE_LEVEL_HIGH>; 331 clock-names = "core", "reg"; 332 clocks = <&CP110_LABEL(clk) 1 21>, 333 <&CP110_LABEL(clk) 1 17>; 334 status = "disabled"; 335 }; 336 337 CP110_LABEL(uart0): serial@702000 { 338 compatible = "snps,dw-apb-uart"; 339 reg = <0x702000 0x100>; 340 reg-shift = <2>; 341 interrupts = <ICU_GRP_NSR 122 IRQ_TYPE_LEVEL_HIGH>; 342 reg-io-width = <1>; 343 clock-names = "baudclk", "apb_pclk"; 344 clocks = <&CP110_LABEL(clk) 1 21>, 345 <&CP110_LABEL(clk) 1 17>; 346 status = "disabled"; 347 }; 348 349 CP110_LABEL(uart1): serial@702100 { 350 compatible = "snps,dw-apb-uart"; 351 reg = <0x702100 0x100>; 352 reg-shift = <2>; 353 interrupts = <ICU_GRP_NSR 123 IRQ_TYPE_LEVEL_HIGH>; 354 reg-io-width = <1>; 355 clock-names = "baudclk", "apb_pclk"; 356 clocks = <&CP110_LABEL(clk) 1 21>, 357 <&CP110_LABEL(clk) 1 17>; 358 status = "disabled"; 359 }; 360 361 CP110_LABEL(uart2): serial@702200 { 362 compatible = "snps,dw-apb-uart"; 363 reg = <0x702200 0x100>; 364 reg-shift = <2>; 365 interrupts = <ICU_GRP_NSR 124 IRQ_TYPE_LEVEL_HIGH>; 366 reg-io-width = <1>; 367 clock-names = "baudclk", "apb_pclk"; 368 clocks = <&CP110_LABEL(clk) 1 21>, 369 <&CP110_LABEL(clk) 1 17>; 370 status = "disabled"; 371 }; 372 373 CP110_LABEL(uart3): serial@702300 { 374 compatible = "snps,dw-apb-uart"; 375 reg = <0x702300 0x100>; 376 reg-shift = <2>; 377 interrupts = <ICU_GRP_NSR 125 IRQ_TYPE_LEVEL_HIGH>; 378 reg-io-width = <1>; 379 clock-names = "baudclk", "apb_pclk"; 380 clocks = <&CP110_LABEL(clk) 1 21>, 381 <&CP110_LABEL(clk) 1 17>; 382 status = "disabled"; 383 }; 384 385 CP110_LABEL(nand_controller): nand@720000 { 386 /* 387 * Due to the limitation of the pins available 388 * this controller is only usable on the CPM 389 * for A7K and on the CPS for A8K. 390 */ 391 compatible = "marvell,armada-8k-nand-controller", 392 "marvell,armada370-nand-controller"; 393 reg = <0x720000 0x54>; 394 #address-cells = <1>; 395 #size-cells = <0>; 396 interrupts = <ICU_GRP_NSR 115 IRQ_TYPE_LEVEL_HIGH>; 397 clock-names = "core", "reg"; 398 clocks = <&CP110_LABEL(clk) 1 2>, 399 <&CP110_LABEL(clk) 1 17>; 400 marvell,system-controller = <&CP110_LABEL(syscon0)>; 401 status = "disabled"; 402 }; 403 404 CP110_LABEL(trng): trng@760000 { 405 compatible = "marvell,armada-8k-rng", 406 "inside-secure,safexcel-eip76"; 407 reg = <0x760000 0x7d>; 408 interrupts = <ICU_GRP_NSR 95 IRQ_TYPE_LEVEL_HIGH>; 409 clock-names = "core", "reg"; 410 clocks = <&CP110_LABEL(clk) 1 25>, 411 <&CP110_LABEL(clk) 1 17>; 412 status = "okay"; 413 }; 414 415 CP110_LABEL(sdhci0): sdhci@780000 { 416 compatible = "marvell,armada-cp110-sdhci"; 417 reg = <0x780000 0x300>; 418 interrupts = <ICU_GRP_NSR 27 IRQ_TYPE_LEVEL_HIGH>; 419 clock-names = "core", "axi"; 420 clocks = <&CP110_LABEL(clk) 1 4>, <&CP110_LABEL(clk) 1 18>; 421 dma-coherent; 422 status = "disabled"; 423 }; 424 425 CP110_LABEL(crypto): crypto@800000 { 426 compatible = "inside-secure,safexcel-eip197b"; 427 reg = <0x800000 0x200000>; 428 interrupts = <ICU_GRP_NSR 87 IRQ_TYPE_LEVEL_HIGH>, 429 <ICU_GRP_NSR 88 IRQ_TYPE_LEVEL_HIGH>, 430 <ICU_GRP_NSR 89 IRQ_TYPE_LEVEL_HIGH>, 431 <ICU_GRP_NSR 90 IRQ_TYPE_LEVEL_HIGH>, 432 <ICU_GRP_NSR 91 IRQ_TYPE_LEVEL_HIGH>, 433 <ICU_GRP_NSR 92 IRQ_TYPE_LEVEL_HIGH>; 434 interrupt-names = "mem", "ring0", "ring1", 435 "ring2", "ring3", "eip"; 436 clock-names = "core", "reg"; 437 clocks = <&CP110_LABEL(clk) 1 26>, 438 <&CP110_LABEL(clk) 1 17>; 439 dma-coherent; 440 }; 441 }; 442 443 CP110_LABEL(pcie0): pcie@CP110_PCIE0_BASE { 444 compatible = "marvell,armada8k-pcie", "snps,dw-pcie"; 445 reg = <0 ADDRESSIFY(CP110_PCIE0_BASE) 0 0x10000>, 446 <0 CP110_PCIEx_CONF_BASE(0) 0 0x80000>; 447 reg-names = "ctrl", "config"; 448 #address-cells = <3>; 449 #size-cells = <2>; 450 #interrupt-cells = <1>; 451 device_type = "pci"; 452 dma-coherent; 453 msi-parent = <&gic_v2m0>; 454 455 bus-range = <0 0xff>; 456 ranges = 457 /* downstream I/O */ 458 <0x81000000 0 CP110_PCIEx_IO_BASE(0) 0 CP110_PCIEx_IO_BASE(0) 0 0x10000 459 /* non-prefetchable memory */ 460 0x82000000 0 CP110_PCIEx_MEM_BASE(0) 0 CP110_PCIEx_MEM_BASE(0) 0 0xf00000>; 461 interrupt-map-mask = <0 0 0 0>; 462 interrupt-map = <0 0 0 0 &CP110_LABEL(icu) ICU_GRP_NSR 22 IRQ_TYPE_LEVEL_HIGH>; 463 interrupts = <ICU_GRP_NSR 22 IRQ_TYPE_LEVEL_HIGH>; 464 num-lanes = <1>; 465 clock-names = "core", "reg"; 466 clocks = <&CP110_LABEL(clk) 1 13>, <&CP110_LABEL(clk) 1 14>; 467 status = "disabled"; 468 }; 469 470 CP110_LABEL(pcie1): pcie@CP110_PCIE1_BASE { 471 compatible = "marvell,armada8k-pcie", "snps,dw-pcie"; 472 reg = <0 ADDRESSIFY(CP110_PCIE1_BASE) 0 0x10000>, 473 <0 CP110_PCIEx_CONF_BASE(1) 0 0x80000>; 474 reg-names = "ctrl", "config"; 475 #address-cells = <3>; 476 #size-cells = <2>; 477 #interrupt-cells = <1>; 478 device_type = "pci"; 479 dma-coherent; 480 msi-parent = <&gic_v2m0>; 481 482 bus-range = <0 0xff>; 483 ranges = 484 /* downstream I/O */ 485 <0x81000000 0 CP110_PCIEx_IO_BASE(1) 0 CP110_PCIEx_IO_BASE(1) 0 0x10000 486 /* non-prefetchable memory */ 487 0x82000000 0 CP110_PCIEx_MEM_BASE(1) 0 CP110_PCIEx_MEM_BASE(1) 0 0xf00000>; 488 interrupt-map-mask = <0 0 0 0>; 489 interrupt-map = <0 0 0 0 &CP110_LABEL(icu) ICU_GRP_NSR 24 IRQ_TYPE_LEVEL_HIGH>; 490 interrupts = <ICU_GRP_NSR 24 IRQ_TYPE_LEVEL_HIGH>; 491 492 num-lanes = <1>; 493 clock-names = "core", "reg"; 494 clocks = <&CP110_LABEL(clk) 1 11>, <&CP110_LABEL(clk) 1 14>; 495 status = "disabled"; 496 }; 497 498 CP110_LABEL(pcie2): pcie@CP110_PCIE2_BASE { 499 compatible = "marvell,armada8k-pcie", "snps,dw-pcie"; 500 reg = <0 ADDRESSIFY(CP110_PCIE2_BASE) 0 0x10000>, 501 <0 CP110_PCIEx_CONF_BASE(2) 0 0x80000>; 502 reg-names = "ctrl", "config"; 503 #address-cells = <3>; 504 #size-cells = <2>; 505 #interrupt-cells = <1>; 506 device_type = "pci"; 507 dma-coherent; 508 msi-parent = <&gic_v2m0>; 509 510 bus-range = <0 0xff>; 511 ranges = 512 /* downstream I/O */ 513 <0x81000000 0 CP110_PCIEx_IO_BASE(2) 0 CP110_PCIEx_IO_BASE(2) 0 0x10000 514 /* non-prefetchable memory */ 515 0x82000000 0 CP110_PCIEx_MEM_BASE(2) 0 CP110_PCIEx_MEM_BASE(2) 0 0xf00000>; 516 interrupt-map-mask = <0 0 0 0>; 517 interrupt-map = <0 0 0 0 &CP110_LABEL(icu) ICU_GRP_NSR 23 IRQ_TYPE_LEVEL_HIGH>; 518 interrupts = <ICU_GRP_NSR 23 IRQ_TYPE_LEVEL_HIGH>; 519 520 num-lanes = <1>; 521 clock-names = "core", "reg"; 522 clocks = <&CP110_LABEL(clk) 1 12>, <&CP110_LABEL(clk) 1 14>; 523 status = "disabled"; 524 }; 525}; 526