1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (C) 2016 Marvell Technology Group Ltd. 4 * 5 * Device Tree file for Marvell Armada CP110. 6 */ 7 8#include <dt-bindings/interrupt-controller/mvebu-icu.h> 9 10#include "armada-common.dtsi" 11 12#define CP110_PCIEx_IO_BASE(iface) (CP110_PCIE_IO_BASE + (iface * 0x10000)) 13#define CP110_PCIEx_MEM_BASE(iface) (CP110_PCIE_MEM_BASE + (iface * 0x1000000)) 14#define CP110_PCIEx_CONF_BASE(iface) (CP110_PCIEx_MEM_BASE(iface) + 0xf00000) 15 16/ { 17 /* 18 * The contents of the node are defined below, in order to 19 * save one indentation level 20 */ 21 CP110_NAME: CP110_NAME { }; 22}; 23 24&CP110_NAME { 25 #address-cells = <2>; 26 #size-cells = <2>; 27 compatible = "simple-bus"; 28 interrupt-parent = <&CP110_LABEL(icu)>; 29 ranges; 30 31 config-space@CP110_BASE { 32 #address-cells = <1>; 33 #size-cells = <1>; 34 compatible = "simple-bus"; 35 ranges = <0x0 0x0 ADDRESSIFY(CP110_BASE) 0x2000000>; 36 37 CP110_LABEL(ethernet): ethernet@0 { 38 compatible = "marvell,armada-7k-pp22"; 39 reg = <0x0 0x100000>, <0x129000 0xb000>; 40 clocks = <&CP110_LABEL(clk) 1 3>, <&CP110_LABEL(clk) 1 9>, 41 <&CP110_LABEL(clk) 1 5>, <&CP110_LABEL(clk) 1 18>; 42 clock-names = "pp_clk", "gop_clk", 43 "mg_clk", "axi_clk"; 44 marvell,system-controller = <&CP110_LABEL(syscon0)>; 45 status = "disabled"; 46 dma-coherent; 47 48 CP110_LABEL(eth0): eth0 { 49 interrupts = <ICU_GRP_NSR 39 IRQ_TYPE_LEVEL_HIGH>, 50 <ICU_GRP_NSR 43 IRQ_TYPE_LEVEL_HIGH>, 51 <ICU_GRP_NSR 47 IRQ_TYPE_LEVEL_HIGH>, 52 <ICU_GRP_NSR 51 IRQ_TYPE_LEVEL_HIGH>, 53 <ICU_GRP_NSR 55 IRQ_TYPE_LEVEL_HIGH>, 54 <ICU_GRP_NSR 129 IRQ_TYPE_LEVEL_HIGH>; 55 interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2", 56 "tx-cpu3", "rx-shared", "link"; 57 port-id = <0>; 58 gop-port-id = <0>; 59 status = "disabled"; 60 }; 61 62 CP110_LABEL(eth1): eth1 { 63 interrupts = <ICU_GRP_NSR 40 IRQ_TYPE_LEVEL_HIGH>, 64 <ICU_GRP_NSR 44 IRQ_TYPE_LEVEL_HIGH>, 65 <ICU_GRP_NSR 48 IRQ_TYPE_LEVEL_HIGH>, 66 <ICU_GRP_NSR 52 IRQ_TYPE_LEVEL_HIGH>, 67 <ICU_GRP_NSR 56 IRQ_TYPE_LEVEL_HIGH>, 68 <ICU_GRP_NSR 128 IRQ_TYPE_LEVEL_HIGH>; 69 interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2", 70 "tx-cpu3", "rx-shared", "link"; 71 port-id = <1>; 72 gop-port-id = <2>; 73 status = "disabled"; 74 }; 75 76 CP110_LABEL(eth2): eth2 { 77 interrupts = <ICU_GRP_NSR 41 IRQ_TYPE_LEVEL_HIGH>, 78 <ICU_GRP_NSR 45 IRQ_TYPE_LEVEL_HIGH>, 79 <ICU_GRP_NSR 49 IRQ_TYPE_LEVEL_HIGH>, 80 <ICU_GRP_NSR 53 IRQ_TYPE_LEVEL_HIGH>, 81 <ICU_GRP_NSR 57 IRQ_TYPE_LEVEL_HIGH>, 82 <ICU_GRP_NSR 127 IRQ_TYPE_LEVEL_HIGH>; 83 interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2", 84 "tx-cpu3", "rx-shared", "link"; 85 port-id = <2>; 86 gop-port-id = <3>; 87 status = "disabled"; 88 }; 89 }; 90 91 CP110_LABEL(comphy): phy@120000 { 92 compatible = "marvell,comphy-cp110"; 93 reg = <0x120000 0x6000>; 94 marvell,system-controller = <&CP110_LABEL(syscon0)>; 95 #address-cells = <1>; 96 #size-cells = <0>; 97 98 CP110_LABEL(comphy0): phy@0 { 99 reg = <0>; 100 #phy-cells = <1>; 101 }; 102 103 CP110_LABEL(comphy1): phy@1 { 104 reg = <1>; 105 #phy-cells = <1>; 106 }; 107 108 CP110_LABEL(comphy2): phy@2 { 109 reg = <2>; 110 #phy-cells = <1>; 111 }; 112 113 CP110_LABEL(comphy3): phy@3 { 114 reg = <3>; 115 #phy-cells = <1>; 116 }; 117 118 CP110_LABEL(comphy4): phy@4 { 119 reg = <4>; 120 #phy-cells = <1>; 121 }; 122 123 CP110_LABEL(comphy5): phy@5 { 124 reg = <5>; 125 #phy-cells = <1>; 126 }; 127 }; 128 129 CP110_LABEL(mdio): mdio@12a200 { 130 #address-cells = <1>; 131 #size-cells = <0>; 132 compatible = "marvell,orion-mdio"; 133 reg = <0x12a200 0x10>; 134 clocks = <&CP110_LABEL(clk) 1 9>, <&CP110_LABEL(clk) 1 5>, 135 <&CP110_LABEL(clk) 1 6>, <&CP110_LABEL(clk) 1 18>; 136 status = "disabled"; 137 }; 138 139 CP110_LABEL(xmdio): mdio@12a600 { 140 #address-cells = <1>; 141 #size-cells = <0>; 142 compatible = "marvell,xmdio"; 143 reg = <0x12a600 0x10>; 144 status = "disabled"; 145 }; 146 147 CP110_LABEL(icu): interrupt-controller@1e0000 { 148 compatible = "marvell,cp110-icu"; 149 reg = <0x1e0000 0x10>; 150 #interrupt-cells = <3>; 151 interrupt-controller; 152 msi-parent = <&gicp>; 153 }; 154 155 CP110_LABEL(rtc): rtc@284000 { 156 compatible = "marvell,armada-8k-rtc"; 157 reg = <0x284000 0x20>, <0x284080 0x24>; 158 reg-names = "rtc", "rtc-soc"; 159 interrupts = <ICU_GRP_NSR 77 IRQ_TYPE_LEVEL_HIGH>; 160 }; 161 162 CP110_LABEL(thermal): thermal@400078 { 163 compatible = "marvell,armada-cp110-thermal"; 164 reg = <0x400078 0x4>, 165 <0x400070 0x8>; 166 }; 167 168 CP110_LABEL(syscon0): system-controller@440000 { 169 compatible = "syscon", "simple-mfd"; 170 reg = <0x440000 0x2000>; 171 172 CP110_LABEL(clk): clock { 173 compatible = "marvell,cp110-clock"; 174 #clock-cells = <2>; 175 }; 176 177 CP110_LABEL(gpio1): gpio@100 { 178 compatible = "marvell,armada-8k-gpio"; 179 offset = <0x100>; 180 ngpios = <32>; 181 gpio-controller; 182 #gpio-cells = <2>; 183 gpio-ranges = <&CP110_LABEL(pinctrl) 0 0 32>; 184 interrupt-controller; 185 interrupts = <ICU_GRP_NSR 86 IRQ_TYPE_LEVEL_HIGH>, 186 <ICU_GRP_NSR 85 IRQ_TYPE_LEVEL_HIGH>, 187 <ICU_GRP_NSR 84 IRQ_TYPE_LEVEL_HIGH>, 188 <ICU_GRP_NSR 83 IRQ_TYPE_LEVEL_HIGH>; 189 status = "disabled"; 190 }; 191 192 CP110_LABEL(gpio2): gpio@140 { 193 compatible = "marvell,armada-8k-gpio"; 194 offset = <0x140>; 195 ngpios = <31>; 196 gpio-controller; 197 #gpio-cells = <2>; 198 gpio-ranges = <&CP110_LABEL(pinctrl) 0 32 31>; 199 interrupt-controller; 200 interrupts = <ICU_GRP_NSR 82 IRQ_TYPE_LEVEL_HIGH>, 201 <ICU_GRP_NSR 81 IRQ_TYPE_LEVEL_HIGH>, 202 <ICU_GRP_NSR 80 IRQ_TYPE_LEVEL_HIGH>, 203 <ICU_GRP_NSR 79 IRQ_TYPE_LEVEL_HIGH>; 204 status = "disabled"; 205 }; 206 }; 207 208 CP110_LABEL(usb3_0): usb3@500000 { 209 compatible = "marvell,armada-8k-xhci", 210 "generic-xhci"; 211 reg = <0x500000 0x4000>; 212 dma-coherent; 213 interrupts = <ICU_GRP_NSR 106 IRQ_TYPE_LEVEL_HIGH>; 214 clocks = <&CP110_LABEL(clk) 1 22>; 215 status = "disabled"; 216 }; 217 218 CP110_LABEL(usb3_1): usb3@510000 { 219 compatible = "marvell,armada-8k-xhci", 220 "generic-xhci"; 221 reg = <0x510000 0x4000>; 222 dma-coherent; 223 interrupts = <ICU_GRP_NSR 105 IRQ_TYPE_LEVEL_HIGH>; 224 clocks = <&CP110_LABEL(clk) 1 23>; 225 status = "disabled"; 226 }; 227 228 CP110_LABEL(sata0): sata@540000 { 229 compatible = "marvell,armada-8k-ahci", 230 "generic-ahci"; 231 reg = <0x540000 0x30000>; 232 interrupts = <ICU_GRP_NSR 107 IRQ_TYPE_LEVEL_HIGH>; 233 clocks = <&CP110_LABEL(clk) 1 15>, 234 <&CP110_LABEL(clk) 1 16>; 235 status = "disabled"; 236 }; 237 238 CP110_LABEL(xor0): xor@6a0000 { 239 compatible = "marvell,armada-7k-xor", "marvell,xor-v2"; 240 reg = <0x6a0000 0x1000>, <0x6b0000 0x1000>; 241 dma-coherent; 242 msi-parent = <&gic_v2m0>; 243 clocks = <&CP110_LABEL(clk) 1 8>; 244 }; 245 246 CP110_LABEL(xor1): xor@6c0000 { 247 compatible = "marvell,armada-7k-xor", "marvell,xor-v2"; 248 reg = <0x6c0000 0x1000>, <0x6d0000 0x1000>; 249 dma-coherent; 250 msi-parent = <&gic_v2m0>; 251 clocks = <&CP110_LABEL(clk) 1 7>; 252 }; 253 254 CP110_LABEL(spi0): spi@700600 { 255 compatible = "marvell,armada-380-spi"; 256 reg = <0x700600 0x50>; 257 #address-cells = <0x1>; 258 #size-cells = <0x0>; 259 clock-names = "core", "axi"; 260 clocks = <&CP110_LABEL(clk) 1 21>, 261 <&CP110_LABEL(clk) 1 17>; 262 status = "disabled"; 263 }; 264 265 CP110_LABEL(spi1): spi@700680 { 266 compatible = "marvell,armada-380-spi"; 267 reg = <0x700680 0x50>; 268 #address-cells = <1>; 269 #size-cells = <0>; 270 clock-names = "core", "axi"; 271 clocks = <&CP110_LABEL(clk) 1 21>, 272 <&CP110_LABEL(clk) 1 17>; 273 status = "disabled"; 274 }; 275 276 CP110_LABEL(i2c0): i2c@701000 { 277 compatible = "marvell,mv78230-i2c"; 278 reg = <0x701000 0x20>; 279 #address-cells = <1>; 280 #size-cells = <0>; 281 interrupts = <ICU_GRP_NSR 120 IRQ_TYPE_LEVEL_HIGH>; 282 clock-names = "core", "reg"; 283 clocks = <&CP110_LABEL(clk) 1 21>, 284 <&CP110_LABEL(clk) 1 17>; 285 status = "disabled"; 286 }; 287 288 CP110_LABEL(i2c1): i2c@701100 { 289 compatible = "marvell,mv78230-i2c"; 290 reg = <0x701100 0x20>; 291 #address-cells = <1>; 292 #size-cells = <0>; 293 interrupts = <ICU_GRP_NSR 121 IRQ_TYPE_LEVEL_HIGH>; 294 clock-names = "core", "reg"; 295 clocks = <&CP110_LABEL(clk) 1 21>, 296 <&CP110_LABEL(clk) 1 17>; 297 status = "disabled"; 298 }; 299 300 CP110_LABEL(uart0): serial@702000 { 301 compatible = "snps,dw-apb-uart"; 302 reg = <0x702000 0x100>; 303 reg-shift = <2>; 304 interrupts = <ICU_GRP_NSR 122 IRQ_TYPE_LEVEL_HIGH>; 305 reg-io-width = <1>; 306 clocks = <&CP110_LABEL(clk) 1 21>; 307 status = "disabled"; 308 }; 309 310 CP110_LABEL(uart1): serial@702100 { 311 compatible = "snps,dw-apb-uart"; 312 reg = <0x702100 0x100>; 313 reg-shift = <2>; 314 interrupts = <ICU_GRP_NSR 123 IRQ_TYPE_LEVEL_HIGH>; 315 reg-io-width = <1>; 316 clocks = <&CP110_LABEL(clk) 1 21>; 317 status = "disabled"; 318 }; 319 320 CP110_LABEL(uart2): serial@702200 { 321 compatible = "snps,dw-apb-uart"; 322 reg = <0x702200 0x100>; 323 reg-shift = <2>; 324 interrupts = <ICU_GRP_NSR 124 IRQ_TYPE_LEVEL_HIGH>; 325 reg-io-width = <1>; 326 clocks = <&CP110_LABEL(clk) 1 21>; 327 status = "disabled"; 328 }; 329 330 CP110_LABEL(uart3): serial@702300 { 331 compatible = "snps,dw-apb-uart"; 332 reg = <0x702300 0x100>; 333 reg-shift = <2>; 334 interrupts = <ICU_GRP_NSR 125 IRQ_TYPE_LEVEL_HIGH>; 335 reg-io-width = <1>; 336 clocks = <&CP110_LABEL(clk) 1 21>; 337 status = "disabled"; 338 }; 339 340 CP110_LABEL(nand_controller): nand@720000 { 341 /* 342 * Due to the limitation of the pins available 343 * this controller is only usable on the CPM 344 * for A7K and on the CPS for A8K. 345 */ 346 compatible = "marvell,armada-8k-nand-controller", 347 "marvell,armada370-nand-controller"; 348 reg = <0x720000 0x54>; 349 #address-cells = <1>; 350 #size-cells = <0>; 351 interrupts = <ICU_GRP_NSR 115 IRQ_TYPE_LEVEL_HIGH>; 352 clocks = <&CP110_LABEL(clk) 1 2>; 353 marvell,system-controller = <&CP110_LABEL(syscon0)>; 354 status = "disabled"; 355 }; 356 357 CP110_LABEL(trng): trng@760000 { 358 compatible = "marvell,armada-8k-rng", 359 "inside-secure,safexcel-eip76"; 360 reg = <0x760000 0x7d>; 361 interrupts = <ICU_GRP_NSR 95 IRQ_TYPE_LEVEL_HIGH>; 362 clocks = <&CP110_LABEL(clk) 1 25>; 363 status = "okay"; 364 }; 365 366 CP110_LABEL(sdhci0): sdhci@780000 { 367 compatible = "marvell,armada-cp110-sdhci"; 368 reg = <0x780000 0x300>; 369 interrupts = <ICU_GRP_NSR 27 IRQ_TYPE_LEVEL_HIGH>; 370 clock-names = "core", "axi"; 371 clocks = <&CP110_LABEL(clk) 1 4>, <&CP110_LABEL(clk) 1 18>; 372 dma-coherent; 373 status = "disabled"; 374 }; 375 376 CP110_LABEL(crypto): crypto@800000 { 377 compatible = "inside-secure,safexcel-eip197"; 378 reg = <0x800000 0x200000>; 379 interrupts = <ICU_GRP_NSR 87 IRQ_TYPE_LEVEL_HIGH>, 380 <ICU_GRP_NSR 88 IRQ_TYPE_LEVEL_HIGH>, 381 <ICU_GRP_NSR 89 IRQ_TYPE_LEVEL_HIGH>, 382 <ICU_GRP_NSR 90 IRQ_TYPE_LEVEL_HIGH>, 383 <ICU_GRP_NSR 91 IRQ_TYPE_LEVEL_HIGH>, 384 <ICU_GRP_NSR 92 IRQ_TYPE_LEVEL_HIGH>; 385 interrupt-names = "mem", "ring0", "ring1", 386 "ring2", "ring3", "eip"; 387 clocks = <&CP110_LABEL(clk) 1 26>; 388 dma-coherent; 389 }; 390 }; 391 392 CP110_LABEL(pcie0): pcie@CP110_PCIE0_BASE { 393 compatible = "marvell,armada8k-pcie", "snps,dw-pcie"; 394 reg = <0 ADDRESSIFY(CP110_PCIE0_BASE) 0 0x10000>, 395 <0 CP110_PCIEx_CONF_BASE(0) 0 0x80000>; 396 reg-names = "ctrl", "config"; 397 #address-cells = <3>; 398 #size-cells = <2>; 399 #interrupt-cells = <1>; 400 device_type = "pci"; 401 dma-coherent; 402 msi-parent = <&gic_v2m0>; 403 404 bus-range = <0 0xff>; 405 ranges = 406 /* downstream I/O */ 407 <0x81000000 0 CP110_PCIEx_IO_BASE(0) 0 CP110_PCIEx_IO_BASE(0) 0 0x10000 408 /* non-prefetchable memory */ 409 0x82000000 0 CP110_PCIEx_MEM_BASE(0) 0 CP110_PCIEx_MEM_BASE(0) 0 0xf00000>; 410 interrupt-map-mask = <0 0 0 0>; 411 interrupt-map = <0 0 0 0 &CP110_LABEL(icu) ICU_GRP_NSR 22 IRQ_TYPE_LEVEL_HIGH>; 412 interrupts = <ICU_GRP_NSR 22 IRQ_TYPE_LEVEL_HIGH>; 413 num-lanes = <1>; 414 clocks = <&CP110_LABEL(clk) 1 13>; 415 status = "disabled"; 416 }; 417 418 CP110_LABEL(pcie1): pcie@CP110_PCIE1_BASE { 419 compatible = "marvell,armada8k-pcie", "snps,dw-pcie"; 420 reg = <0 ADDRESSIFY(CP110_PCIE1_BASE) 0 0x10000>, 421 <0 CP110_PCIEx_CONF_BASE(1) 0 0x80000>; 422 reg-names = "ctrl", "config"; 423 #address-cells = <3>; 424 #size-cells = <2>; 425 #interrupt-cells = <1>; 426 device_type = "pci"; 427 dma-coherent; 428 msi-parent = <&gic_v2m0>; 429 430 bus-range = <0 0xff>; 431 ranges = 432 /* downstream I/O */ 433 <0x81000000 0 CP110_PCIEx_IO_BASE(1) 0 CP110_PCIEx_IO_BASE(1) 0 0x10000 434 /* non-prefetchable memory */ 435 0x82000000 0 CP110_PCIEx_MEM_BASE(1) 0 CP110_PCIEx_MEM_BASE(1) 0 0xf00000>; 436 interrupt-map-mask = <0 0 0 0>; 437 interrupt-map = <0 0 0 0 &CP110_LABEL(icu) ICU_GRP_NSR 24 IRQ_TYPE_LEVEL_HIGH>; 438 interrupts = <ICU_GRP_NSR 24 IRQ_TYPE_LEVEL_HIGH>; 439 440 num-lanes = <1>; 441 clocks = <&CP110_LABEL(clk) 1 11>; 442 status = "disabled"; 443 }; 444 445 CP110_LABEL(pcie2): pcie@CP110_PCIE2_BASE { 446 compatible = "marvell,armada8k-pcie", "snps,dw-pcie"; 447 reg = <0 ADDRESSIFY(CP110_PCIE2_BASE) 0 0x10000>, 448 <0 CP110_PCIEx_CONF_BASE(2) 0 0x80000>; 449 reg-names = "ctrl", "config"; 450 #address-cells = <3>; 451 #size-cells = <2>; 452 #interrupt-cells = <1>; 453 device_type = "pci"; 454 dma-coherent; 455 msi-parent = <&gic_v2m0>; 456 457 bus-range = <0 0xff>; 458 ranges = 459 /* downstream I/O */ 460 <0x81000000 0 CP110_PCIEx_IO_BASE(2) 0 CP110_PCIEx_IO_BASE(2) 0 0x10000 461 /* non-prefetchable memory */ 462 0x82000000 0 CP110_PCIEx_MEM_BASE(2) 0 CP110_PCIEx_MEM_BASE(2) 0 0xf00000>; 463 interrupt-map-mask = <0 0 0 0>; 464 interrupt-map = <0 0 0 0 &CP110_LABEL(icu) ICU_GRP_NSR 23 IRQ_TYPE_LEVEL_HIGH>; 465 interrupts = <ICU_GRP_NSR 23 IRQ_TYPE_LEVEL_HIGH>; 466 467 num-lanes = <1>; 468 clocks = <&CP110_LABEL(clk) 1 12>; 469 status = "disabled"; 470 }; 471}; 472