1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (C) 2016 Marvell Technology Group Ltd. 4 * 5 * Device Tree file for Marvell Armada CP110. 6 */ 7 8#include <dt-bindings/interrupt-controller/mvebu-icu.h> 9 10#include "armada-common.dtsi" 11 12#define CP110_PCIEx_IO_BASE(iface) (CP110_PCIE_IO_BASE + (iface * 0x10000)) 13#define CP110_PCIEx_MEM_BASE(iface) (CP110_PCIE_MEM_BASE + (iface * 0x1000000)) 14#define CP110_PCIEx_CONF_BASE(iface) (CP110_PCIEx_MEM_BASE(iface) + 0xf00000) 15 16/ { 17 /* 18 * The contents of the node are defined below, in order to 19 * save one indentation level 20 */ 21 CP110_NAME: CP110_NAME { }; 22}; 23 24&CP110_NAME { 25 #address-cells = <2>; 26 #size-cells = <2>; 27 compatible = "simple-bus"; 28 interrupt-parent = <&CP110_LABEL(icu)>; 29 ranges; 30 31 config-space@CP110_BASE { 32 #address-cells = <1>; 33 #size-cells = <1>; 34 compatible = "simple-bus"; 35 ranges = <0x0 0x0 ADDRESSIFY(CP110_BASE) 0x2000000>; 36 37 CP110_LABEL(ethernet): ethernet@0 { 38 compatible = "marvell,armada-7k-pp22"; 39 reg = <0x0 0x100000>, <0x129000 0xb000>; 40 clocks = <&CP110_LABEL(clk) 1 3>, <&CP110_LABEL(clk) 1 9>, 41 <&CP110_LABEL(clk) 1 5>, <&CP110_LABEL(clk) 1 6>, 42 <&CP110_LABEL(clk) 1 18>; 43 clock-names = "pp_clk", "gop_clk", 44 "mg_clk", "mg_core_clk", "axi_clk"; 45 marvell,system-controller = <&CP110_LABEL(syscon0)>; 46 status = "disabled"; 47 dma-coherent; 48 49 CP110_LABEL(eth0): eth0 { 50 interrupts = <ICU_GRP_NSR 39 IRQ_TYPE_LEVEL_HIGH>, 51 <ICU_GRP_NSR 43 IRQ_TYPE_LEVEL_HIGH>, 52 <ICU_GRP_NSR 47 IRQ_TYPE_LEVEL_HIGH>, 53 <ICU_GRP_NSR 51 IRQ_TYPE_LEVEL_HIGH>, 54 <ICU_GRP_NSR 55 IRQ_TYPE_LEVEL_HIGH>, 55 <ICU_GRP_NSR 129 IRQ_TYPE_LEVEL_HIGH>; 56 interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2", 57 "tx-cpu3", "rx-shared", "link"; 58 port-id = <0>; 59 gop-port-id = <0>; 60 status = "disabled"; 61 }; 62 63 CP110_LABEL(eth1): eth1 { 64 interrupts = <ICU_GRP_NSR 40 IRQ_TYPE_LEVEL_HIGH>, 65 <ICU_GRP_NSR 44 IRQ_TYPE_LEVEL_HIGH>, 66 <ICU_GRP_NSR 48 IRQ_TYPE_LEVEL_HIGH>, 67 <ICU_GRP_NSR 52 IRQ_TYPE_LEVEL_HIGH>, 68 <ICU_GRP_NSR 56 IRQ_TYPE_LEVEL_HIGH>, 69 <ICU_GRP_NSR 128 IRQ_TYPE_LEVEL_HIGH>; 70 interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2", 71 "tx-cpu3", "rx-shared", "link"; 72 port-id = <1>; 73 gop-port-id = <2>; 74 status = "disabled"; 75 }; 76 77 CP110_LABEL(eth2): eth2 { 78 interrupts = <ICU_GRP_NSR 41 IRQ_TYPE_LEVEL_HIGH>, 79 <ICU_GRP_NSR 45 IRQ_TYPE_LEVEL_HIGH>, 80 <ICU_GRP_NSR 49 IRQ_TYPE_LEVEL_HIGH>, 81 <ICU_GRP_NSR 53 IRQ_TYPE_LEVEL_HIGH>, 82 <ICU_GRP_NSR 57 IRQ_TYPE_LEVEL_HIGH>, 83 <ICU_GRP_NSR 127 IRQ_TYPE_LEVEL_HIGH>; 84 interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2", 85 "tx-cpu3", "rx-shared", "link"; 86 port-id = <2>; 87 gop-port-id = <3>; 88 status = "disabled"; 89 }; 90 }; 91 92 CP110_LABEL(comphy): phy@120000 { 93 compatible = "marvell,comphy-cp110"; 94 reg = <0x120000 0x6000>; 95 marvell,system-controller = <&CP110_LABEL(syscon0)>; 96 #address-cells = <1>; 97 #size-cells = <0>; 98 99 CP110_LABEL(comphy0): phy@0 { 100 reg = <0>; 101 #phy-cells = <1>; 102 }; 103 104 CP110_LABEL(comphy1): phy@1 { 105 reg = <1>; 106 #phy-cells = <1>; 107 }; 108 109 CP110_LABEL(comphy2): phy@2 { 110 reg = <2>; 111 #phy-cells = <1>; 112 }; 113 114 CP110_LABEL(comphy3): phy@3 { 115 reg = <3>; 116 #phy-cells = <1>; 117 }; 118 119 CP110_LABEL(comphy4): phy@4 { 120 reg = <4>; 121 #phy-cells = <1>; 122 }; 123 124 CP110_LABEL(comphy5): phy@5 { 125 reg = <5>; 126 #phy-cells = <1>; 127 }; 128 }; 129 130 CP110_LABEL(mdio): mdio@12a200 { 131 #address-cells = <1>; 132 #size-cells = <0>; 133 compatible = "marvell,orion-mdio"; 134 reg = <0x12a200 0x10>; 135 clocks = <&CP110_LABEL(clk) 1 9>, <&CP110_LABEL(clk) 1 5>, 136 <&CP110_LABEL(clk) 1 6>, <&CP110_LABEL(clk) 1 18>; 137 status = "disabled"; 138 }; 139 140 CP110_LABEL(xmdio): mdio@12a600 { 141 #address-cells = <1>; 142 #size-cells = <0>; 143 compatible = "marvell,xmdio"; 144 reg = <0x12a600 0x10>; 145 clocks = <&CP110_LABEL(clk) 1 5>, 146 <&CP110_LABEL(clk) 1 6>, <&CP110_LABEL(clk) 1 18>; 147 status = "disabled"; 148 }; 149 150 CP110_LABEL(icu): interrupt-controller@1e0000 { 151 compatible = "marvell,cp110-icu"; 152 reg = <0x1e0000 0x440>; 153 #interrupt-cells = <3>; 154 interrupt-controller; 155 msi-parent = <&gicp>; 156 }; 157 158 CP110_LABEL(rtc): rtc@284000 { 159 compatible = "marvell,armada-8k-rtc"; 160 reg = <0x284000 0x20>, <0x284080 0x24>; 161 reg-names = "rtc", "rtc-soc"; 162 interrupts = <ICU_GRP_NSR 77 IRQ_TYPE_LEVEL_HIGH>; 163 }; 164 165 CP110_LABEL(thermal): thermal@400078 { 166 compatible = "marvell,armada-cp110-thermal"; 167 reg = <0x400078 0x4>, 168 <0x400070 0x8>; 169 }; 170 171 CP110_LABEL(syscon0): system-controller@440000 { 172 compatible = "syscon", "simple-mfd"; 173 reg = <0x440000 0x2000>; 174 175 CP110_LABEL(clk): clock { 176 compatible = "marvell,cp110-clock"; 177 #clock-cells = <2>; 178 }; 179 180 CP110_LABEL(gpio1): gpio@100 { 181 compatible = "marvell,armada-8k-gpio"; 182 offset = <0x100>; 183 ngpios = <32>; 184 gpio-controller; 185 #gpio-cells = <2>; 186 gpio-ranges = <&CP110_LABEL(pinctrl) 0 0 32>; 187 interrupt-controller; 188 interrupts = <ICU_GRP_NSR 86 IRQ_TYPE_LEVEL_HIGH>, 189 <ICU_GRP_NSR 85 IRQ_TYPE_LEVEL_HIGH>, 190 <ICU_GRP_NSR 84 IRQ_TYPE_LEVEL_HIGH>, 191 <ICU_GRP_NSR 83 IRQ_TYPE_LEVEL_HIGH>; 192 status = "disabled"; 193 }; 194 195 CP110_LABEL(gpio2): gpio@140 { 196 compatible = "marvell,armada-8k-gpio"; 197 offset = <0x140>; 198 ngpios = <31>; 199 gpio-controller; 200 #gpio-cells = <2>; 201 gpio-ranges = <&CP110_LABEL(pinctrl) 0 32 31>; 202 interrupt-controller; 203 interrupts = <ICU_GRP_NSR 82 IRQ_TYPE_LEVEL_HIGH>, 204 <ICU_GRP_NSR 81 IRQ_TYPE_LEVEL_HIGH>, 205 <ICU_GRP_NSR 80 IRQ_TYPE_LEVEL_HIGH>, 206 <ICU_GRP_NSR 79 IRQ_TYPE_LEVEL_HIGH>; 207 status = "disabled"; 208 }; 209 }; 210 211 CP110_LABEL(usb3_0): usb3@500000 { 212 compatible = "marvell,armada-8k-xhci", 213 "generic-xhci"; 214 reg = <0x500000 0x4000>; 215 dma-coherent; 216 interrupts = <ICU_GRP_NSR 106 IRQ_TYPE_LEVEL_HIGH>; 217 clock-names = "core", "reg"; 218 clocks = <&CP110_LABEL(clk) 1 22>, 219 <&CP110_LABEL(clk) 1 16>; 220 status = "disabled"; 221 }; 222 223 CP110_LABEL(usb3_1): usb3@510000 { 224 compatible = "marvell,armada-8k-xhci", 225 "generic-xhci"; 226 reg = <0x510000 0x4000>; 227 dma-coherent; 228 interrupts = <ICU_GRP_NSR 105 IRQ_TYPE_LEVEL_HIGH>; 229 clock-names = "core", "reg"; 230 clocks = <&CP110_LABEL(clk) 1 23>, 231 <&CP110_LABEL(clk) 1 16>; 232 status = "disabled"; 233 }; 234 235 CP110_LABEL(sata0): sata@540000 { 236 compatible = "marvell,armada-8k-ahci", 237 "generic-ahci"; 238 reg = <0x540000 0x30000>; 239 interrupts = <ICU_GRP_NSR 107 IRQ_TYPE_LEVEL_HIGH>; 240 clocks = <&CP110_LABEL(clk) 1 15>, 241 <&CP110_LABEL(clk) 1 16>; 242 status = "disabled"; 243 }; 244 245 CP110_LABEL(xor0): xor@6a0000 { 246 compatible = "marvell,armada-7k-xor", "marvell,xor-v2"; 247 reg = <0x6a0000 0x1000>, <0x6b0000 0x1000>; 248 dma-coherent; 249 msi-parent = <&gic_v2m0>; 250 clock-names = "core", "reg"; 251 clocks = <&CP110_LABEL(clk) 1 8>, 252 <&CP110_LABEL(clk) 1 14>; 253 }; 254 255 CP110_LABEL(xor1): xor@6c0000 { 256 compatible = "marvell,armada-7k-xor", "marvell,xor-v2"; 257 reg = <0x6c0000 0x1000>, <0x6d0000 0x1000>; 258 dma-coherent; 259 msi-parent = <&gic_v2m0>; 260 clock-names = "core", "reg"; 261 clocks = <&CP110_LABEL(clk) 1 7>, 262 <&CP110_LABEL(clk) 1 14>; 263 }; 264 265 CP110_LABEL(spi0): spi@700600 { 266 compatible = "marvell,armada-380-spi"; 267 reg = <0x700600 0x50>; 268 #address-cells = <0x1>; 269 #size-cells = <0x0>; 270 clock-names = "core", "axi"; 271 clocks = <&CP110_LABEL(clk) 1 21>, 272 <&CP110_LABEL(clk) 1 17>; 273 status = "disabled"; 274 }; 275 276 CP110_LABEL(spi1): spi@700680 { 277 compatible = "marvell,armada-380-spi"; 278 reg = <0x700680 0x50>; 279 #address-cells = <1>; 280 #size-cells = <0>; 281 clock-names = "core", "axi"; 282 clocks = <&CP110_LABEL(clk) 1 21>, 283 <&CP110_LABEL(clk) 1 17>; 284 status = "disabled"; 285 }; 286 287 CP110_LABEL(i2c0): i2c@701000 { 288 compatible = "marvell,mv78230-i2c"; 289 reg = <0x701000 0x20>; 290 #address-cells = <1>; 291 #size-cells = <0>; 292 interrupts = <ICU_GRP_NSR 120 IRQ_TYPE_LEVEL_HIGH>; 293 clock-names = "core", "reg"; 294 clocks = <&CP110_LABEL(clk) 1 21>, 295 <&CP110_LABEL(clk) 1 17>; 296 status = "disabled"; 297 }; 298 299 CP110_LABEL(i2c1): i2c@701100 { 300 compatible = "marvell,mv78230-i2c"; 301 reg = <0x701100 0x20>; 302 #address-cells = <1>; 303 #size-cells = <0>; 304 interrupts = <ICU_GRP_NSR 121 IRQ_TYPE_LEVEL_HIGH>; 305 clock-names = "core", "reg"; 306 clocks = <&CP110_LABEL(clk) 1 21>, 307 <&CP110_LABEL(clk) 1 17>; 308 status = "disabled"; 309 }; 310 311 CP110_LABEL(uart0): serial@702000 { 312 compatible = "snps,dw-apb-uart"; 313 reg = <0x702000 0x100>; 314 reg-shift = <2>; 315 interrupts = <ICU_GRP_NSR 122 IRQ_TYPE_LEVEL_HIGH>; 316 reg-io-width = <1>; 317 clock-names = "baudclk", "apb_pclk"; 318 clocks = <&CP110_LABEL(clk) 1 21>, 319 <&CP110_LABEL(clk) 1 17>; 320 status = "disabled"; 321 }; 322 323 CP110_LABEL(uart1): serial@702100 { 324 compatible = "snps,dw-apb-uart"; 325 reg = <0x702100 0x100>; 326 reg-shift = <2>; 327 interrupts = <ICU_GRP_NSR 123 IRQ_TYPE_LEVEL_HIGH>; 328 reg-io-width = <1>; 329 clock-names = "baudclk", "apb_pclk"; 330 clocks = <&CP110_LABEL(clk) 1 21>, 331 <&CP110_LABEL(clk) 1 17>; 332 status = "disabled"; 333 }; 334 335 CP110_LABEL(uart2): serial@702200 { 336 compatible = "snps,dw-apb-uart"; 337 reg = <0x702200 0x100>; 338 reg-shift = <2>; 339 interrupts = <ICU_GRP_NSR 124 IRQ_TYPE_LEVEL_HIGH>; 340 reg-io-width = <1>; 341 clock-names = "baudclk", "apb_pclk"; 342 clocks = <&CP110_LABEL(clk) 1 21>, 343 <&CP110_LABEL(clk) 1 17>; 344 status = "disabled"; 345 }; 346 347 CP110_LABEL(uart3): serial@702300 { 348 compatible = "snps,dw-apb-uart"; 349 reg = <0x702300 0x100>; 350 reg-shift = <2>; 351 interrupts = <ICU_GRP_NSR 125 IRQ_TYPE_LEVEL_HIGH>; 352 reg-io-width = <1>; 353 clock-names = "baudclk", "apb_pclk"; 354 clocks = <&CP110_LABEL(clk) 1 21>, 355 <&CP110_LABEL(clk) 1 17>; 356 status = "disabled"; 357 }; 358 359 CP110_LABEL(nand_controller): nand@720000 { 360 /* 361 * Due to the limitation of the pins available 362 * this controller is only usable on the CPM 363 * for A7K and on the CPS for A8K. 364 */ 365 compatible = "marvell,armada-8k-nand-controller", 366 "marvell,armada370-nand-controller"; 367 reg = <0x720000 0x54>; 368 #address-cells = <1>; 369 #size-cells = <0>; 370 interrupts = <ICU_GRP_NSR 115 IRQ_TYPE_LEVEL_HIGH>; 371 clock-names = "core", "reg"; 372 clocks = <&CP110_LABEL(clk) 1 2>, 373 <&CP110_LABEL(clk) 1 17>; 374 marvell,system-controller = <&CP110_LABEL(syscon0)>; 375 status = "disabled"; 376 }; 377 378 CP110_LABEL(trng): trng@760000 { 379 compatible = "marvell,armada-8k-rng", 380 "inside-secure,safexcel-eip76"; 381 reg = <0x760000 0x7d>; 382 interrupts = <ICU_GRP_NSR 95 IRQ_TYPE_LEVEL_HIGH>; 383 clock-names = "core", "reg"; 384 clocks = <&CP110_LABEL(clk) 1 25>, 385 <&CP110_LABEL(clk) 1 17>; 386 status = "okay"; 387 }; 388 389 CP110_LABEL(sdhci0): sdhci@780000 { 390 compatible = "marvell,armada-cp110-sdhci"; 391 reg = <0x780000 0x300>; 392 interrupts = <ICU_GRP_NSR 27 IRQ_TYPE_LEVEL_HIGH>; 393 clock-names = "core", "axi"; 394 clocks = <&CP110_LABEL(clk) 1 4>, <&CP110_LABEL(clk) 1 18>; 395 dma-coherent; 396 status = "disabled"; 397 }; 398 399 CP110_LABEL(crypto): crypto@800000 { 400 compatible = "inside-secure,safexcel-eip197"; 401 reg = <0x800000 0x200000>; 402 interrupts = <ICU_GRP_NSR 87 IRQ_TYPE_LEVEL_HIGH>, 403 <ICU_GRP_NSR 88 IRQ_TYPE_LEVEL_HIGH>, 404 <ICU_GRP_NSR 89 IRQ_TYPE_LEVEL_HIGH>, 405 <ICU_GRP_NSR 90 IRQ_TYPE_LEVEL_HIGH>, 406 <ICU_GRP_NSR 91 IRQ_TYPE_LEVEL_HIGH>, 407 <ICU_GRP_NSR 92 IRQ_TYPE_LEVEL_HIGH>; 408 interrupt-names = "mem", "ring0", "ring1", 409 "ring2", "ring3", "eip"; 410 clock-names = "core", "reg"; 411 clocks = <&CP110_LABEL(clk) 1 26>, 412 <&CP110_LABEL(clk) 1 17>; 413 dma-coherent; 414 }; 415 }; 416 417 CP110_LABEL(pcie0): pcie@CP110_PCIE0_BASE { 418 compatible = "marvell,armada8k-pcie", "snps,dw-pcie"; 419 reg = <0 ADDRESSIFY(CP110_PCIE0_BASE) 0 0x10000>, 420 <0 CP110_PCIEx_CONF_BASE(0) 0 0x80000>; 421 reg-names = "ctrl", "config"; 422 #address-cells = <3>; 423 #size-cells = <2>; 424 #interrupt-cells = <1>; 425 device_type = "pci"; 426 dma-coherent; 427 msi-parent = <&gic_v2m0>; 428 429 bus-range = <0 0xff>; 430 ranges = 431 /* downstream I/O */ 432 <0x81000000 0 CP110_PCIEx_IO_BASE(0) 0 CP110_PCIEx_IO_BASE(0) 0 0x10000 433 /* non-prefetchable memory */ 434 0x82000000 0 CP110_PCIEx_MEM_BASE(0) 0 CP110_PCIEx_MEM_BASE(0) 0 0xf00000>; 435 interrupt-map-mask = <0 0 0 0>; 436 interrupt-map = <0 0 0 0 &CP110_LABEL(icu) ICU_GRP_NSR 22 IRQ_TYPE_LEVEL_HIGH>; 437 interrupts = <ICU_GRP_NSR 22 IRQ_TYPE_LEVEL_HIGH>; 438 num-lanes = <1>; 439 clock-names = "core", "reg"; 440 clocks = <&CP110_LABEL(clk) 1 13>, <&CP110_LABEL(clk) 1 14>; 441 status = "disabled"; 442 }; 443 444 CP110_LABEL(pcie1): pcie@CP110_PCIE1_BASE { 445 compatible = "marvell,armada8k-pcie", "snps,dw-pcie"; 446 reg = <0 ADDRESSIFY(CP110_PCIE1_BASE) 0 0x10000>, 447 <0 CP110_PCIEx_CONF_BASE(1) 0 0x80000>; 448 reg-names = "ctrl", "config"; 449 #address-cells = <3>; 450 #size-cells = <2>; 451 #interrupt-cells = <1>; 452 device_type = "pci"; 453 dma-coherent; 454 msi-parent = <&gic_v2m0>; 455 456 bus-range = <0 0xff>; 457 ranges = 458 /* downstream I/O */ 459 <0x81000000 0 CP110_PCIEx_IO_BASE(1) 0 CP110_PCIEx_IO_BASE(1) 0 0x10000 460 /* non-prefetchable memory */ 461 0x82000000 0 CP110_PCIEx_MEM_BASE(1) 0 CP110_PCIEx_MEM_BASE(1) 0 0xf00000>; 462 interrupt-map-mask = <0 0 0 0>; 463 interrupt-map = <0 0 0 0 &CP110_LABEL(icu) ICU_GRP_NSR 24 IRQ_TYPE_LEVEL_HIGH>; 464 interrupts = <ICU_GRP_NSR 24 IRQ_TYPE_LEVEL_HIGH>; 465 466 num-lanes = <1>; 467 clock-names = "core", "reg"; 468 clocks = <&CP110_LABEL(clk) 1 11>, <&CP110_LABEL(clk) 1 14>; 469 status = "disabled"; 470 }; 471 472 CP110_LABEL(pcie2): pcie@CP110_PCIE2_BASE { 473 compatible = "marvell,armada8k-pcie", "snps,dw-pcie"; 474 reg = <0 ADDRESSIFY(CP110_PCIE2_BASE) 0 0x10000>, 475 <0 CP110_PCIEx_CONF_BASE(2) 0 0x80000>; 476 reg-names = "ctrl", "config"; 477 #address-cells = <3>; 478 #size-cells = <2>; 479 #interrupt-cells = <1>; 480 device_type = "pci"; 481 dma-coherent; 482 msi-parent = <&gic_v2m0>; 483 484 bus-range = <0 0xff>; 485 ranges = 486 /* downstream I/O */ 487 <0x81000000 0 CP110_PCIEx_IO_BASE(2) 0 CP110_PCIEx_IO_BASE(2) 0 0x10000 488 /* non-prefetchable memory */ 489 0x82000000 0 CP110_PCIEx_MEM_BASE(2) 0 CP110_PCIEx_MEM_BASE(2) 0 0xf00000>; 490 interrupt-map-mask = <0 0 0 0>; 491 interrupt-map = <0 0 0 0 &CP110_LABEL(icu) ICU_GRP_NSR 23 IRQ_TYPE_LEVEL_HIGH>; 492 interrupts = <ICU_GRP_NSR 23 IRQ_TYPE_LEVEL_HIGH>; 493 494 num-lanes = <1>; 495 clock-names = "core", "reg"; 496 clocks = <&CP110_LABEL(clk) 1 12>, <&CP110_LABEL(clk) 1 14>; 497 status = "disabled"; 498 }; 499}; 500