Revision tags: v6.6.25, v6.6.24, v6.6.23, v6.6.16, v6.6.15, v6.6.14, v6.6.13, v6.6.12, v6.6.11, v6.6.10, v6.6.9, v6.6.8, v6.6.7, v6.6.6, v6.6.5, v6.6.4, v6.6.3, v6.6.2, v6.5.11, v6.6.1, v6.5.10, v6.6, v6.5.9, v6.5.8, v6.5.7, v6.5.6, v6.5.5, v6.5.4, v6.5.3, v6.5.2, v6.1.51, v6.5.1, v6.1.50, v6.5, v6.1.49, v6.1.48, v6.1.46, v6.1.45, v6.1.44, v6.1.43, v6.1.42, v6.1.41, v6.1.40, v6.1.39, v6.1.38, v6.1.37, v6.1.36, v6.4, v6.1.35, v6.1.34, v6.1.33, v6.1.32, v6.1.31, v6.1.30, v6.1.29, v6.1.28, v6.1.27, v6.1.26, v6.3, v6.1.25, v6.1.24, v6.1.23, v6.1.22, v6.1.21, v6.1.20, v6.1.19, v6.1.18, v6.1.17, v6.1.16, v6.1.15, v6.1.14, v6.1.13, v6.2, v6.1.12, v6.1.11, v6.1.10 |
|
#
4dcc844c |
| 01-Feb-2023 |
Heiner Kallweit <hkallweit1@gmail.com> |
arm64: dts: meson: adjust order of some compatibles
During review of a new yaml binding, affecting these dts, it turned out that some compatibles aren't ordered as they should be. Order should be mo
arm64: dts: meson: adjust order of some compatibles
During review of a new yaml binding, affecting these dts, it turned out that some compatibles aren't ordered as they should be. Order should be most specific to least specific.
Suggested-by: Rob Herring <robh+dt@kernel.org> Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Link: https://lore.kernel.org/r/1ce888df-6096-73de-a98a-354d086428d4@gmail.com Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
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Revision tags: v6.1.9, v6.1.8, v6.1.7, v6.1.6, v6.1.5, v6.0.19, v6.0.18, v6.1.4, v6.1.3, v6.0.17, v6.1.2, v6.0.16, v6.1.1, v6.0.15, v6.0.14, v6.0.13, v6.1, v6.0.12, v6.0.11, v6.0.10, v5.15.80, v6.0.9, v5.15.79, v6.0.8, v5.15.78, v6.0.7, v5.15.77, v5.15.76, v6.0.6, v6.0.5, v5.15.75, v6.0.4 |
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#
ce759829 |
| 21-Oct-2022 |
Amjad Ouled-Ameur <aouledameur@baylibre.com> |
arm64: dts: meson-gxbb: add SPI pinctrl nodes for CLK
Add SPICC Controller pin nodes for CLK line when idle for Amlogic GXBB SoCs.
Signed-off-by: Amjad Ouled-Ameur <aouledameur@baylibre.com> Review
arm64: dts: meson-gxbb: add SPI pinctrl nodes for CLK
Add SPICC Controller pin nodes for CLK line when idle for Amlogic GXBB SoCs.
Signed-off-by: Amjad Ouled-Ameur <aouledameur@baylibre.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Link: https://lore.kernel.org/r/20221004-up-aml-fix-spi-v4-4-0342d8e10c49@baylibre.com Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
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Revision tags: v6.0.3, v6.0.2, v5.15.74, v5.15.73, v6.0.1, v5.15.72, v6.0, v5.15.71, v5.15.70, v5.15.69, v5.15.68, v5.15.67, v5.15.66, v5.15.65, v5.15.64, v5.15.63, v5.15.62, v5.15.61, v5.15.60, v5.15.59, v5.19, v5.15.58, v5.15.57, v5.15.56, v5.15.55, v5.15.54, v5.15.53, v5.15.52, v5.15.51, v5.15.50, v5.15.49, v5.15.48, v5.15.47, v5.15.46, v5.15.45, v5.15.44, v5.15.43, v5.15.42, v5.18, v5.15.41, v5.15.40, v5.15.39, v5.15.38, v5.15.37, v5.15.36, v5.15.35, v5.15.34, v5.15.33, v5.15.32, v5.15.31, v5.17, v5.15.30, v5.15.29, v5.15.28, v5.15.27, v5.15.26, v5.15.25, v5.15.24, v5.15.23, v5.15.22, v5.15.21, v5.15.20, v5.15.19, v5.15.18, v5.15.17, v5.4.173, v5.15.16, v5.15.15, v5.16, v5.15.10, v5.15.9, v5.15.8, v5.15.7, v5.15.6, v5.15.5, v5.15.4, v5.15.3, v5.15.2, v5.15.1, v5.15, v5.14.14, v5.14.13, v5.14.12, v5.14.11, v5.14.10, v5.14.9, v5.14.8, v5.14.7, v5.14.6, v5.10.67, v5.10.66, v5.14.5, v5.14.4, v5.10.65, v5.14.3, v5.10.64, v5.14.2, v5.10.63, v5.14.1, v5.10.62, v5.14, v5.10.61, v5.10.60, v5.10.53, v5.10.52, v5.10.51, v5.10.50, v5.10.49, v5.13, v5.10.46, v5.10.43, v5.10.42, v5.10.41, v5.10.40, v5.10.39, v5.4.119, v5.10.36, v5.10.35, v5.10.34, v5.4.116, v5.10.33, v5.12, v5.10.32, v5.10.31, v5.10.30, v5.10.27, v5.10.26, v5.10.25, v5.10.24, v5.10.23, v5.10.22, v5.10.21, v5.10.20, v5.10.19, v5.4.101, v5.10.18, v5.10.17, v5.11, v5.10.16, v5.10.15, v5.10.14, v5.10, v5.8.17, v5.8.16, v5.8.15, v5.9, v5.8.14, v5.8.13, v5.8.12, v5.8.11, v5.8.10, v5.8.9, v5.8.8, v5.8.7, v5.8.6, v5.4.62, v5.8.5, v5.8.4, v5.4.61, v5.8.3, v5.4.60, v5.8.2, v5.4.59, v5.8.1, v5.4.58, v5.4.57, v5.4.56, v5.8, v5.7.12, v5.4.55, v5.7.11, v5.4.54, v5.7.10, v5.4.53 |
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#
46ffadc7 |
| 19-Jul-2020 |
Martin Blumenstingl <martin.blumenstingl@googlemail.com> |
arm64: dts: amlogic: meson-gx: add the Mali-450 OPP table and use DVFS
Add the OPP table for the Mali-450 GPU and drop the hardcoded initial clock configuration. This enables GPU DVFS and thus saves
arm64: dts: amlogic: meson-gx: add the Mali-450 OPP table and use DVFS
Add the OPP table for the Mali-450 GPU and drop the hardcoded initial clock configuration. This enables GPU DVFS and thus saves power when the GPU is not in use while still being able switch to a higher clock on demand.
Set the GP0_PLL clock to 744MHz (which is the only frequency which cannot be derived from the FCLK dividers) as the clock driver avoids setting the parent clock rates so the MPLL clocks aren't changed (as these are reserved for audio). The only exception to this is the GXL S805X package because the 744MHz OPP isn't working correctly there.
While here, make most of meson-gxl-mali re-usable to reduce the amount of duplicate code between GXBB and GXL. This is more important now as we don't want to duplicate the GPU OPP table.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com> Link: https://lore.kernel.org/r/20200719173213.639540-2-martin.blumenstingl@googlemail.com
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Revision tags: v5.4.52, v5.7.9, v5.7.8, v5.4.51, v5.4.50, v5.7.7, v5.4.49, v5.7.6, v5.7.5, v5.4.48 |
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#
32b5f4b6 |
| 20-Jun-2020 |
Martin Blumenstingl <martin.blumenstingl@googlemail.com> |
arm64: dts: amlogic: Add the Ethernet "timing-adjustment" clock
Add the "timing-adjustment" clock now that we know how it is connected to the PRG_ETHERNET registers. It is used internally to generat
arm64: dts: amlogic: Add the Ethernet "timing-adjustment" clock
Add the "timing-adjustment" clock now that we know how it is connected to the PRG_ETHERNET registers. It is used internally to generate the RGMII RX delay on the MAC side (if needed).
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Link: https://lore.kernel.org/r/20200620162347.26159-1-martin.blumenstingl@googlemail.com
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#
5273d6ca |
| 20-Jun-2020 |
Martin Blumenstingl <martin.blumenstingl@googlemail.com> |
arm64: dts: meson-gx: Switch to the meson-ee-pwrc bindings
The "amlogic,meson-gx-pwrc-vpu" binding only supports the VPU power domain, while actually there are more power domains behind that set of
arm64: dts: meson-gx: Switch to the meson-ee-pwrc bindings
The "amlogic,meson-gx-pwrc-vpu" binding only supports the VPU power domain, while actually there are more power domains behind that set of registers. Switch to the new bindings so we can add more power domains as needed.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Link: https://lore.kernel.org/r/20200620161211.23685-1-martin.blumenstingl@googlemail.com
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Revision tags: v5.7.4, v5.7.3, v5.4.47, v5.4.46, v5.7.2, v5.4.45, v5.7.1, v5.4.44, v5.7, v5.4.43, v5.4.42, v5.4.41, v5.4.40, v5.4.39, v5.4.38, v5.4.37, v5.4.36, v5.4.35 |
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#
4cc1b265 |
| 21-Apr-2020 |
Jerome Brunet <jbrunet@baylibre.com> |
arm64: dts: meson-gx: add aiu support
Add the AIU audio device to the Amlogic GX SoC family DT. ATM, this device provides the i2s and spdif output stages and also the hdmi and internal codec glues.
arm64: dts: meson-gx: add aiu support
Add the AIU audio device to the Amlogic GX SoC family DT. ATM, this device provides the i2s and spdif output stages and also the hdmi and internal codec glues.
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com> Tested-by: Christian Hewitt <christianshewitt@gmail.com> Link: https://lore.kernel.org/r/20200421163935.775935-3-jbrunet@baylibre.com
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Revision tags: v5.4.34, v5.4.33, v5.4.32, v5.4.31, v5.4.30, v5.4.29, v5.6, v5.4.28, v5.4.27, v5.4.26, v5.4.25, v5.4.24, v5.4.23, v5.4.22, v5.4.21, v5.4.20, v5.4.19, v5.4.18, v5.4.17, v5.4.16, v5.5, v5.4.15, v5.4.14, v5.4.13, v5.4.12, v5.4.11, v5.4.10, v5.4.9, v5.4.8, v5.4.7, v5.4.6, v5.4.5, v5.4.4, v5.4.3, v5.3.15, v5.4.2, v5.4.1, v5.3.14, v5.4, v5.3.13, v5.3.12, v5.3.11, v5.3.10, v5.3.9, v5.3.8, v5.3.7, v5.3.6, v5.3.5, v5.3.4, v5.3.3, v5.3.2, v5.3.1, v5.3, v5.2.14, v5.3-rc8, v5.2.13, v5.2.12, v5.2.11, v5.2.10, v5.2.9, v5.2.8, v5.2.7, v5.2.6, v5.2.5, v5.2.4 |
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#
4be247f7 |
| 26-Jul-2019 |
Maxime Jourdan <mjourdan@baylibre.com> |
arm64: dts: meson: add video decoder entries
This enables the video decoder for GXBB, GXL and GXM chips
Signed-off-by: Maxime Jourdan <mjourdan@baylibre.com> Reviewed-by: Neil Armstrong <narmstrong
arm64: dts: meson: add video decoder entries
This enables the video decoder for GXBB, GXL and GXM chips
Signed-off-by: Maxime Jourdan <mjourdan@baylibre.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
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Revision tags: v5.2.3, v5.2.2, v5.2.1, v5.2, v5.1.16, v5.1.15, v5.1.14, v5.1.13, v5.1.12, v5.1.11, v5.1.10, v5.1.9, v5.1.8, v5.1.7, v5.1.6, v5.1.5, v5.1.4, v5.1.3, v5.1.2, v5.1.1, v5.0.14, v5.1, v5.0.13, v5.0.12, v5.0.11, v5.0.10, v5.0.9 |
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#
b43033b1 |
| 18-Apr-2019 |
Jerome Brunet <jbrunet@baylibre.com> |
arm64: dts: meson: fix mmc pin bias
Clk pin does not require bias, data strobe should be pulled low. The rest of the pin (data and cmd) are pulled up.
Signed-off-by: Jerome Brunet <jbrunet@baylibre
arm64: dts: meson: fix mmc pin bias
Clk pin does not require bias, data strobe should be pulled low. The rest of the pin (data and cmd) are pulled up.
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
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Revision tags: v5.0.8, v5.0.7, v5.0.6, v5.0.5, v5.0.4, v5.0.3, v4.19.29, v5.0.2, v4.19.28, v5.0.1, v4.19.27, v5.0, v4.19.26, v4.19.25, v4.19.24, v4.19.23, v4.19.22, v4.19.21, v4.19.20, v4.19.19, v4.19.18, v4.19.17, v4.19.16 |
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#
03b37035 |
| 16-Jan-2019 |
Maxime Jourdan <mjourdan@baylibre.com> |
arm64: dts: meson-gx: add support for simplefb
SimpleFB allows transferring a framebuffer from the firmware/bootloader to the kernel, while making sure the related clocks and power supplies stay ena
arm64: dts: meson-gx: add support for simplefb
SimpleFB allows transferring a framebuffer from the firmware/bootloader to the kernel, while making sure the related clocks and power supplies stay enabled.
Add nodes for CVBS and HDMI Simple Framebuffers.
Signed-off-by: Maxime Jourdan <mjourdan@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
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Revision tags: v4.19.15, v4.19.14, v4.19.13, v4.19.12, v4.19.11, v4.19.10, v4.19.9, v4.19.8, v4.19.7 |
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#
16361ff2 |
| 03-Dec-2018 |
Jerome Brunet <jbrunet@baylibre.com> |
arm64: dts: meson: add clock controller clock inputs
Add the clock inputs of the clock controllers
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.
arm64: dts: meson: add clock controller clock inputs
Add the clock inputs of the clock controllers
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
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Revision tags: v4.19.6, v4.19.5, v4.19.4, v4.18.20, v4.19.3, v4.18.19, v4.19.2, v4.18.18 |
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#
1c5cc1c8 |
| 09-Nov-2018 |
Jerome Brunet <jbrunet@baylibre.com> |
arm64: dts: meson: consistently disable pin bias
On Amlogic chipsets, the bias set through pinconf applies to the pad itself, not only the GPIO function. This means that even when we change the func
arm64: dts: meson: consistently disable pin bias
On Amlogic chipsets, the bias set through pinconf applies to the pad itself, not only the GPIO function. This means that even when we change the function of the pad from GPIO to anything else, the bias previously set still applies.
As we have seen with the eMMC, depending on the bias type and the function, it may trigger problems.
The underlying issue is that we inherit whatever was left by previous user of the pad (pinconf, u-boot or the ROM code). As a consequence, the actual setup we will get is undefined.
There is nothing mentioned in the documentation about pad bias and pinmux function, however leaving it undefined is not an option.
This change consistently disable the pad bias for every pinmux functions. It seems to work well, we can only assume that the necessary bias (if any) is already provided by the pin function itself.
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
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#
96a13691 |
| 09-Nov-2018 |
Jerome Brunet <jbrunet@baylibre.com> |
arm64: dts: meson: disable pad bias for mmc pinmuxes
In some cases (such as a boot from SPI) the bootloader or the ROM code may leave a bias pull-down on the mmc pins. If so the MMC will fail during
arm64: dts: meson: disable pad bias for mmc pinmuxes
In some cases (such as a boot from SPI) the bootloader or the ROM code may leave a bias pull-down on the mmc pins. If so the MMC will fail during the initialisation.
Explicitly disabling the pinmux solves the problem.
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
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#
06096d7a |
| 09-Nov-2018 |
Jerome Brunet <jbrunet@baylibre.com> |
arm64: dts: meson: remove extra subnode in mmc clk_gate pinmux
In the pinmux of the mmc clk_gate nodes, we define 2 subnodes. One for the function definition, the other for the bias. This is not nec
arm64: dts: meson: remove extra subnode in mmc clk_gate pinmux
In the pinmux of the mmc clk_gate nodes, we define 2 subnodes. One for the function definition, the other for the bias. This is not necessary since we can define the function and the bias in the same subnode.
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
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Revision tags: v4.18.17, v4.19.1 |
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#
eed5afc6 |
| 30-Oct-2018 |
Jerome Brunet <jbrunet@baylibre.com> |
arm64: dts: meson-gx: add efuse pclk
Add the required peripheral clock for the efuse device.
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
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Revision tags: v4.19, v4.18.16, v4.18.15, v4.18.14, v4.18.13, v4.18.12, v4.18.11, v4.18.10, v4.18.9 |
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#
68ecb5c1 |
| 13-Sep-2018 |
Rob Herring <robh@kernel.org> |
arm64: dts: meson: Fix erroneous SPI bus warnings
dtc has new checks for SPI buses. The meson dts files have a node named spi' which causes false positive warnings. As the node is a pinctrl child no
arm64: dts: meson: Fix erroneous SPI bus warnings
dtc has new checks for SPI buses. The meson dts files have a node named spi' which causes false positive warnings. As the node is a pinctrl child node, change the node name to be 'spi-pins' to fix the warnings.
arch/arm64/boot/dts/amlogic/meson-gxbb-nanopi-k2.dtb: Warning (spi_bus_bridge): /soc/periphs@c8834000/pinctrl@4b0/spi: incorrect #address-cells for SPI bus
Cc: Carlo Caione <carlo@caione.org> Cc: Kevin Hilman <khilman@baylibre.com> Cc: linux-amlogic@lists.infradead.org Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
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Revision tags: v4.18.7, v4.18.6, v4.18.5, v4.17.18, v4.18.4, v4.18.3, v4.17.17, v4.18.2, v4.17.16, v4.17.15, v4.18.1, v4.18, v4.17.14, v4.17.13, v4.17.12, v4.17.11, v4.17.10, v4.17.9, v4.17.8, v4.17.7, v4.17.6, v4.17.5, v4.17.4, v4.17.3, v4.17.2, v4.17.1, v4.17, v4.16 |
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#
9adda353 |
| 27-Mar-2018 |
Yixun Lan <yixun.lan@amlogic.com> |
ARM64: dts: meson: fix clock source of the pclk for UART_AO
>From the hardware perspective, the actual pclk of the AO uarts is the corresponding clkc_ao uart gate, not the main clock controller clk8
ARM64: dts: meson: fix clock source of the pclk for UART_AO
>From the hardware perspective, the actual pclk of the AO uarts is the corresponding clkc_ao uart gate, not the main clock controller clk81. This was not problem so far, because the uart_gate had the CLK_IGNORE_UNUSED flag, which kept the gate open.
We plan to remove the CLK_IGNORE_UNUSED flag in another patch, but before doing that, we need to fix the clock in the DTS file.
Signed-off-by: Yixun Lan <yixun.lan@amlogic.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
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#
098e5303 |
| 26-Apr-2018 |
Jerome Brunet <jbrunet@baylibre.com> |
ARM64: dts: meson: add MMC resets
Add reset lines to the mmc controllers of the meson gx and axg SoCs
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylib
ARM64: dts: meson: add MMC resets
Add reset lines to the mmc controllers of the meson gx and axg SoCs
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
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#
6f95c8cd |
| 15-Mar-2018 |
Jerome Brunet <jbrunet@baylibre.com> |
ARM64: dts: meson-gx: sysctrl is the parent of the clock controller
The parent of the meson-gx clock controller should be the hhi system controller, not the HIU bus. This way, the HHI register regio
ARM64: dts: meson-gx: sysctrl is the parent of the clock controller
The parent of the meson-gx clock controller should be the hhi system controller, not the HIU bus. This way, the HHI register region can be used safely by multiple drivers
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
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#
97ac0093 |
| 12-Mar-2018 |
Neil Armstrong <narmstrong@baylibre.com> |
ARM64: dts: meson: bump mali450 clk to 744MHz
The Mali-450 IP can run up to 744MHz, bump the frequency using the GP0 PLL clock.
Cc: Michal Lazo <michal.lazo@gmail.com> Signed-off-by: Neil Armstrong
ARM64: dts: meson: bump mali450 clk to 744MHz
The Mali-450 IP can run up to 744MHz, bump the frequency using the GP0 PLL clock.
Cc: Michal Lazo <michal.lazo@gmail.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
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114abfe1 |
| 27-Feb-2018 |
Neil Armstrong <narmstrong@baylibre.com> |
ARM64: dts: amlogic: Convert to new-style SPDX license identifiers
Move the SPDX-License-Identifier lines to the top and drop the license splat.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.c
ARM64: dts: amlogic: Convert to new-style SPDX license identifiers
Move the SPDX-License-Identifier lines to the top and drop the license splat.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
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Revision tags: v4.15 |
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39005e56 |
| 04-Dec-2017 |
Neil Armstrong <narmstrong@baylibre.com> |
ARM64: dts: meson-gx: fix UART pclk clock name
The clock-names for pclk was wrongly set to "core", but the bindings specifies "pclk". This was not cathed until the legacy non-documented bindings wer
ARM64: dts: meson-gx: fix UART pclk clock name
The clock-names for pclk was wrongly set to "core", but the bindings specifies "pclk". This was not cathed until the legacy non-documented bindings were removed.
Reported-by: Andreas Färber <afaerber@suse.de> Fixes: f72d6f6037b7 ("ARM64: dts: meson-gx: use stable UART bindings with correct gate clock") Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
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Revision tags: v4.13.16 |
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e102da49 |
| 16-Nov-2017 |
Xingyu Chen <xingyu.chen@amlogic.com> |
ARM64: dts: meson: drop "sana" clock from SAR ADC
The SAR ADC modules doesn't require The "sana" clock.
Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Singed-off-by: Xingyu Chen
ARM64: dts: meson: drop "sana" clock from SAR ADC
The SAR ADC modules doesn't require The "sana" clock.
Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Singed-off-by: Xingyu Chen <xingyu.chen@amlogic.com> Signed-off-by: Yixun Lan <yixun.lan@amlogic.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
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74d1c6e9 |
| 20-Nov-2017 |
Neil Armstrong <narmstrong@baylibre.com> |
ARM64: dts: meson-gx: add VPU power domain
This patch adds support for the VPU Power Domain nodes, and attaches the VPU power domain to the VPU node.
Signed-off-by: Neil Armstrong <narmstrong@bayli
ARM64: dts: meson-gx: add VPU power domain
This patch adds support for the VPU Power Domain nodes, and attaches the VPU power domain to the VPU node.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
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Revision tags: v4.14 |
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9dbb56ea |
| 19-Oct-2017 |
Jerome Brunet <jbrunet@baylibre.com> |
ARM64: dts: meson-gx: add gpio interrupt controller
Add gpio interrupt controller to Amlogic GX family SoCs
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Reviewed-by: Neil Armstrong <narmstro
ARM64: dts: meson-gx: add gpio interrupt controller
Add gpio interrupt controller to Amlogic GX family SoCs
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
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Revision tags: v4.13.5 |
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ab36be66 |
| 03-Oct-2017 |
Neil Armstrong <narmstrong@baylibre.com> |
ARM64: dts: meson-gxl: Take eMMC data strobe out of eMMC pins
Since the Data Strobe pin is optional, take it out of the default eMMC pins and add a separate entry.
Signed-off-by: Neil Armstrong <na
ARM64: dts: meson-gxl: Take eMMC data strobe out of eMMC pins
Since the Data Strobe pin is optional, take it out of the default eMMC pins and add a separate entry.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Tested-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
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