1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2016 Andreas Färber 4 */ 5 6#include "meson-gx.dtsi" 7#include <dt-bindings/gpio/meson-gxbb-gpio.h> 8#include <dt-bindings/reset/amlogic,meson-gxbb-reset.h> 9#include <dt-bindings/clock/gxbb-clkc.h> 10#include <dt-bindings/clock/gxbb-aoclkc.h> 11#include <dt-bindings/reset/gxbb-aoclkc.h> 12 13/ { 14 compatible = "amlogic,meson-gxbb"; 15 16 soc { 17 usb0_phy: phy@c0000000 { 18 compatible = "amlogic,meson-gxbb-usb2-phy"; 19 #phy-cells = <0>; 20 reg = <0x0 0xc0000000 0x0 0x20>; 21 resets = <&reset RESET_USB_OTG>; 22 clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB0>; 23 clock-names = "usb_general", "usb"; 24 status = "disabled"; 25 }; 26 27 usb1_phy: phy@c0000020 { 28 compatible = "amlogic,meson-gxbb-usb2-phy"; 29 #phy-cells = <0>; 30 reg = <0x0 0xc0000020 0x0 0x20>; 31 resets = <&reset RESET_USB_OTG>; 32 clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1>; 33 clock-names = "usb_general", "usb"; 34 status = "disabled"; 35 }; 36 37 usb0: usb@c9000000 { 38 compatible = "amlogic,meson-gxbb-usb", "snps,dwc2"; 39 reg = <0x0 0xc9000000 0x0 0x40000>; 40 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 41 clocks = <&clkc CLKID_USB0_DDR_BRIDGE>; 42 clock-names = "otg"; 43 phys = <&usb0_phy>; 44 phy-names = "usb2-phy"; 45 dr_mode = "host"; 46 status = "disabled"; 47 }; 48 49 usb1: usb@c9100000 { 50 compatible = "amlogic,meson-gxbb-usb", "snps,dwc2"; 51 reg = <0x0 0xc9100000 0x0 0x40000>; 52 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 53 clocks = <&clkc CLKID_USB1_DDR_BRIDGE>; 54 clock-names = "otg"; 55 phys = <&usb1_phy>; 56 phy-names = "usb2-phy"; 57 dr_mode = "host"; 58 status = "disabled"; 59 }; 60 }; 61}; 62 63&aobus { 64 pinctrl_aobus: pinctrl@14 { 65 compatible = "amlogic,meson-gxbb-aobus-pinctrl"; 66 #address-cells = <2>; 67 #size-cells = <2>; 68 ranges; 69 70 gpio_ao: bank@14 { 71 reg = <0x0 0x00014 0x0 0x8>, 72 <0x0 0x0002c 0x0 0x4>, 73 <0x0 0x00024 0x0 0x8>; 74 reg-names = "mux", "pull", "gpio"; 75 gpio-controller; 76 #gpio-cells = <2>; 77 gpio-ranges = <&pinctrl_aobus 0 0 14>; 78 }; 79 80 uart_ao_a_pins: uart_ao_a { 81 mux { 82 groups = "uart_tx_ao_a", "uart_rx_ao_a"; 83 function = "uart_ao"; 84 bias-disable; 85 }; 86 }; 87 88 uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts { 89 mux { 90 groups = "uart_cts_ao_a", 91 "uart_rts_ao_a"; 92 function = "uart_ao"; 93 bias-disable; 94 }; 95 }; 96 97 uart_ao_b_pins: uart_ao_b { 98 mux { 99 groups = "uart_tx_ao_b", "uart_rx_ao_b"; 100 function = "uart_ao_b"; 101 bias-disable; 102 }; 103 }; 104 105 uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts { 106 mux { 107 groups = "uart_cts_ao_b", 108 "uart_rts_ao_b"; 109 function = "uart_ao_b"; 110 bias-disable; 111 }; 112 }; 113 114 remote_input_ao_pins: remote_input_ao { 115 mux { 116 groups = "remote_input_ao"; 117 function = "remote_input_ao"; 118 bias-disable; 119 }; 120 }; 121 122 i2c_ao_pins: i2c_ao { 123 mux { 124 groups = "i2c_sck_ao", 125 "i2c_sda_ao"; 126 function = "i2c_ao"; 127 bias-disable; 128 }; 129 }; 130 131 pwm_ao_a_3_pins: pwm_ao_a_3 { 132 mux { 133 groups = "pwm_ao_a_3"; 134 function = "pwm_ao_a_3"; 135 bias-disable; 136 }; 137 }; 138 139 pwm_ao_a_6_pins: pwm_ao_a_6 { 140 mux { 141 groups = "pwm_ao_a_6"; 142 function = "pwm_ao_a_6"; 143 bias-disable; 144 }; 145 }; 146 147 pwm_ao_a_12_pins: pwm_ao_a_12 { 148 mux { 149 groups = "pwm_ao_a_12"; 150 function = "pwm_ao_a_12"; 151 bias-disable; 152 }; 153 }; 154 155 pwm_ao_b_pins: pwm_ao_b { 156 mux { 157 groups = "pwm_ao_b"; 158 function = "pwm_ao_b"; 159 bias-disable; 160 }; 161 }; 162 163 i2s_am_clk_pins: i2s_am_clk { 164 mux { 165 groups = "i2s_am_clk"; 166 function = "i2s_out_ao"; 167 bias-disable; 168 }; 169 }; 170 171 i2s_out_ao_clk_pins: i2s_out_ao_clk { 172 mux { 173 groups = "i2s_out_ao_clk"; 174 function = "i2s_out_ao"; 175 bias-disable; 176 }; 177 }; 178 179 i2s_out_lr_clk_pins: i2s_out_lr_clk { 180 mux { 181 groups = "i2s_out_lr_clk"; 182 function = "i2s_out_ao"; 183 bias-disable; 184 }; 185 }; 186 187 i2s_out_ch01_ao_pins: i2s_out_ch01_ao { 188 mux { 189 groups = "i2s_out_ch01_ao"; 190 function = "i2s_out_ao"; 191 bias-disable; 192 }; 193 }; 194 195 i2s_out_ch23_ao_pins: i2s_out_ch23_ao { 196 mux { 197 groups = "i2s_out_ch23_ao"; 198 function = "i2s_out_ao"; 199 bias-disable; 200 }; 201 }; 202 203 i2s_out_ch45_ao_pins: i2s_out_ch45_ao { 204 mux { 205 groups = "i2s_out_ch45_ao"; 206 function = "i2s_out_ao"; 207 bias-disable; 208 }; 209 }; 210 211 spdif_out_ao_6_pins: spdif_out_ao_6 { 212 mux { 213 groups = "spdif_out_ao_6"; 214 function = "spdif_out_ao"; 215 }; 216 }; 217 218 spdif_out_ao_13_pins: spdif_out_ao_13 { 219 mux { 220 groups = "spdif_out_ao_13"; 221 function = "spdif_out_ao"; 222 bias-disable; 223 }; 224 }; 225 226 ao_cec_pins: ao_cec { 227 mux { 228 groups = "ao_cec"; 229 function = "cec_ao"; 230 bias-disable; 231 }; 232 }; 233 234 ee_cec_pins: ee_cec { 235 mux { 236 groups = "ee_cec"; 237 function = "cec_ao"; 238 bias-disable; 239 }; 240 }; 241 }; 242}; 243 244&apb { 245 mali: gpu@c0000 { 246 compatible = "amlogic,meson-gxbb-mali", "arm,mali-450"; 247 reg = <0x0 0xc0000 0x0 0x40000>; 248 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 249 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, 250 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, 251 <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 252 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, 253 <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, 254 <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, 255 <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, 256 <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, 257 <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; 258 interrupt-names = "gp", "gpmmu", "pp", "pmu", 259 "pp0", "ppmmu0", "pp1", "ppmmu1", 260 "pp2", "ppmmu2"; 261 clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>; 262 clock-names = "bus", "core"; 263 264 /* 265 * Mali clocking is provided by two identical clock paths 266 * MALI_0 and MALI_1 muxed to a single clock by a glitch 267 * free mux to safely change frequency while running. 268 */ 269 assigned-clocks = <&clkc CLKID_GP0_PLL>, 270 <&clkc CLKID_MALI_0_SEL>, 271 <&clkc CLKID_MALI_0>, 272 <&clkc CLKID_MALI>; /* Glitch free mux */ 273 assigned-clock-parents = <0>, /* Do Nothing */ 274 <&clkc CLKID_GP0_PLL>, 275 <0>, /* Do Nothing */ 276 <&clkc CLKID_MALI_0>; 277 assigned-clock-rates = <744000000>, 278 <0>, /* Do Nothing */ 279 <744000000>, 280 <0>; /* Do Nothing */ 281 }; 282}; 283 284&cbus { 285 spifc: spi@8c80 { 286 compatible = "amlogic,meson-gxbb-spifc"; 287 reg = <0x0 0x08c80 0x0 0x80>; 288 #address-cells = <1>; 289 #size-cells = <0>; 290 clocks = <&clkc CLKID_SPI>; 291 status = "disabled"; 292 }; 293}; 294 295&cec_AO { 296 clocks = <&clkc_AO CLKID_AO_CEC_32K>; 297 clock-names = "core"; 298}; 299 300&clkc_AO { 301 compatible = "amlogic,meson-gxbb-aoclkc", "amlogic,meson-gx-aoclkc"; 302}; 303 304&efuse { 305 clocks = <&clkc CLKID_EFUSE>; 306}; 307 308ðmac { 309 clocks = <&clkc CLKID_ETH>, 310 <&clkc CLKID_FCLK_DIV2>, 311 <&clkc CLKID_MPLL2>; 312 clock-names = "stmmaceth", "clkin0", "clkin1"; 313}; 314 315&gpio_intc { 316 compatible = "amlogic,meson-gpio-intc", 317 "amlogic,meson-gxbb-gpio-intc"; 318 status = "okay"; 319}; 320 321&hdmi_tx { 322 compatible = "amlogic,meson-gxbb-dw-hdmi", "amlogic,meson-gx-dw-hdmi"; 323 resets = <&reset RESET_HDMITX_CAPB3>, 324 <&reset RESET_HDMI_SYSTEM_RESET>, 325 <&reset RESET_HDMI_TX>; 326 reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy"; 327 clocks = <&clkc CLKID_HDMI_PCLK>, 328 <&clkc CLKID_CLK81>, 329 <&clkc CLKID_GCLK_VENCI_INT0>; 330 clock-names = "isfr", "iahb", "venci"; 331}; 332 333&sysctrl { 334 clkc: clock-controller { 335 compatible = "amlogic,gxbb-clkc"; 336 #clock-cells = <1>; 337 }; 338}; 339 340&hwrng { 341 clocks = <&clkc CLKID_RNG0>; 342 clock-names = "core"; 343}; 344 345&i2c_A { 346 clocks = <&clkc CLKID_I2C>; 347}; 348 349&i2c_AO { 350 clocks = <&clkc CLKID_AO_I2C>; 351}; 352 353&i2c_B { 354 clocks = <&clkc CLKID_I2C>; 355}; 356 357&i2c_C { 358 clocks = <&clkc CLKID_I2C>; 359}; 360 361&periphs { 362 pinctrl_periphs: pinctrl@4b0 { 363 compatible = "amlogic,meson-gxbb-periphs-pinctrl"; 364 #address-cells = <2>; 365 #size-cells = <2>; 366 ranges; 367 368 gpio: bank@4b0 { 369 reg = <0x0 0x004b0 0x0 0x28>, 370 <0x0 0x004e8 0x0 0x14>, 371 <0x0 0x00520 0x0 0x14>, 372 <0x0 0x00430 0x0 0x40>; 373 reg-names = "mux", "pull", "pull-enable", "gpio"; 374 gpio-controller; 375 #gpio-cells = <2>; 376 gpio-ranges = <&pinctrl_periphs 0 0 119>; 377 }; 378 379 emmc_pins: emmc { 380 mux { 381 groups = "emmc_nand_d07", 382 "emmc_cmd", 383 "emmc_clk"; 384 function = "emmc"; 385 bias-disable; 386 }; 387 }; 388 389 emmc_ds_pins: emmc-ds { 390 mux { 391 groups = "emmc_ds"; 392 function = "emmc"; 393 bias-disable; 394 }; 395 }; 396 397 emmc_clk_gate_pins: emmc_clk_gate { 398 mux { 399 groups = "BOOT_8"; 400 function = "gpio_periphs"; 401 bias-pull-down; 402 }; 403 }; 404 405 nor_pins: nor { 406 mux { 407 groups = "nor_d", 408 "nor_q", 409 "nor_c", 410 "nor_cs"; 411 function = "nor"; 412 bias-disable; 413 }; 414 }; 415 416 spi_pins: spi-pins { 417 mux { 418 groups = "spi_miso", 419 "spi_mosi", 420 "spi_sclk"; 421 function = "spi"; 422 bias-disable; 423 }; 424 }; 425 426 spi_ss0_pins: spi-ss0 { 427 mux { 428 groups = "spi_ss0"; 429 function = "spi"; 430 bias-disable; 431 }; 432 }; 433 434 sdcard_pins: sdcard { 435 mux { 436 groups = "sdcard_d0", 437 "sdcard_d1", 438 "sdcard_d2", 439 "sdcard_d3", 440 "sdcard_cmd", 441 "sdcard_clk"; 442 function = "sdcard"; 443 bias-disable; 444 }; 445 }; 446 447 sdcard_clk_gate_pins: sdcard_clk_gate { 448 mux { 449 groups = "CARD_2"; 450 function = "gpio_periphs"; 451 bias-pull-down; 452 }; 453 }; 454 455 sdio_pins: sdio { 456 mux { 457 groups = "sdio_d0", 458 "sdio_d1", 459 "sdio_d2", 460 "sdio_d3", 461 "sdio_cmd", 462 "sdio_clk"; 463 function = "sdio"; 464 bias-disable; 465 }; 466 }; 467 468 sdio_clk_gate_pins: sdio_clk_gate { 469 mux { 470 groups = "GPIOX_4"; 471 function = "gpio_periphs"; 472 bias-pull-down; 473 }; 474 }; 475 476 sdio_irq_pins: sdio_irq { 477 mux { 478 groups = "sdio_irq"; 479 function = "sdio"; 480 bias-disable; 481 }; 482 }; 483 484 uart_a_pins: uart_a { 485 mux { 486 groups = "uart_tx_a", 487 "uart_rx_a"; 488 function = "uart_a"; 489 bias-disable; 490 }; 491 }; 492 493 uart_a_cts_rts_pins: uart_a_cts_rts { 494 mux { 495 groups = "uart_cts_a", 496 "uart_rts_a"; 497 function = "uart_a"; 498 bias-disable; 499 }; 500 }; 501 502 uart_b_pins: uart_b { 503 mux { 504 groups = "uart_tx_b", 505 "uart_rx_b"; 506 function = "uart_b"; 507 bias-disable; 508 }; 509 }; 510 511 uart_b_cts_rts_pins: uart_b_cts_rts { 512 mux { 513 groups = "uart_cts_b", 514 "uart_rts_b"; 515 function = "uart_b"; 516 bias-disable; 517 }; 518 }; 519 520 uart_c_pins: uart_c { 521 mux { 522 groups = "uart_tx_c", 523 "uart_rx_c"; 524 function = "uart_c"; 525 bias-disable; 526 }; 527 }; 528 529 uart_c_cts_rts_pins: uart_c_cts_rts { 530 mux { 531 groups = "uart_cts_c", 532 "uart_rts_c"; 533 function = "uart_c"; 534 bias-disable; 535 }; 536 }; 537 538 i2c_a_pins: i2c_a { 539 mux { 540 groups = "i2c_sck_a", 541 "i2c_sda_a"; 542 function = "i2c_a"; 543 bias-disable; 544 }; 545 }; 546 547 i2c_b_pins: i2c_b { 548 mux { 549 groups = "i2c_sck_b", 550 "i2c_sda_b"; 551 function = "i2c_b"; 552 bias-disable; 553 }; 554 }; 555 556 i2c_c_pins: i2c_c { 557 mux { 558 groups = "i2c_sck_c", 559 "i2c_sda_c"; 560 function = "i2c_c"; 561 bias-disable; 562 }; 563 }; 564 565 eth_rgmii_pins: eth-rgmii { 566 mux { 567 groups = "eth_mdio", 568 "eth_mdc", 569 "eth_clk_rx_clk", 570 "eth_rx_dv", 571 "eth_rxd0", 572 "eth_rxd1", 573 "eth_rxd2", 574 "eth_rxd3", 575 "eth_rgmii_tx_clk", 576 "eth_tx_en", 577 "eth_txd0", 578 "eth_txd1", 579 "eth_txd2", 580 "eth_txd3"; 581 function = "eth"; 582 bias-disable; 583 }; 584 }; 585 586 eth_rmii_pins: eth-rmii { 587 mux { 588 groups = "eth_mdio", 589 "eth_mdc", 590 "eth_clk_rx_clk", 591 "eth_rx_dv", 592 "eth_rxd0", 593 "eth_rxd1", 594 "eth_tx_en", 595 "eth_txd0", 596 "eth_txd1"; 597 function = "eth"; 598 bias-disable; 599 }; 600 }; 601 602 pwm_a_x_pins: pwm_a_x { 603 mux { 604 groups = "pwm_a_x"; 605 function = "pwm_a_x"; 606 bias-disable; 607 }; 608 }; 609 610 pwm_a_y_pins: pwm_a_y { 611 mux { 612 groups = "pwm_a_y"; 613 function = "pwm_a_y"; 614 bias-disable; 615 }; 616 }; 617 618 pwm_b_pins: pwm_b { 619 mux { 620 groups = "pwm_b"; 621 function = "pwm_b"; 622 bias-disable; 623 }; 624 }; 625 626 pwm_d_pins: pwm_d { 627 mux { 628 groups = "pwm_d"; 629 function = "pwm_d"; 630 bias-disable; 631 }; 632 }; 633 634 pwm_e_pins: pwm_e { 635 mux { 636 groups = "pwm_e"; 637 function = "pwm_e"; 638 bias-disable; 639 }; 640 }; 641 642 pwm_f_x_pins: pwm_f_x { 643 mux { 644 groups = "pwm_f_x"; 645 function = "pwm_f_x"; 646 bias-disable; 647 }; 648 }; 649 650 pwm_f_y_pins: pwm_f_y { 651 mux { 652 groups = "pwm_f_y"; 653 function = "pwm_f_y"; 654 bias-disable; 655 }; 656 }; 657 658 hdmi_hpd_pins: hdmi_hpd { 659 mux { 660 groups = "hdmi_hpd"; 661 function = "hdmi_hpd"; 662 bias-disable; 663 }; 664 }; 665 666 hdmi_i2c_pins: hdmi_i2c { 667 mux { 668 groups = "hdmi_sda", "hdmi_scl"; 669 function = "hdmi_i2c"; 670 bias-disable; 671 }; 672 }; 673 674 i2sout_ch23_y_pins: i2sout_ch23_y { 675 mux { 676 groups = "i2sout_ch23_y"; 677 function = "i2s_out"; 678 bias-disable; 679 }; 680 }; 681 682 i2sout_ch45_y_pins: i2sout_ch45_y { 683 mux { 684 groups = "i2sout_ch45_y"; 685 function = "i2s_out"; 686 bias-disable; 687 }; 688 }; 689 690 i2sout_ch67_y_pins: i2sout_ch67_y { 691 mux { 692 groups = "i2sout_ch67_y"; 693 function = "i2s_out"; 694 bias-disable; 695 }; 696 }; 697 698 spdif_out_y_pins: spdif_out_y { 699 mux { 700 groups = "spdif_out_y"; 701 function = "spdif_out"; 702 bias-disable; 703 }; 704 }; 705 }; 706}; 707 708&pwrc_vpu { 709 resets = <&reset RESET_VIU>, 710 <&reset RESET_VENC>, 711 <&reset RESET_VCBUS>, 712 <&reset RESET_BT656>, 713 <&reset RESET_DVIN_RESET>, 714 <&reset RESET_RDMA>, 715 <&reset RESET_VENCI>, 716 <&reset RESET_VENCP>, 717 <&reset RESET_VDAC>, 718 <&reset RESET_VDI6>, 719 <&reset RESET_VENCL>, 720 <&reset RESET_VID_LOCK>; 721 clocks = <&clkc CLKID_VPU>, 722 <&clkc CLKID_VAPB>; 723 clock-names = "vpu", "vapb"; 724 /* 725 * VPU clocking is provided by two identical clock paths 726 * VPU_0 and VPU_1 muxed to a single clock by a glitch 727 * free mux to safely change frequency while running. 728 * Same for VAPB but with a final gate after the glitch free mux. 729 */ 730 assigned-clocks = <&clkc CLKID_VPU_0_SEL>, 731 <&clkc CLKID_VPU_0>, 732 <&clkc CLKID_VPU>, /* Glitch free mux */ 733 <&clkc CLKID_VAPB_0_SEL>, 734 <&clkc CLKID_VAPB_0>, 735 <&clkc CLKID_VAPB_SEL>; /* Glitch free mux */ 736 assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>, 737 <0>, /* Do Nothing */ 738 <&clkc CLKID_VPU_0>, 739 <&clkc CLKID_FCLK_DIV4>, 740 <0>, /* Do Nothing */ 741 <&clkc CLKID_VAPB_0>; 742 assigned-clock-rates = <0>, /* Do Nothing */ 743 <666666666>, 744 <0>, /* Do Nothing */ 745 <0>, /* Do Nothing */ 746 <250000000>, 747 <0>; /* Do Nothing */ 748}; 749 750&saradc { 751 compatible = "amlogic,meson-gxbb-saradc", "amlogic,meson-saradc"; 752 clocks = <&xtal>, 753 <&clkc CLKID_SAR_ADC>, 754 <&clkc CLKID_SAR_ADC_CLK>, 755 <&clkc CLKID_SAR_ADC_SEL>; 756 clock-names = "clkin", "core", "adc_clk", "adc_sel"; 757}; 758 759&sd_emmc_a { 760 clocks = <&clkc CLKID_SD_EMMC_A>, 761 <&clkc CLKID_SD_EMMC_A_CLK0>, 762 <&clkc CLKID_FCLK_DIV2>; 763 clock-names = "core", "clkin0", "clkin1"; 764 resets = <&reset RESET_SD_EMMC_A>; 765}; 766 767&sd_emmc_b { 768 clocks = <&clkc CLKID_SD_EMMC_B>, 769 <&clkc CLKID_SD_EMMC_B_CLK0>, 770 <&clkc CLKID_FCLK_DIV2>; 771 clock-names = "core", "clkin0", "clkin1"; 772 resets = <&reset RESET_SD_EMMC_B>; 773}; 774 775&sd_emmc_c { 776 clocks = <&clkc CLKID_SD_EMMC_C>, 777 <&clkc CLKID_SD_EMMC_C_CLK0>, 778 <&clkc CLKID_FCLK_DIV2>; 779 clock-names = "core", "clkin0", "clkin1"; 780 resets = <&reset RESET_SD_EMMC_C>; 781}; 782 783&spicc { 784 clocks = <&clkc CLKID_SPICC>; 785 clock-names = "core"; 786 resets = <&reset RESET_PERIPHS_SPICC>; 787 num-cs = <1>; 788}; 789 790&spifc { 791 clocks = <&clkc CLKID_SPI>; 792}; 793 794&uart_A { 795 clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>; 796 clock-names = "xtal", "pclk", "baud"; 797}; 798 799&uart_AO { 800 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART1>, <&xtal>; 801 clock-names = "xtal", "pclk", "baud"; 802}; 803 804&uart_AO_B { 805 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>; 806 clock-names = "xtal", "pclk", "baud"; 807}; 808 809&uart_B { 810 clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>; 811 clock-names = "xtal", "pclk", "baud"; 812}; 813 814&uart_C { 815 clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>; 816 clock-names = "xtal", "pclk", "baud"; 817}; 818 819&vpu { 820 compatible = "amlogic,meson-gxbb-vpu", "amlogic,meson-gx-vpu"; 821 power-domains = <&pwrc_vpu>; 822}; 823