1/*
2 * Copyright (c) 2016 Andreas Färber
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 *  a) This library is free software; you can redistribute it and/or
10 *     modify it under the terms of the GNU General Public License as
11 *     published by the Free Software Foundation; either version 2 of the
12 *     License, or (at your option) any later version.
13 *
14 *     This library is distributed in the hope that it will be useful,
15 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
16 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17 *     GNU General Public License for more details.
18 *
19 * Or, alternatively,
20 *
21 *  b) Permission is hereby granted, free of charge, to any person
22 *     obtaining a copy of this software and associated documentation
23 *     files (the "Software"), to deal in the Software without
24 *     restriction, including without limitation the rights to use,
25 *     copy, modify, merge, publish, distribute, sublicense, and/or
26 *     sell copies of the Software, and to permit persons to whom the
27 *     Software is furnished to do so, subject to the following
28 *     conditions:
29 *
30 *     The above copyright notice and this permission notice shall be
31 *     included in all copies or substantial portions of the Software.
32 *
33 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 *     OTHER DEALINGS IN THE SOFTWARE.
41 */
42
43#include "meson-gx.dtsi"
44#include <dt-bindings/gpio/meson-gxbb-gpio.h>
45#include <dt-bindings/reset/amlogic,meson-gxbb-reset.h>
46#include <dt-bindings/clock/gxbb-clkc.h>
47#include <dt-bindings/clock/gxbb-aoclkc.h>
48#include <dt-bindings/reset/gxbb-aoclkc.h>
49
50/ {
51	compatible = "amlogic,meson-gxbb";
52
53	soc {
54		usb0_phy: phy@c0000000 {
55			compatible = "amlogic,meson-gxbb-usb2-phy";
56			#phy-cells = <0>;
57			reg = <0x0 0xc0000000 0x0 0x20>;
58			resets = <&reset RESET_USB_OTG>;
59			clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB0>;
60			clock-names = "usb_general", "usb";
61			status = "disabled";
62		};
63
64		usb1_phy: phy@c0000020 {
65			compatible = "amlogic,meson-gxbb-usb2-phy";
66			#phy-cells = <0>;
67			reg = <0x0 0xc0000020 0x0 0x20>;
68			resets = <&reset RESET_USB_OTG>;
69			clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1>;
70			clock-names = "usb_general", "usb";
71			status = "disabled";
72		};
73
74		usb0: usb@c9000000 {
75			compatible = "amlogic,meson-gxbb-usb", "snps,dwc2";
76			reg = <0x0 0xc9000000 0x0 0x40000>;
77			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
78			clocks = <&clkc CLKID_USB0_DDR_BRIDGE>;
79			clock-names = "otg";
80			phys = <&usb0_phy>;
81			phy-names = "usb2-phy";
82			dr_mode = "host";
83			status = "disabled";
84		};
85
86		usb1: usb@c9100000 {
87			compatible = "amlogic,meson-gxbb-usb", "snps,dwc2";
88			reg = <0x0 0xc9100000 0x0 0x40000>;
89			interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
90			clocks = <&clkc CLKID_USB1_DDR_BRIDGE>;
91			clock-names = "otg";
92			phys = <&usb1_phy>;
93			phy-names = "usb2-phy";
94			dr_mode = "host";
95			status = "disabled";
96		};
97	};
98};
99
100&aobus {
101	pinctrl_aobus: pinctrl@14 {
102		compatible = "amlogic,meson-gxbb-aobus-pinctrl";
103		#address-cells = <2>;
104		#size-cells = <2>;
105		ranges;
106
107		gpio_ao: bank@14 {
108			reg = <0x0 0x00014 0x0 0x8>,
109			      <0x0 0x0002c 0x0 0x4>,
110			      <0x0 0x00024 0x0 0x8>;
111			reg-names = "mux", "pull", "gpio";
112			gpio-controller;
113			#gpio-cells = <2>;
114			gpio-ranges = <&pinctrl_aobus 0 0 14>;
115		};
116
117		uart_ao_a_pins: uart_ao_a {
118			mux {
119				groups = "uart_tx_ao_a", "uart_rx_ao_a";
120				function = "uart_ao";
121			};
122		};
123
124		uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts {
125			mux {
126				groups = "uart_cts_ao_a",
127				       "uart_rts_ao_a";
128				function = "uart_ao";
129			};
130		};
131
132		uart_ao_b_pins: uart_ao_b {
133			mux {
134				groups = "uart_tx_ao_b", "uart_rx_ao_b";
135				function = "uart_ao_b";
136			};
137		};
138
139		uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts {
140			mux {
141				groups = "uart_cts_ao_b",
142				       "uart_rts_ao_b";
143				function = "uart_ao_b";
144			};
145		};
146
147		remote_input_ao_pins: remote_input_ao {
148			mux {
149				groups = "remote_input_ao";
150				function = "remote_input_ao";
151			};
152		};
153
154		i2c_ao_pins: i2c_ao {
155			mux {
156				groups = "i2c_sck_ao",
157				       "i2c_sda_ao";
158				function = "i2c_ao";
159			};
160		};
161
162		pwm_ao_a_3_pins: pwm_ao_a_3 {
163			mux {
164				groups = "pwm_ao_a_3";
165				function = "pwm_ao_a_3";
166			};
167		};
168
169		pwm_ao_a_6_pins: pwm_ao_a_6 {
170			mux {
171				groups = "pwm_ao_a_6";
172				function = "pwm_ao_a_6";
173			};
174		};
175
176		pwm_ao_a_12_pins: pwm_ao_a_12 {
177			mux {
178				groups = "pwm_ao_a_12";
179				function = "pwm_ao_a_12";
180			};
181		};
182
183		pwm_ao_b_pins: pwm_ao_b {
184			mux {
185				groups = "pwm_ao_b";
186				function = "pwm_ao_b";
187			};
188		};
189
190		i2s_am_clk_pins: i2s_am_clk {
191			mux {
192				groups = "i2s_am_clk";
193				function = "i2s_out_ao";
194			};
195		};
196
197		i2s_out_ao_clk_pins: i2s_out_ao_clk {
198			mux {
199				groups = "i2s_out_ao_clk";
200				function = "i2s_out_ao";
201			};
202		};
203
204		i2s_out_lr_clk_pins: i2s_out_lr_clk {
205			mux {
206				groups = "i2s_out_lr_clk";
207				function = "i2s_out_ao";
208			};
209		};
210
211		i2s_out_ch01_ao_pins: i2s_out_ch01_ao {
212			mux {
213				groups = "i2s_out_ch01_ao";
214				function = "i2s_out_ao";
215			};
216		};
217
218		i2s_out_ch23_ao_pins: i2s_out_ch23_ao {
219			mux {
220				groups = "i2s_out_ch23_ao";
221				function = "i2s_out_ao";
222			};
223		};
224
225		i2s_out_ch45_ao_pins: i2s_out_ch45_ao {
226			mux {
227				groups = "i2s_out_ch45_ao";
228				function = "i2s_out_ao";
229			};
230		};
231
232		spdif_out_ao_6_pins: spdif_out_ao_6 {
233			mux {
234				groups = "spdif_out_ao_6";
235				function = "spdif_out_ao";
236			};
237		};
238
239		spdif_out_ao_13_pins: spdif_out_ao_13 {
240			mux {
241				groups = "spdif_out_ao_13";
242				function = "spdif_out_ao";
243			};
244		};
245
246		ao_cec_pins: ao_cec {
247			mux {
248				groups = "ao_cec";
249				function = "cec_ao";
250			};
251		};
252
253		ee_cec_pins: ee_cec {
254			mux {
255				groups = "ee_cec";
256				function = "cec_ao";
257			};
258		};
259	};
260};
261
262&apb {
263	mali: gpu@c0000 {
264		compatible = "amlogic,meson-gxbb-mali", "arm,mali-450";
265		reg = <0x0 0xc0000 0x0 0x40000>;
266		interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
267			     <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
268			     <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
269			     <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
270			     <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
271			     <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
272			     <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
273			     <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
274			     <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
275			     <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
276		interrupt-names = "gp", "gpmmu", "pp", "pmu",
277			"pp0", "ppmmu0", "pp1", "ppmmu1",
278			"pp2", "ppmmu2";
279		clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>;
280		clock-names = "bus", "core";
281
282		/*
283		 * Mali clocking is provided by two identical clock paths
284		 * MALI_0 and MALI_1 muxed to a single clock by a glitch
285		 * free mux to safely change frequency while running.
286		 */
287		assigned-clocks = <&clkc CLKID_MALI_0_SEL>,
288				  <&clkc CLKID_MALI_0>,
289				  <&clkc CLKID_MALI>; /* Glitch free mux */
290		assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
291					 <0>, /* Do Nothing */
292					 <&clkc CLKID_MALI_0>;
293		assigned-clock-rates = <0>, /* Do Nothing */
294				       <666666666>,
295				       <0>; /* Do Nothing */
296	};
297};
298
299&cbus {
300	spifc: spi@8c80 {
301		compatible = "amlogic,meson-gxbb-spifc";
302		reg = <0x0 0x08c80 0x0 0x80>;
303		#address-cells = <1>;
304		#size-cells = <0>;
305		clocks = <&clkc CLKID_SPI>;
306		status = "disabled";
307	};
308};
309
310&cec_AO {
311	clocks = <&clkc_AO CLKID_AO_CEC_32K>;
312	clock-names = "core";
313};
314
315&clkc_AO {
316	compatible = "amlogic,meson-gxbb-aoclkc", "amlogic,meson-gx-aoclkc";
317};
318
319&ethmac {
320	clocks = <&clkc CLKID_ETH>,
321		 <&clkc CLKID_FCLK_DIV2>,
322		 <&clkc CLKID_MPLL2>;
323	clock-names = "stmmaceth", "clkin0", "clkin1";
324};
325
326&gpio_intc {
327	compatible = "amlogic,meson-gpio-intc",
328		     "amlogic,meson-gxbb-gpio-intc";
329	status = "okay";
330};
331
332&hdmi_tx {
333	compatible = "amlogic,meson-gxbb-dw-hdmi", "amlogic,meson-gx-dw-hdmi";
334	resets = <&reset RESET_HDMITX_CAPB3>,
335		 <&reset RESET_HDMI_SYSTEM_RESET>,
336		 <&reset RESET_HDMI_TX>;
337	reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy";
338	clocks = <&clkc CLKID_HDMI_PCLK>,
339		 <&clkc CLKID_CLK81>,
340		 <&clkc CLKID_GCLK_VENCI_INT0>;
341	clock-names = "isfr", "iahb", "venci";
342};
343
344&hiubus {
345	clkc: clock-controller@0 {
346		compatible = "amlogic,gxbb-clkc";
347		#clock-cells = <1>;
348		reg = <0x0 0x0 0x0 0x3db>;
349	};
350};
351
352&hwrng {
353	clocks = <&clkc CLKID_RNG0>;
354	clock-names = "core";
355};
356
357&i2c_A {
358	clocks = <&clkc CLKID_I2C>;
359};
360
361&i2c_AO {
362	clocks = <&clkc CLKID_AO_I2C>;
363};
364
365&i2c_B {
366	clocks = <&clkc CLKID_I2C>;
367};
368
369&i2c_C {
370	clocks = <&clkc CLKID_I2C>;
371};
372
373&periphs {
374	pinctrl_periphs: pinctrl@4b0 {
375		compatible = "amlogic,meson-gxbb-periphs-pinctrl";
376		#address-cells = <2>;
377		#size-cells = <2>;
378		ranges;
379
380		gpio: bank@4b0 {
381			reg = <0x0 0x004b0 0x0 0x28>,
382			      <0x0 0x004e8 0x0 0x14>,
383			      <0x0 0x00520 0x0 0x14>,
384			      <0x0 0x00430 0x0 0x40>;
385			reg-names = "mux", "pull", "pull-enable", "gpio";
386			gpio-controller;
387			#gpio-cells = <2>;
388			gpio-ranges = <&pinctrl_periphs 0 0 119>;
389		};
390
391		emmc_pins: emmc {
392			mux {
393				groups = "emmc_nand_d07",
394				       "emmc_cmd",
395				       "emmc_clk";
396				function = "emmc";
397			};
398		};
399
400		emmc_ds_pins: emmc-ds {
401			mux {
402				groups = "emmc_ds";
403				function = "emmc";
404			};
405		};
406
407		emmc_clk_gate_pins: emmc_clk_gate {
408			mux {
409				groups = "BOOT_8";
410				function = "gpio_periphs";
411			};
412			cfg-pull-down {
413				pins = "BOOT_8";
414				bias-pull-down;
415			};
416		};
417
418		nor_pins: nor {
419			mux {
420				groups = "nor_d",
421				       "nor_q",
422				       "nor_c",
423				       "nor_cs";
424				function = "nor";
425			};
426		};
427
428		spi_pins: spi {
429			mux {
430				groups = "spi_miso",
431					"spi_mosi",
432					"spi_sclk";
433				function = "spi";
434			};
435		};
436
437		spi_ss0_pins: spi-ss0 {
438			mux {
439				groups = "spi_ss0";
440				function = "spi";
441			};
442		};
443
444		sdcard_pins: sdcard {
445			mux {
446				groups = "sdcard_d0",
447				       "sdcard_d1",
448				       "sdcard_d2",
449				       "sdcard_d3",
450				       "sdcard_cmd",
451				       "sdcard_clk";
452				function = "sdcard";
453			};
454		};
455
456		sdcard_clk_gate_pins: sdcard_clk_gate {
457			mux {
458				groups = "CARD_2";
459				function = "gpio_periphs";
460			};
461			cfg-pull-down {
462				pins = "CARD_2";
463				bias-pull-down;
464			};
465		};
466
467		sdio_pins: sdio {
468			mux {
469				groups = "sdio_d0",
470				       "sdio_d1",
471				       "sdio_d2",
472				       "sdio_d3",
473				       "sdio_cmd",
474				       "sdio_clk";
475				function = "sdio";
476			};
477		};
478
479		sdio_clk_gate_pins: sdio_clk_gate {
480			mux {
481				groups = "GPIOX_4";
482				function = "gpio_periphs";
483			};
484			cfg-pull-down {
485				pins = "GPIOX_4";
486				bias-pull-down;
487			};
488		};
489
490		sdio_irq_pins: sdio_irq {
491			mux {
492				groups = "sdio_irq";
493				function = "sdio";
494			};
495		};
496
497		uart_a_pins: uart_a {
498			mux {
499				groups = "uart_tx_a",
500				       "uart_rx_a";
501				function = "uart_a";
502			};
503		};
504
505		uart_a_cts_rts_pins: uart_a_cts_rts {
506			mux {
507				groups = "uart_cts_a",
508				       "uart_rts_a";
509				function = "uart_a";
510			};
511		};
512
513		uart_b_pins: uart_b {
514			mux {
515				groups = "uart_tx_b",
516				       "uart_rx_b";
517				function = "uart_b";
518			};
519		};
520
521		uart_b_cts_rts_pins: uart_b_cts_rts {
522			mux {
523				groups = "uart_cts_b",
524				       "uart_rts_b";
525				function = "uart_b";
526			};
527		};
528
529		uart_c_pins: uart_c {
530			mux {
531				groups = "uart_tx_c",
532				       "uart_rx_c";
533				function = "uart_c";
534			};
535		};
536
537		uart_c_cts_rts_pins: uart_c_cts_rts {
538			mux {
539				groups = "uart_cts_c",
540				       "uart_rts_c";
541				function = "uart_c";
542			};
543		};
544
545		i2c_a_pins: i2c_a {
546			mux {
547				groups = "i2c_sck_a",
548				       "i2c_sda_a";
549				function = "i2c_a";
550			};
551		};
552
553		i2c_b_pins: i2c_b {
554			mux {
555				groups = "i2c_sck_b",
556				       "i2c_sda_b";
557				function = "i2c_b";
558			};
559		};
560
561		i2c_c_pins: i2c_c {
562			mux {
563				groups = "i2c_sck_c",
564				       "i2c_sda_c";
565				function = "i2c_c";
566			};
567		};
568
569		eth_rgmii_pins: eth-rgmii {
570			mux {
571				groups = "eth_mdio",
572				       "eth_mdc",
573				       "eth_clk_rx_clk",
574				       "eth_rx_dv",
575				       "eth_rxd0",
576				       "eth_rxd1",
577				       "eth_rxd2",
578				       "eth_rxd3",
579				       "eth_rgmii_tx_clk",
580				       "eth_tx_en",
581				       "eth_txd0",
582				       "eth_txd1",
583				       "eth_txd2",
584				       "eth_txd3";
585				function = "eth";
586			};
587		};
588
589		eth_rmii_pins: eth-rmii {
590			mux {
591				groups = "eth_mdio",
592				       "eth_mdc",
593				       "eth_clk_rx_clk",
594				       "eth_rx_dv",
595				       "eth_rxd0",
596				       "eth_rxd1",
597				       "eth_tx_en",
598				       "eth_txd0",
599				       "eth_txd1";
600				function = "eth";
601			};
602		};
603
604		pwm_a_x_pins: pwm_a_x {
605			mux {
606				groups = "pwm_a_x";
607				function = "pwm_a_x";
608			};
609		};
610
611		pwm_a_y_pins: pwm_a_y {
612			mux {
613				groups = "pwm_a_y";
614				function = "pwm_a_y";
615			};
616		};
617
618		pwm_b_pins: pwm_b {
619			mux {
620				groups = "pwm_b";
621				function = "pwm_b";
622			};
623		};
624
625		pwm_d_pins: pwm_d {
626			mux {
627				groups = "pwm_d";
628				function = "pwm_d";
629			};
630		};
631
632		pwm_e_pins: pwm_e {
633			mux {
634				groups = "pwm_e";
635				function = "pwm_e";
636			};
637		};
638
639		pwm_f_x_pins: pwm_f_x {
640			mux {
641				groups = "pwm_f_x";
642				function = "pwm_f_x";
643			};
644		};
645
646		pwm_f_y_pins: pwm_f_y {
647			mux {
648				groups = "pwm_f_y";
649				function = "pwm_f_y";
650			};
651		};
652
653		hdmi_hpd_pins: hdmi_hpd {
654			mux {
655				groups = "hdmi_hpd";
656				function = "hdmi_hpd";
657			};
658		};
659
660		hdmi_i2c_pins: hdmi_i2c {
661			mux {
662				groups = "hdmi_sda", "hdmi_scl";
663				function = "hdmi_i2c";
664			};
665		};
666
667		i2sout_ch23_y_pins: i2sout_ch23_y {
668			mux {
669				groups = "i2sout_ch23_y";
670				function = "i2s_out";
671			};
672		};
673
674		i2sout_ch45_y_pins: i2sout_ch45_y {
675			mux {
676				groups = "i2sout_ch45_y";
677				function = "i2s_out";
678			};
679		};
680
681		i2sout_ch67_y_pins: i2sout_ch67_y {
682			mux {
683				groups = "i2sout_ch67_y";
684				function = "i2s_out";
685			};
686		};
687
688		spdif_out_y_pins: spdif_out_y {
689			mux {
690				groups = "spdif_out_y";
691				function = "spdif_out";
692			};
693		};
694	};
695};
696
697&pwrc_vpu {
698	resets = <&reset RESET_VIU>,
699		 <&reset RESET_VENC>,
700		 <&reset RESET_VCBUS>,
701		 <&reset RESET_BT656>,
702		 <&reset RESET_DVIN_RESET>,
703		 <&reset RESET_RDMA>,
704		 <&reset RESET_VENCI>,
705		 <&reset RESET_VENCP>,
706		 <&reset RESET_VDAC>,
707		 <&reset RESET_VDI6>,
708		 <&reset RESET_VENCL>,
709		 <&reset RESET_VID_LOCK>;
710	clocks = <&clkc CLKID_VPU>,
711	         <&clkc CLKID_VAPB>;
712	clock-names = "vpu", "vapb";
713	/*
714	 * VPU clocking is provided by two identical clock paths
715	 * VPU_0 and VPU_1 muxed to a single clock by a glitch
716	 * free mux to safely change frequency while running.
717	 * Same for VAPB but with a final gate after the glitch free mux.
718	 */
719	assigned-clocks = <&clkc CLKID_VPU_0_SEL>,
720			  <&clkc CLKID_VPU_0>,
721			  <&clkc CLKID_VPU>, /* Glitch free mux */
722			  <&clkc CLKID_VAPB_0_SEL>,
723			  <&clkc CLKID_VAPB_0>,
724			  <&clkc CLKID_VAPB_SEL>; /* Glitch free mux */
725	assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
726				 <0>, /* Do Nothing */
727				 <&clkc CLKID_VPU_0>,
728				 <&clkc CLKID_FCLK_DIV4>,
729				 <0>, /* Do Nothing */
730				 <&clkc CLKID_VAPB_0>;
731	assigned-clock-rates = <0>, /* Do Nothing */
732			       <666666666>,
733			       <0>, /* Do Nothing */
734			       <0>, /* Do Nothing */
735			       <250000000>,
736			       <0>; /* Do Nothing */
737};
738
739&saradc {
740	compatible = "amlogic,meson-gxbb-saradc", "amlogic,meson-saradc";
741	clocks = <&xtal>,
742		 <&clkc CLKID_SAR_ADC>,
743		 <&clkc CLKID_SANA>,
744		 <&clkc CLKID_SAR_ADC_CLK>,
745		 <&clkc CLKID_SAR_ADC_SEL>;
746	clock-names = "clkin", "core", "sana", "adc_clk", "adc_sel";
747};
748
749&sd_emmc_a {
750	clocks = <&clkc CLKID_SD_EMMC_A>,
751		 <&clkc CLKID_SD_EMMC_A_CLK0>,
752		 <&clkc CLKID_FCLK_DIV2>;
753	clock-names = "core", "clkin0", "clkin1";
754};
755
756&sd_emmc_b {
757	clocks = <&clkc CLKID_SD_EMMC_B>,
758		 <&clkc CLKID_SD_EMMC_B_CLK0>,
759		 <&clkc CLKID_FCLK_DIV2>;
760	clock-names = "core", "clkin0", "clkin1";
761};
762
763&sd_emmc_c {
764	clocks = <&clkc CLKID_SD_EMMC_C>,
765		 <&clkc CLKID_SD_EMMC_C_CLK0>,
766		 <&clkc CLKID_FCLK_DIV2>;
767	clock-names = "core", "clkin0", "clkin1";
768};
769
770&spicc {
771	clocks = <&clkc CLKID_SPICC>;
772	clock-names = "core";
773	resets = <&reset RESET_PERIPHS_SPICC>;
774	num-cs = <1>;
775};
776
777&spifc {
778	clocks = <&clkc CLKID_SPI>;
779};
780
781&uart_A {
782	clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
783	clock-names = "xtal", "pclk", "baud";
784};
785
786&uart_AO {
787	clocks = <&xtal>, <&clkc CLKID_CLK81>, <&xtal>;
788	clock-names = "xtal", "pclk", "baud";
789};
790
791&uart_AO_B {
792	clocks = <&xtal>, <&clkc CLKID_CLK81>, <&xtal>;
793	clock-names = "xtal", "pclk", "baud";
794};
795
796&uart_B {
797	clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
798	clock-names = "xtal", "core", "baud";
799};
800
801&uart_C {
802	clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>;
803	clock-names = "xtal", "core", "baud";
804};
805
806&vpu {
807	compatible = "amlogic,meson-gxbb-vpu", "amlogic,meson-gx-vpu";
808	power-domains = <&pwrc_vpu>;
809};
810