1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (c) 2016 Andreas Färber
4 */
5
6#include "meson-gx.dtsi"
7#include <dt-bindings/gpio/meson-gxbb-gpio.h>
8#include <dt-bindings/reset/amlogic,meson-gxbb-reset.h>
9#include <dt-bindings/clock/gxbb-clkc.h>
10#include <dt-bindings/clock/gxbb-aoclkc.h>
11#include <dt-bindings/reset/gxbb-aoclkc.h>
12
13/ {
14	compatible = "amlogic,meson-gxbb";
15
16	soc {
17		usb0_phy: phy@c0000000 {
18			compatible = "amlogic,meson-gxbb-usb2-phy";
19			#phy-cells = <0>;
20			reg = <0x0 0xc0000000 0x0 0x20>;
21			resets = <&reset RESET_USB_OTG>;
22			clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB0>;
23			clock-names = "usb_general", "usb";
24			status = "disabled";
25		};
26
27		usb1_phy: phy@c0000020 {
28			compatible = "amlogic,meson-gxbb-usb2-phy";
29			#phy-cells = <0>;
30			reg = <0x0 0xc0000020 0x0 0x20>;
31			resets = <&reset RESET_USB_OTG>;
32			clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1>;
33			clock-names = "usb_general", "usb";
34			status = "disabled";
35		};
36
37		usb0: usb@c9000000 {
38			compatible = "amlogic,meson-gxbb-usb", "snps,dwc2";
39			reg = <0x0 0xc9000000 0x0 0x40000>;
40			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
41			clocks = <&clkc CLKID_USB0_DDR_BRIDGE>;
42			clock-names = "otg";
43			phys = <&usb0_phy>;
44			phy-names = "usb2-phy";
45			dr_mode = "host";
46			status = "disabled";
47		};
48
49		usb1: usb@c9100000 {
50			compatible = "amlogic,meson-gxbb-usb", "snps,dwc2";
51			reg = <0x0 0xc9100000 0x0 0x40000>;
52			interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
53			clocks = <&clkc CLKID_USB1_DDR_BRIDGE>;
54			clock-names = "otg";
55			phys = <&usb1_phy>;
56			phy-names = "usb2-phy";
57			dr_mode = "host";
58			status = "disabled";
59		};
60	};
61};
62
63&aobus {
64	pinctrl_aobus: pinctrl@14 {
65		compatible = "amlogic,meson-gxbb-aobus-pinctrl";
66		#address-cells = <2>;
67		#size-cells = <2>;
68		ranges;
69
70		gpio_ao: bank@14 {
71			reg = <0x0 0x00014 0x0 0x8>,
72			      <0x0 0x0002c 0x0 0x4>,
73			      <0x0 0x00024 0x0 0x8>;
74			reg-names = "mux", "pull", "gpio";
75			gpio-controller;
76			#gpio-cells = <2>;
77			gpio-ranges = <&pinctrl_aobus 0 0 14>;
78		};
79
80		uart_ao_a_pins: uart_ao_a {
81			mux {
82				groups = "uart_tx_ao_a", "uart_rx_ao_a";
83				function = "uart_ao";
84			};
85		};
86
87		uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts {
88			mux {
89				groups = "uart_cts_ao_a",
90				       "uart_rts_ao_a";
91				function = "uart_ao";
92			};
93		};
94
95		uart_ao_b_pins: uart_ao_b {
96			mux {
97				groups = "uart_tx_ao_b", "uart_rx_ao_b";
98				function = "uart_ao_b";
99			};
100		};
101
102		uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts {
103			mux {
104				groups = "uart_cts_ao_b",
105				       "uart_rts_ao_b";
106				function = "uart_ao_b";
107			};
108		};
109
110		remote_input_ao_pins: remote_input_ao {
111			mux {
112				groups = "remote_input_ao";
113				function = "remote_input_ao";
114			};
115		};
116
117		i2c_ao_pins: i2c_ao {
118			mux {
119				groups = "i2c_sck_ao",
120				       "i2c_sda_ao";
121				function = "i2c_ao";
122			};
123		};
124
125		pwm_ao_a_3_pins: pwm_ao_a_3 {
126			mux {
127				groups = "pwm_ao_a_3";
128				function = "pwm_ao_a_3";
129			};
130		};
131
132		pwm_ao_a_6_pins: pwm_ao_a_6 {
133			mux {
134				groups = "pwm_ao_a_6";
135				function = "pwm_ao_a_6";
136			};
137		};
138
139		pwm_ao_a_12_pins: pwm_ao_a_12 {
140			mux {
141				groups = "pwm_ao_a_12";
142				function = "pwm_ao_a_12";
143			};
144		};
145
146		pwm_ao_b_pins: pwm_ao_b {
147			mux {
148				groups = "pwm_ao_b";
149				function = "pwm_ao_b";
150			};
151		};
152
153		i2s_am_clk_pins: i2s_am_clk {
154			mux {
155				groups = "i2s_am_clk";
156				function = "i2s_out_ao";
157			};
158		};
159
160		i2s_out_ao_clk_pins: i2s_out_ao_clk {
161			mux {
162				groups = "i2s_out_ao_clk";
163				function = "i2s_out_ao";
164			};
165		};
166
167		i2s_out_lr_clk_pins: i2s_out_lr_clk {
168			mux {
169				groups = "i2s_out_lr_clk";
170				function = "i2s_out_ao";
171			};
172		};
173
174		i2s_out_ch01_ao_pins: i2s_out_ch01_ao {
175			mux {
176				groups = "i2s_out_ch01_ao";
177				function = "i2s_out_ao";
178			};
179		};
180
181		i2s_out_ch23_ao_pins: i2s_out_ch23_ao {
182			mux {
183				groups = "i2s_out_ch23_ao";
184				function = "i2s_out_ao";
185			};
186		};
187
188		i2s_out_ch45_ao_pins: i2s_out_ch45_ao {
189			mux {
190				groups = "i2s_out_ch45_ao";
191				function = "i2s_out_ao";
192			};
193		};
194
195		spdif_out_ao_6_pins: spdif_out_ao_6 {
196			mux {
197				groups = "spdif_out_ao_6";
198				function = "spdif_out_ao";
199			};
200		};
201
202		spdif_out_ao_13_pins: spdif_out_ao_13 {
203			mux {
204				groups = "spdif_out_ao_13";
205				function = "spdif_out_ao";
206			};
207		};
208
209		ao_cec_pins: ao_cec {
210			mux {
211				groups = "ao_cec";
212				function = "cec_ao";
213			};
214		};
215
216		ee_cec_pins: ee_cec {
217			mux {
218				groups = "ee_cec";
219				function = "cec_ao";
220			};
221		};
222	};
223};
224
225&apb {
226	mali: gpu@c0000 {
227		compatible = "amlogic,meson-gxbb-mali", "arm,mali-450";
228		reg = <0x0 0xc0000 0x0 0x40000>;
229		interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
230			     <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
231			     <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
232			     <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
233			     <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
234			     <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
235			     <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
236			     <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
237			     <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
238			     <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
239		interrupt-names = "gp", "gpmmu", "pp", "pmu",
240			"pp0", "ppmmu0", "pp1", "ppmmu1",
241			"pp2", "ppmmu2";
242		clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>;
243		clock-names = "bus", "core";
244
245		/*
246		 * Mali clocking is provided by two identical clock paths
247		 * MALI_0 and MALI_1 muxed to a single clock by a glitch
248		 * free mux to safely change frequency while running.
249		 */
250		assigned-clocks = <&clkc CLKID_MALI_0_SEL>,
251				  <&clkc CLKID_MALI_0>,
252				  <&clkc CLKID_MALI>; /* Glitch free mux */
253		assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
254					 <0>, /* Do Nothing */
255					 <&clkc CLKID_MALI_0>;
256		assigned-clock-rates = <0>, /* Do Nothing */
257				       <666666666>,
258				       <0>; /* Do Nothing */
259	};
260};
261
262&cbus {
263	spifc: spi@8c80 {
264		compatible = "amlogic,meson-gxbb-spifc";
265		reg = <0x0 0x08c80 0x0 0x80>;
266		#address-cells = <1>;
267		#size-cells = <0>;
268		clocks = <&clkc CLKID_SPI>;
269		status = "disabled";
270	};
271};
272
273&cec_AO {
274	clocks = <&clkc_AO CLKID_AO_CEC_32K>;
275	clock-names = "core";
276};
277
278&clkc_AO {
279	compatible = "amlogic,meson-gxbb-aoclkc", "amlogic,meson-gx-aoclkc";
280};
281
282&ethmac {
283	clocks = <&clkc CLKID_ETH>,
284		 <&clkc CLKID_FCLK_DIV2>,
285		 <&clkc CLKID_MPLL2>;
286	clock-names = "stmmaceth", "clkin0", "clkin1";
287};
288
289&gpio_intc {
290	compatible = "amlogic,meson-gpio-intc",
291		     "amlogic,meson-gxbb-gpio-intc";
292	status = "okay";
293};
294
295&hdmi_tx {
296	compatible = "amlogic,meson-gxbb-dw-hdmi", "amlogic,meson-gx-dw-hdmi";
297	resets = <&reset RESET_HDMITX_CAPB3>,
298		 <&reset RESET_HDMI_SYSTEM_RESET>,
299		 <&reset RESET_HDMI_TX>;
300	reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy";
301	clocks = <&clkc CLKID_HDMI_PCLK>,
302		 <&clkc CLKID_CLK81>,
303		 <&clkc CLKID_GCLK_VENCI_INT0>;
304	clock-names = "isfr", "iahb", "venci";
305};
306
307&hiubus {
308	clkc: clock-controller@0 {
309		compatible = "amlogic,gxbb-clkc";
310		#clock-cells = <1>;
311		reg = <0x0 0x0 0x0 0x3db>;
312	};
313};
314
315&hwrng {
316	clocks = <&clkc CLKID_RNG0>;
317	clock-names = "core";
318};
319
320&i2c_A {
321	clocks = <&clkc CLKID_I2C>;
322};
323
324&i2c_AO {
325	clocks = <&clkc CLKID_AO_I2C>;
326};
327
328&i2c_B {
329	clocks = <&clkc CLKID_I2C>;
330};
331
332&i2c_C {
333	clocks = <&clkc CLKID_I2C>;
334};
335
336&periphs {
337	pinctrl_periphs: pinctrl@4b0 {
338		compatible = "amlogic,meson-gxbb-periphs-pinctrl";
339		#address-cells = <2>;
340		#size-cells = <2>;
341		ranges;
342
343		gpio: bank@4b0 {
344			reg = <0x0 0x004b0 0x0 0x28>,
345			      <0x0 0x004e8 0x0 0x14>,
346			      <0x0 0x00520 0x0 0x14>,
347			      <0x0 0x00430 0x0 0x40>;
348			reg-names = "mux", "pull", "pull-enable", "gpio";
349			gpio-controller;
350			#gpio-cells = <2>;
351			gpio-ranges = <&pinctrl_periphs 0 0 119>;
352		};
353
354		emmc_pins: emmc {
355			mux {
356				groups = "emmc_nand_d07",
357				       "emmc_cmd",
358				       "emmc_clk";
359				function = "emmc";
360			};
361		};
362
363		emmc_ds_pins: emmc-ds {
364			mux {
365				groups = "emmc_ds";
366				function = "emmc";
367			};
368		};
369
370		emmc_clk_gate_pins: emmc_clk_gate {
371			mux {
372				groups = "BOOT_8";
373				function = "gpio_periphs";
374			};
375			cfg-pull-down {
376				pins = "BOOT_8";
377				bias-pull-down;
378			};
379		};
380
381		nor_pins: nor {
382			mux {
383				groups = "nor_d",
384				       "nor_q",
385				       "nor_c",
386				       "nor_cs";
387				function = "nor";
388			};
389		};
390
391		spi_pins: spi {
392			mux {
393				groups = "spi_miso",
394					"spi_mosi",
395					"spi_sclk";
396				function = "spi";
397			};
398		};
399
400		spi_ss0_pins: spi-ss0 {
401			mux {
402				groups = "spi_ss0";
403				function = "spi";
404			};
405		};
406
407		sdcard_pins: sdcard {
408			mux {
409				groups = "sdcard_d0",
410				       "sdcard_d1",
411				       "sdcard_d2",
412				       "sdcard_d3",
413				       "sdcard_cmd",
414				       "sdcard_clk";
415				function = "sdcard";
416			};
417		};
418
419		sdcard_clk_gate_pins: sdcard_clk_gate {
420			mux {
421				groups = "CARD_2";
422				function = "gpio_periphs";
423			};
424			cfg-pull-down {
425				pins = "CARD_2";
426				bias-pull-down;
427			};
428		};
429
430		sdio_pins: sdio {
431			mux {
432				groups = "sdio_d0",
433				       "sdio_d1",
434				       "sdio_d2",
435				       "sdio_d3",
436				       "sdio_cmd",
437				       "sdio_clk";
438				function = "sdio";
439			};
440		};
441
442		sdio_clk_gate_pins: sdio_clk_gate {
443			mux {
444				groups = "GPIOX_4";
445				function = "gpio_periphs";
446			};
447			cfg-pull-down {
448				pins = "GPIOX_4";
449				bias-pull-down;
450			};
451		};
452
453		sdio_irq_pins: sdio_irq {
454			mux {
455				groups = "sdio_irq";
456				function = "sdio";
457			};
458		};
459
460		uart_a_pins: uart_a {
461			mux {
462				groups = "uart_tx_a",
463				       "uart_rx_a";
464				function = "uart_a";
465			};
466		};
467
468		uart_a_cts_rts_pins: uart_a_cts_rts {
469			mux {
470				groups = "uart_cts_a",
471				       "uart_rts_a";
472				function = "uart_a";
473			};
474		};
475
476		uart_b_pins: uart_b {
477			mux {
478				groups = "uart_tx_b",
479				       "uart_rx_b";
480				function = "uart_b";
481			};
482		};
483
484		uart_b_cts_rts_pins: uart_b_cts_rts {
485			mux {
486				groups = "uart_cts_b",
487				       "uart_rts_b";
488				function = "uart_b";
489			};
490		};
491
492		uart_c_pins: uart_c {
493			mux {
494				groups = "uart_tx_c",
495				       "uart_rx_c";
496				function = "uart_c";
497			};
498		};
499
500		uart_c_cts_rts_pins: uart_c_cts_rts {
501			mux {
502				groups = "uart_cts_c",
503				       "uart_rts_c";
504				function = "uart_c";
505			};
506		};
507
508		i2c_a_pins: i2c_a {
509			mux {
510				groups = "i2c_sck_a",
511				       "i2c_sda_a";
512				function = "i2c_a";
513			};
514		};
515
516		i2c_b_pins: i2c_b {
517			mux {
518				groups = "i2c_sck_b",
519				       "i2c_sda_b";
520				function = "i2c_b";
521			};
522		};
523
524		i2c_c_pins: i2c_c {
525			mux {
526				groups = "i2c_sck_c",
527				       "i2c_sda_c";
528				function = "i2c_c";
529			};
530		};
531
532		eth_rgmii_pins: eth-rgmii {
533			mux {
534				groups = "eth_mdio",
535				       "eth_mdc",
536				       "eth_clk_rx_clk",
537				       "eth_rx_dv",
538				       "eth_rxd0",
539				       "eth_rxd1",
540				       "eth_rxd2",
541				       "eth_rxd3",
542				       "eth_rgmii_tx_clk",
543				       "eth_tx_en",
544				       "eth_txd0",
545				       "eth_txd1",
546				       "eth_txd2",
547				       "eth_txd3";
548				function = "eth";
549			};
550		};
551
552		eth_rmii_pins: eth-rmii {
553			mux {
554				groups = "eth_mdio",
555				       "eth_mdc",
556				       "eth_clk_rx_clk",
557				       "eth_rx_dv",
558				       "eth_rxd0",
559				       "eth_rxd1",
560				       "eth_tx_en",
561				       "eth_txd0",
562				       "eth_txd1";
563				function = "eth";
564			};
565		};
566
567		pwm_a_x_pins: pwm_a_x {
568			mux {
569				groups = "pwm_a_x";
570				function = "pwm_a_x";
571			};
572		};
573
574		pwm_a_y_pins: pwm_a_y {
575			mux {
576				groups = "pwm_a_y";
577				function = "pwm_a_y";
578			};
579		};
580
581		pwm_b_pins: pwm_b {
582			mux {
583				groups = "pwm_b";
584				function = "pwm_b";
585			};
586		};
587
588		pwm_d_pins: pwm_d {
589			mux {
590				groups = "pwm_d";
591				function = "pwm_d";
592			};
593		};
594
595		pwm_e_pins: pwm_e {
596			mux {
597				groups = "pwm_e";
598				function = "pwm_e";
599			};
600		};
601
602		pwm_f_x_pins: pwm_f_x {
603			mux {
604				groups = "pwm_f_x";
605				function = "pwm_f_x";
606			};
607		};
608
609		pwm_f_y_pins: pwm_f_y {
610			mux {
611				groups = "pwm_f_y";
612				function = "pwm_f_y";
613			};
614		};
615
616		hdmi_hpd_pins: hdmi_hpd {
617			mux {
618				groups = "hdmi_hpd";
619				function = "hdmi_hpd";
620			};
621		};
622
623		hdmi_i2c_pins: hdmi_i2c {
624			mux {
625				groups = "hdmi_sda", "hdmi_scl";
626				function = "hdmi_i2c";
627			};
628		};
629
630		i2sout_ch23_y_pins: i2sout_ch23_y {
631			mux {
632				groups = "i2sout_ch23_y";
633				function = "i2s_out";
634			};
635		};
636
637		i2sout_ch45_y_pins: i2sout_ch45_y {
638			mux {
639				groups = "i2sout_ch45_y";
640				function = "i2s_out";
641			};
642		};
643
644		i2sout_ch67_y_pins: i2sout_ch67_y {
645			mux {
646				groups = "i2sout_ch67_y";
647				function = "i2s_out";
648			};
649		};
650
651		spdif_out_y_pins: spdif_out_y {
652			mux {
653				groups = "spdif_out_y";
654				function = "spdif_out";
655			};
656		};
657	};
658};
659
660&pwrc_vpu {
661	resets = <&reset RESET_VIU>,
662		 <&reset RESET_VENC>,
663		 <&reset RESET_VCBUS>,
664		 <&reset RESET_BT656>,
665		 <&reset RESET_DVIN_RESET>,
666		 <&reset RESET_RDMA>,
667		 <&reset RESET_VENCI>,
668		 <&reset RESET_VENCP>,
669		 <&reset RESET_VDAC>,
670		 <&reset RESET_VDI6>,
671		 <&reset RESET_VENCL>,
672		 <&reset RESET_VID_LOCK>;
673	clocks = <&clkc CLKID_VPU>,
674	         <&clkc CLKID_VAPB>;
675	clock-names = "vpu", "vapb";
676	/*
677	 * VPU clocking is provided by two identical clock paths
678	 * VPU_0 and VPU_1 muxed to a single clock by a glitch
679	 * free mux to safely change frequency while running.
680	 * Same for VAPB but with a final gate after the glitch free mux.
681	 */
682	assigned-clocks = <&clkc CLKID_VPU_0_SEL>,
683			  <&clkc CLKID_VPU_0>,
684			  <&clkc CLKID_VPU>, /* Glitch free mux */
685			  <&clkc CLKID_VAPB_0_SEL>,
686			  <&clkc CLKID_VAPB_0>,
687			  <&clkc CLKID_VAPB_SEL>; /* Glitch free mux */
688	assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
689				 <0>, /* Do Nothing */
690				 <&clkc CLKID_VPU_0>,
691				 <&clkc CLKID_FCLK_DIV4>,
692				 <0>, /* Do Nothing */
693				 <&clkc CLKID_VAPB_0>;
694	assigned-clock-rates = <0>, /* Do Nothing */
695			       <666666666>,
696			       <0>, /* Do Nothing */
697			       <0>, /* Do Nothing */
698			       <250000000>,
699			       <0>; /* Do Nothing */
700};
701
702&saradc {
703	compatible = "amlogic,meson-gxbb-saradc", "amlogic,meson-saradc";
704	clocks = <&xtal>,
705		 <&clkc CLKID_SAR_ADC>,
706		 <&clkc CLKID_SAR_ADC_CLK>,
707		 <&clkc CLKID_SAR_ADC_SEL>;
708	clock-names = "clkin", "core", "adc_clk", "adc_sel";
709};
710
711&sd_emmc_a {
712	clocks = <&clkc CLKID_SD_EMMC_A>,
713		 <&clkc CLKID_SD_EMMC_A_CLK0>,
714		 <&clkc CLKID_FCLK_DIV2>;
715	clock-names = "core", "clkin0", "clkin1";
716};
717
718&sd_emmc_b {
719	clocks = <&clkc CLKID_SD_EMMC_B>,
720		 <&clkc CLKID_SD_EMMC_B_CLK0>,
721		 <&clkc CLKID_FCLK_DIV2>;
722	clock-names = "core", "clkin0", "clkin1";
723};
724
725&sd_emmc_c {
726	clocks = <&clkc CLKID_SD_EMMC_C>,
727		 <&clkc CLKID_SD_EMMC_C_CLK0>,
728		 <&clkc CLKID_FCLK_DIV2>;
729	clock-names = "core", "clkin0", "clkin1";
730};
731
732&spicc {
733	clocks = <&clkc CLKID_SPICC>;
734	clock-names = "core";
735	resets = <&reset RESET_PERIPHS_SPICC>;
736	num-cs = <1>;
737};
738
739&spifc {
740	clocks = <&clkc CLKID_SPI>;
741};
742
743&uart_A {
744	clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
745	clock-names = "xtal", "pclk", "baud";
746};
747
748&uart_AO {
749	clocks = <&xtal>, <&clkc CLKID_CLK81>, <&xtal>;
750	clock-names = "xtal", "pclk", "baud";
751};
752
753&uart_AO_B {
754	clocks = <&xtal>, <&clkc CLKID_CLK81>, <&xtal>;
755	clock-names = "xtal", "pclk", "baud";
756};
757
758&uart_B {
759	clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
760	clock-names = "xtal", "pclk", "baud";
761};
762
763&uart_C {
764	clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>;
765	clock-names = "xtal", "pclk", "baud";
766};
767
768&vpu {
769	compatible = "amlogic,meson-gxbb-vpu", "amlogic,meson-gx-vpu";
770	power-domains = <&pwrc_vpu>;
771};
772