1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/phy/qcom,sc8280xp-qmp-pcie-phy.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm QMP PHY controller (PCIe, SC8280XP)
8
9maintainers:
10  - Vinod Koul <vkoul@kernel.org>
11
12description:
13  The QMP PHY controller supports physical layer functionality for a number of
14  controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.
15
16properties:
17  compatible:
18    enum:
19      - qcom,sc8280xp-qmp-gen3x1-pcie-phy
20      - qcom,sc8280xp-qmp-gen3x2-pcie-phy
21      - qcom,sc8280xp-qmp-gen3x4-pcie-phy
22      - qcom,sm8350-qmp-gen3x1-pcie-phy
23
24  reg:
25    minItems: 1
26    maxItems: 2
27
28  clocks:
29    minItems: 5
30    maxItems: 6
31
32  clock-names:
33    minItems: 5
34    items:
35      - const: aux
36      - const: cfg_ahb
37      - const: ref
38      - const: rchng
39      - const: pipe
40      - const: pipediv2
41
42  power-domains:
43    maxItems: 1
44
45  resets:
46    maxItems: 1
47
48  reset-names:
49    items:
50      - const: phy
51
52  vdda-phy-supply: true
53
54  vdda-pll-supply: true
55
56  qcom,4ln-config-sel:
57    description: PCIe 4-lane configuration
58    $ref: /schemas/types.yaml#/definitions/phandle-array
59    items:
60      - items:
61          - description: phandle of TCSR syscon
62          - description: offset of PCIe 4-lane configuration register
63          - description: offset of configuration bit for this PHY
64
65  "#clock-cells":
66    const: 0
67
68  clock-output-names:
69    maxItems: 1
70
71  "#phy-cells":
72    const: 0
73
74required:
75  - compatible
76  - reg
77  - clocks
78  - clock-names
79  - power-domains
80  - resets
81  - reset-names
82  - vdda-phy-supply
83  - vdda-pll-supply
84  - "#clock-cells"
85  - clock-output-names
86  - "#phy-cells"
87
88additionalProperties: false
89
90allOf:
91  - if:
92      properties:
93        compatible:
94          contains:
95            enum:
96              - qcom,sc8280xp-qmp-gen3x4-pcie-phy
97    then:
98      properties:
99        reg:
100          items:
101            - description: port a
102            - description: port b
103      required:
104        - qcom,4ln-config-sel
105    else:
106      properties:
107        reg:
108          maxItems: 1
109
110  - if:
111      properties:
112        compatible:
113          contains:
114            enum:
115              - qcom,sm8350-qmp-gen3x1-pcie-phy
116    then:
117      properties:
118        clocks:
119          maxItems: 5
120        clock-names:
121          maxItems: 5
122    else:
123      properties:
124        clocks:
125          minItems: 6
126        clock-names:
127          minItems: 6
128
129examples:
130  - |
131    #include <dt-bindings/clock/qcom,gcc-sc8280xp.h>
132
133    pcie2b_phy: phy@1c18000 {
134      compatible = "qcom,sc8280xp-qmp-gen3x2-pcie-phy";
135      reg = <0x01c18000 0x2000>;
136
137      clocks = <&gcc GCC_PCIE_2B_AUX_CLK>,
138               <&gcc GCC_PCIE_2B_CFG_AHB_CLK>,
139               <&gcc GCC_PCIE_2A2B_CLKREF_CLK>,
140               <&gcc GCC_PCIE2B_PHY_RCHNG_CLK>,
141               <&gcc GCC_PCIE_2B_PIPE_CLK>,
142               <&gcc GCC_PCIE_2B_PIPEDIV2_CLK>;
143      clock-names = "aux", "cfg_ahb", "ref", "rchng",
144                    "pipe", "pipediv2";
145
146      power-domains = <&gcc PCIE_2B_GDSC>;
147
148      resets = <&gcc GCC_PCIE_2B_PHY_BCR>;
149      reset-names = "phy";
150
151      vdda-phy-supply = <&vreg_l6d>;
152      vdda-pll-supply = <&vreg_l4d>;
153
154      #clock-cells = <0>;
155      clock-output-names = "pcie_2b_pipe_clk";
156
157      #phy-cells = <0>;
158    };
159
160    pcie2a_phy: phy@1c24000 {
161      compatible = "qcom,sc8280xp-qmp-gen3x4-pcie-phy";
162      reg = <0x01c24000 0x2000>, <0x01c26000 0x2000>;
163
164      clocks = <&gcc GCC_PCIE_2A_AUX_CLK>,
165               <&gcc GCC_PCIE_2A_CFG_AHB_CLK>,
166               <&gcc GCC_PCIE_2A2B_CLKREF_CLK>,
167               <&gcc GCC_PCIE2A_PHY_RCHNG_CLK>,
168               <&gcc GCC_PCIE_2A_PIPE_CLK>,
169               <&gcc GCC_PCIE_2A_PIPEDIV2_CLK>;
170      clock-names = "aux", "cfg_ahb", "ref", "rchng",
171                    "pipe", "pipediv2";
172
173      power-domains = <&gcc PCIE_2A_GDSC>;
174
175      resets = <&gcc GCC_PCIE_2A_PHY_BCR>;
176      reset-names = "phy";
177
178      vdda-phy-supply = <&vreg_l6d>;
179      vdda-pll-supply = <&vreg_l4d>;
180
181      qcom,4ln-config-sel = <&tcsr 0xa044 0>;
182
183      #clock-cells = <0>;
184      clock-output-names = "pcie_2a_pipe_clk";
185
186      #phy-cells = <0>;
187    };
188