1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/phy/qcom,sc8280xp-qmp-pcie-phy.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Qualcomm QMP PHY controller (PCIe, SC8280XP) 8 9maintainers: 10 - Vinod Koul <vkoul@kernel.org> 11 12description: 13 The QMP PHY controller supports physical layer functionality for a number of 14 controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB. 15 16properties: 17 compatible: 18 enum: 19 - qcom,sa8775p-qmp-gen4x2-pcie-phy 20 - qcom,sa8775p-qmp-gen4x4-pcie-phy 21 - qcom,sc8180x-qmp-pcie-phy 22 - qcom,sc8280xp-qmp-gen3x1-pcie-phy 23 - qcom,sc8280xp-qmp-gen3x2-pcie-phy 24 - qcom,sc8280xp-qmp-gen3x4-pcie-phy 25 - qcom,sdm845-qhp-pcie-phy 26 - qcom,sdm845-qmp-pcie-phy 27 - qcom,sdx55-qmp-pcie-phy 28 - qcom,sdx65-qmp-gen4x2-pcie-phy 29 - qcom,sm8250-qmp-gen3x1-pcie-phy 30 - qcom,sm8250-qmp-gen3x2-pcie-phy 31 - qcom,sm8250-qmp-modem-pcie-phy 32 - qcom,sm8350-qmp-gen3x1-pcie-phy 33 - qcom,sm8450-qmp-gen3x1-pcie-phy 34 - qcom,sm8450-qmp-gen4x2-pcie-phy 35 - qcom,sm8550-qmp-gen3x2-pcie-phy 36 - qcom,sm8550-qmp-gen4x2-pcie-phy 37 38 reg: 39 minItems: 1 40 maxItems: 2 41 42 clocks: 43 minItems: 5 44 maxItems: 7 45 46 clock-names: 47 minItems: 5 48 items: 49 - const: aux 50 - const: cfg_ahb 51 - const: ref 52 - enum: [rchng, refgen] 53 - const: pipe 54 - const: pipediv2 55 - const: phy_aux 56 57 power-domains: 58 maxItems: 1 59 60 resets: 61 minItems: 1 62 maxItems: 2 63 64 reset-names: 65 minItems: 1 66 items: 67 - const: phy 68 - const: phy_nocsr 69 70 vdda-phy-supply: true 71 72 vdda-pll-supply: true 73 74 vdda-qref-supply: true 75 76 qcom,4ln-config-sel: 77 description: PCIe 4-lane configuration 78 $ref: /schemas/types.yaml#/definitions/phandle-array 79 items: 80 - items: 81 - description: phandle of TCSR syscon 82 - description: offset of PCIe 4-lane configuration register 83 - description: offset of configuration bit for this PHY 84 85 "#clock-cells": 86 const: 0 87 88 clock-output-names: 89 maxItems: 1 90 91 "#phy-cells": 92 const: 0 93 94required: 95 - compatible 96 - reg 97 - clocks 98 - clock-names 99 - resets 100 - reset-names 101 - vdda-phy-supply 102 - vdda-pll-supply 103 - "#clock-cells" 104 - clock-output-names 105 - "#phy-cells" 106 107additionalProperties: false 108 109allOf: 110 - if: 111 properties: 112 compatible: 113 contains: 114 enum: 115 - qcom,sc8280xp-qmp-gen3x4-pcie-phy 116 then: 117 properties: 118 reg: 119 items: 120 - description: port a 121 - description: port b 122 required: 123 - qcom,4ln-config-sel 124 else: 125 properties: 126 reg: 127 maxItems: 1 128 129 - if: 130 properties: 131 compatible: 132 contains: 133 enum: 134 - qcom,sc8180x-qmp-pcie-phy 135 - qcom,sdm845-qhp-pcie-phy 136 - qcom,sdm845-qmp-pcie-phy 137 - qcom,sdx55-qmp-pcie-phy 138 - qcom,sm8250-qmp-gen3x1-pcie-phy 139 - qcom,sm8250-qmp-gen3x2-pcie-phy 140 - qcom,sm8250-qmp-modem-pcie-phy 141 - qcom,sm8350-qmp-gen3x1-pcie-phy 142 - qcom,sm8450-qmp-gen3x1-pcie-phy 143 - qcom,sm8450-qmp-gen3x2-pcie-phy 144 - qcom,sm8550-qmp-gen3x2-pcie-phy 145 - qcom,sm8550-qmp-gen4x2-pcie-phy 146 then: 147 properties: 148 clocks: 149 maxItems: 5 150 clock-names: 151 maxItems: 5 152 153 - if: 154 properties: 155 compatible: 156 contains: 157 enum: 158 - qcom,sc8280xp-qmp-gen3x1-pcie-phy 159 - qcom,sc8280xp-qmp-gen3x2-pcie-phy 160 - qcom,sc8280xp-qmp-gen3x4-pcie-phy 161 then: 162 properties: 163 clocks: 164 minItems: 6 165 clock-names: 166 minItems: 6 167 168 - if: 169 properties: 170 compatible: 171 contains: 172 enum: 173 - qcom,sa8775p-qmp-gen4x2-pcie-phy 174 - qcom,sa8775p-qmp-gen4x4-pcie-phy 175 then: 176 properties: 177 clocks: 178 minItems: 7 179 clock-names: 180 minItems: 7 181 182 - if: 183 properties: 184 compatible: 185 contains: 186 enum: 187 - qcom,sm8550-qmp-gen4x2-pcie-phy 188 then: 189 properties: 190 resets: 191 minItems: 2 192 reset-names: 193 minItems: 2 194 else: 195 properties: 196 resets: 197 maxItems: 1 198 reset-names: 199 maxItems: 1 200 201examples: 202 - | 203 #include <dt-bindings/clock/qcom,gcc-sc8280xp.h> 204 205 pcie2b_phy: phy@1c18000 { 206 compatible = "qcom,sc8280xp-qmp-gen3x2-pcie-phy"; 207 reg = <0x01c18000 0x2000>; 208 209 clocks = <&gcc GCC_PCIE_2B_AUX_CLK>, 210 <&gcc GCC_PCIE_2B_CFG_AHB_CLK>, 211 <&gcc GCC_PCIE_2A2B_CLKREF_CLK>, 212 <&gcc GCC_PCIE2B_PHY_RCHNG_CLK>, 213 <&gcc GCC_PCIE_2B_PIPE_CLK>, 214 <&gcc GCC_PCIE_2B_PIPEDIV2_CLK>; 215 clock-names = "aux", "cfg_ahb", "ref", "rchng", 216 "pipe", "pipediv2"; 217 218 power-domains = <&gcc PCIE_2B_GDSC>; 219 220 resets = <&gcc GCC_PCIE_2B_PHY_BCR>; 221 reset-names = "phy"; 222 223 vdda-phy-supply = <&vreg_l6d>; 224 vdda-pll-supply = <&vreg_l4d>; 225 226 #clock-cells = <0>; 227 clock-output-names = "pcie_2b_pipe_clk"; 228 229 #phy-cells = <0>; 230 }; 231 232 pcie2a_phy: phy@1c24000 { 233 compatible = "qcom,sc8280xp-qmp-gen3x4-pcie-phy"; 234 reg = <0x01c24000 0x2000>, <0x01c26000 0x2000>; 235 236 clocks = <&gcc GCC_PCIE_2A_AUX_CLK>, 237 <&gcc GCC_PCIE_2A_CFG_AHB_CLK>, 238 <&gcc GCC_PCIE_2A2B_CLKREF_CLK>, 239 <&gcc GCC_PCIE2A_PHY_RCHNG_CLK>, 240 <&gcc GCC_PCIE_2A_PIPE_CLK>, 241 <&gcc GCC_PCIE_2A_PIPEDIV2_CLK>; 242 clock-names = "aux", "cfg_ahb", "ref", "rchng", 243 "pipe", "pipediv2"; 244 245 power-domains = <&gcc PCIE_2A_GDSC>; 246 247 resets = <&gcc GCC_PCIE_2A_PHY_BCR>; 248 reset-names = "phy"; 249 250 vdda-phy-supply = <&vreg_l6d>; 251 vdda-pll-supply = <&vreg_l4d>; 252 253 qcom,4ln-config-sel = <&tcsr 0xa044 0>; 254 255 #clock-cells = <0>; 256 clock-output-names = "pcie_2a_pipe_clk"; 257 258 #phy-cells = <0>; 259 }; 260