1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/phy/qcom,sc8280xp-qmp-pcie-phy.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Qualcomm QMP PHY controller (PCIe, SC8280XP) 8 9maintainers: 10 - Vinod Koul <vkoul@kernel.org> 11 12description: 13 The QMP PHY controller supports physical layer functionality for a number of 14 controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB. 15 16properties: 17 compatible: 18 enum: 19 - qcom,sa8775p-qmp-gen4x2-pcie-phy 20 - qcom,sa8775p-qmp-gen4x4-pcie-phy 21 - qcom,sc8280xp-qmp-gen3x1-pcie-phy 22 - qcom,sc8280xp-qmp-gen3x2-pcie-phy 23 - qcom,sc8280xp-qmp-gen3x4-pcie-phy 24 - qcom,sdx65-qmp-gen4x2-pcie-phy 25 - qcom,sm8350-qmp-gen3x1-pcie-phy 26 - qcom,sm8550-qmp-gen3x2-pcie-phy 27 - qcom,sm8550-qmp-gen4x2-pcie-phy 28 29 reg: 30 minItems: 1 31 maxItems: 2 32 33 clocks: 34 minItems: 5 35 maxItems: 7 36 37 clock-names: 38 minItems: 5 39 items: 40 - const: aux 41 - const: cfg_ahb 42 - const: ref 43 - const: rchng 44 - const: pipe 45 - const: pipediv2 46 - const: phy_aux 47 48 power-domains: 49 maxItems: 1 50 51 resets: 52 minItems: 1 53 maxItems: 2 54 55 reset-names: 56 minItems: 1 57 items: 58 - const: phy 59 - const: phy_nocsr 60 61 vdda-phy-supply: true 62 63 vdda-pll-supply: true 64 65 vdda-qref-supply: true 66 67 qcom,4ln-config-sel: 68 description: PCIe 4-lane configuration 69 $ref: /schemas/types.yaml#/definitions/phandle-array 70 items: 71 - items: 72 - description: phandle of TCSR syscon 73 - description: offset of PCIe 4-lane configuration register 74 - description: offset of configuration bit for this PHY 75 76 "#clock-cells": 77 const: 0 78 79 clock-output-names: 80 maxItems: 1 81 82 "#phy-cells": 83 const: 0 84 85required: 86 - compatible 87 - reg 88 - clocks 89 - clock-names 90 - power-domains 91 - resets 92 - reset-names 93 - vdda-phy-supply 94 - vdda-pll-supply 95 - "#clock-cells" 96 - clock-output-names 97 - "#phy-cells" 98 99additionalProperties: false 100 101allOf: 102 - if: 103 properties: 104 compatible: 105 contains: 106 enum: 107 - qcom,sc8280xp-qmp-gen3x4-pcie-phy 108 then: 109 properties: 110 reg: 111 items: 112 - description: port a 113 - description: port b 114 required: 115 - qcom,4ln-config-sel 116 else: 117 properties: 118 reg: 119 maxItems: 1 120 121 - if: 122 properties: 123 compatible: 124 contains: 125 enum: 126 - qcom,sm8350-qmp-gen3x1-pcie-phy 127 - qcom,sm8550-qmp-gen3x2-pcie-phy 128 - qcom,sm8550-qmp-gen4x2-pcie-phy 129 then: 130 properties: 131 clocks: 132 maxItems: 5 133 clock-names: 134 maxItems: 5 135 else: 136 properties: 137 clocks: 138 minItems: 6 139 clock-names: 140 minItems: 6 141 142 - if: 143 properties: 144 compatible: 145 contains: 146 enum: 147 - qcom,sa8775p-qmp-gen4x2-pcie-phy 148 - qcom,sa8775p-qmp-gen4x4-pcie-phy 149 then: 150 properties: 151 clocks: 152 minItems: 7 153 clock-names: 154 minItems: 7 155 156 - if: 157 properties: 158 compatible: 159 contains: 160 enum: 161 - qcom,sm8550-qmp-gen4x2-pcie-phy 162 then: 163 properties: 164 resets: 165 minItems: 2 166 reset-names: 167 minItems: 2 168 else: 169 properties: 170 resets: 171 maxItems: 1 172 reset-names: 173 maxItems: 1 174 175examples: 176 - | 177 #include <dt-bindings/clock/qcom,gcc-sc8280xp.h> 178 179 pcie2b_phy: phy@1c18000 { 180 compatible = "qcom,sc8280xp-qmp-gen3x2-pcie-phy"; 181 reg = <0x01c18000 0x2000>; 182 183 clocks = <&gcc GCC_PCIE_2B_AUX_CLK>, 184 <&gcc GCC_PCIE_2B_CFG_AHB_CLK>, 185 <&gcc GCC_PCIE_2A2B_CLKREF_CLK>, 186 <&gcc GCC_PCIE2B_PHY_RCHNG_CLK>, 187 <&gcc GCC_PCIE_2B_PIPE_CLK>, 188 <&gcc GCC_PCIE_2B_PIPEDIV2_CLK>; 189 clock-names = "aux", "cfg_ahb", "ref", "rchng", 190 "pipe", "pipediv2"; 191 192 power-domains = <&gcc PCIE_2B_GDSC>; 193 194 resets = <&gcc GCC_PCIE_2B_PHY_BCR>; 195 reset-names = "phy"; 196 197 vdda-phy-supply = <&vreg_l6d>; 198 vdda-pll-supply = <&vreg_l4d>; 199 200 #clock-cells = <0>; 201 clock-output-names = "pcie_2b_pipe_clk"; 202 203 #phy-cells = <0>; 204 }; 205 206 pcie2a_phy: phy@1c24000 { 207 compatible = "qcom,sc8280xp-qmp-gen3x4-pcie-phy"; 208 reg = <0x01c24000 0x2000>, <0x01c26000 0x2000>; 209 210 clocks = <&gcc GCC_PCIE_2A_AUX_CLK>, 211 <&gcc GCC_PCIE_2A_CFG_AHB_CLK>, 212 <&gcc GCC_PCIE_2A2B_CLKREF_CLK>, 213 <&gcc GCC_PCIE2A_PHY_RCHNG_CLK>, 214 <&gcc GCC_PCIE_2A_PIPE_CLK>, 215 <&gcc GCC_PCIE_2A_PIPEDIV2_CLK>; 216 clock-names = "aux", "cfg_ahb", "ref", "rchng", 217 "pipe", "pipediv2"; 218 219 power-domains = <&gcc PCIE_2A_GDSC>; 220 221 resets = <&gcc GCC_PCIE_2A_PHY_BCR>; 222 reset-names = "phy"; 223 224 vdda-phy-supply = <&vreg_l6d>; 225 vdda-pll-supply = <&vreg_l4d>; 226 227 qcom,4ln-config-sel = <&tcsr 0xa044 0>; 228 229 #clock-cells = <0>; 230 clock-output-names = "pcie_2a_pipe_clk"; 231 232 #phy-cells = <0>; 233 }; 234