1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pci/fsl,imx6q-pcie.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Freescale i.MX6 PCIe host controller
8
9maintainers:
10  - Lucas Stach <l.stach@pengutronix.de>
11  - Richard Zhu <hongxing.zhu@nxp.com>
12
13description: |+
14  This PCIe host controller is based on the Synopsys DesignWare PCIe IP
15  and thus inherits all the common properties defined in snps,dw-pcie.yaml.
16
17properties:
18  compatible:
19    enum:
20      - fsl,imx6q-pcie
21      - fsl,imx6sx-pcie
22      - fsl,imx6qp-pcie
23      - fsl,imx7d-pcie
24      - fsl,imx8mq-pcie
25      - fsl,imx8mm-pcie
26      - fsl,imx8mp-pcie
27
28  reg:
29    items:
30      - description: Data Bus Interface (DBI) registers.
31      - description: PCIe configuration space region.
32
33  reg-names:
34    items:
35      - const: dbi
36      - const: config
37
38  interrupts:
39    items:
40      - description: builtin MSI controller.
41
42  interrupt-names:
43    items:
44      - const: msi
45
46  clocks:
47    minItems: 3
48    items:
49      - description: PCIe bridge clock.
50      - description: PCIe bus clock.
51      - description: PCIe PHY clock.
52      - description: Additional required clock entry for imx6sx-pcie,
53          imx8mq-pcie.
54
55  clock-names:
56    minItems: 3
57    items:
58      - const: pcie
59      - const: pcie_bus
60      - enum: [ pcie_phy, pcie_aux ]
61      - enum: [ pcie_inbound_axi, pcie_aux ]
62
63  num-lanes:
64    const: 1
65
66  fsl,imx7d-pcie-phy:
67    $ref: /schemas/types.yaml#/definitions/phandle
68    description: A phandle to an fsl,imx7d-pcie-phy node. Additional
69      required properties for imx7d-pcie and imx8mq-pcie.
70
71  power-domains:
72    items:
73      - description: The phandle pointing to the DISPLAY domain for
74          imx6sx-pcie, to PCIE_PHY power domain for imx7d-pcie and
75          imx8mq-pcie.
76      - description: The phandle pointing to the PCIE_PHY power domains
77          for imx6sx-pcie.
78
79  power-domain-names:
80    items:
81      - const: pcie
82      - const: pcie_phy
83
84  resets:
85    maxItems: 3
86    description: Phandles to PCIe-related reset lines exposed by SRC
87      IP block. Additional required by imx7d-pcie and imx8mq-pcie.
88
89  reset-names:
90    items:
91      - const: pciephy
92      - const: apps
93      - const: turnoff
94
95  fsl,tx-deemph-gen1:
96    description: Gen1 De-emphasis value (optional required).
97    $ref: /schemas/types.yaml#/definitions/uint32
98    default: 0
99
100  fsl,tx-deemph-gen2-3p5db:
101    description: Gen2 (3.5db) De-emphasis value (optional required).
102    $ref: /schemas/types.yaml#/definitions/uint32
103    default: 0
104
105  fsl,tx-deemph-gen2-6db:
106    description: Gen2 (6db) De-emphasis value (optional required).
107    $ref: /schemas/types.yaml#/definitions/uint32
108    default: 20
109
110  fsl,tx-swing-full:
111    description: Gen2 TX SWING FULL value (optional required).
112    $ref: /schemas/types.yaml#/definitions/uint32
113    default: 127
114
115  fsl,tx-swing-low:
116    description: TX launch amplitude swing_low value (optional required).
117    $ref: /schemas/types.yaml#/definitions/uint32
118    default: 127
119
120  fsl,max-link-speed:
121    description: Specify PCI Gen for link capability (optional required).
122      Note that the IMX6 LVDS clock outputs do not meet gen2 jitter
123      requirements and thus for gen2 capability a gen2 compliant clock
124      generator should be used and configured.
125    $ref: /schemas/types.yaml#/definitions/uint32
126    enum: [1, 2, 3, 4]
127    default: 1
128
129  phys:
130    maxItems: 1
131
132  phy-names:
133    const: pcie-phy
134
135  reset-gpio:
136    description: Should specify the GPIO for controlling the PCI bus device
137      reset signal. It's not polarity aware and defaults to active-low reset
138      sequence (L=reset state, H=operation state) (optional required).
139
140  reset-gpio-active-high:
141    description: If present then the reset sequence using the GPIO
142      specified in the "reset-gpio" property is reversed (H=reset state,
143      L=operation state) (optional required).
144    type: boolean
145
146  vpcie-supply:
147    description: Should specify the regulator in charge of PCIe port power.
148      The regulator will be enabled when initializing the PCIe host and
149      disabled either as part of the init process or when shutting down
150      the host (optional required).
151
152  vph-supply:
153    description: Should specify the regulator in charge of VPH one of
154      the three PCIe PHY powers. This regulator can be supplied by both
155      1.8v and 3.3v voltage supplies (optional required).
156
157required:
158  - compatible
159  - reg
160  - reg-names
161  - "#address-cells"
162  - "#size-cells"
163  - device_type
164  - bus-range
165  - ranges
166  - num-lanes
167  - interrupts
168  - interrupt-names
169  - "#interrupt-cells"
170  - interrupt-map-mask
171  - interrupt-map
172  - clocks
173  - clock-names
174
175allOf:
176  - $ref: /schemas/pci/snps,dw-pcie.yaml#
177  - if:
178      properties:
179        compatible:
180          contains:
181            const: fsl,imx6sx-pcie
182    then:
183      properties:
184        clock-names:
185          items:
186            - {}
187            - {}
188            - const: pcie_phy
189            - const: pcie_inbound_axi
190  - if:
191      properties:
192        compatible:
193          contains:
194            const: fsl,imx8mq-pcie
195    then:
196      properties:
197        clock-names:
198          items:
199            - {}
200            - {}
201            - const: pcie_phy
202            - const: pcie_aux
203  - if:
204      properties:
205        compatible:
206          not:
207            contains:
208              enum:
209                - fsl,imx6sx-pcie
210                - fsl,imx8mq-pcie
211    then:
212      properties:
213        clocks:
214          maxItems: 3
215        clock-names:
216          maxItems: 3
217
218  - if:
219      properties:
220        compatible:
221          contains:
222            enum:
223              - fsl,imx6q-pcie
224              - fsl,imx6qp-pcie
225              - fsl,imx7d-pcie
226    then:
227      properties:
228        clock-names:
229          maxItems: 3
230          contains:
231            const: pcie_phy
232
233  - if:
234      properties:
235        compatible:
236          contains:
237            enum:
238              - fsl,imx8mm-pcie
239              - fsl,imx8mp-pcie
240    then:
241      properties:
242        clock-names:
243          maxItems: 3
244          contains:
245            const: pcie_aux
246
247unevaluatedProperties: false
248
249examples:
250  - |
251    #include <dt-bindings/clock/imx6qdl-clock.h>
252    #include <dt-bindings/interrupt-controller/arm-gic.h>
253
254    pcie: pcie@1ffc000 {
255        compatible = "fsl,imx6q-pcie";
256        reg = <0x01ffc000 0x04000>,
257              <0x01f00000 0x80000>;
258        reg-names = "dbi", "config";
259        #address-cells = <3>;
260        #size-cells = <2>;
261        device_type = "pci";
262        bus-range = <0x00 0xff>;
263        ranges = <0x81000000 0 0          0x01f80000 0 0x00010000>,
264                 <0x82000000 0 0x01000000 0x01000000 0 0x00f00000>;
265        num-lanes = <1>;
266        interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
267        interrupt-names = "msi";
268        #interrupt-cells = <1>;
269        interrupt-map-mask = <0 0 0 0x7>;
270        interrupt-map = <0 0 0 1 &gpc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
271                        <0 0 0 2 &gpc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
272                        <0 0 0 3 &gpc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
273                        <0 0 0 4 &gpc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
274        clocks = <&clks IMX6QDL_CLK_PCIE_AXI>,
275                <&clks IMX6QDL_CLK_LVDS1_GATE>,
276                <&clks IMX6QDL_CLK_PCIE_REF_125M>;
277        clock-names = "pcie", "pcie_bus", "pcie_phy";
278    };
279...
280