1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pci/fsl,imx6q-pcie.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Freescale i.MX6 PCIe host controller
8
9maintainers:
10  - Lucas Stach <l.stach@pengutronix.de>
11  - Richard Zhu <hongxing.zhu@nxp.com>
12
13description: |+
14  This PCIe host controller is based on the Synopsys DesignWare PCIe IP
15  and thus inherits all the common properties defined in snps,dw-pcie.yaml.
16
17properties:
18  compatible:
19    enum:
20      - fsl,imx6q-pcie
21      - fsl,imx6sx-pcie
22      - fsl,imx6qp-pcie
23      - fsl,imx7d-pcie
24      - fsl,imx8mq-pcie
25      - fsl,imx8mm-pcie
26      - fsl,imx8mp-pcie
27
28  reg:
29    items:
30      - description: Data Bus Interface (DBI) registers.
31      - description: PCIe configuration space region.
32
33  reg-names:
34    items:
35      - const: dbi
36      - const: config
37
38  interrupts:
39    items:
40      - description: builtin MSI controller.
41
42  interrupt-names:
43    items:
44      - const: msi
45
46  clocks:
47    minItems: 3
48    items:
49      - description: PCIe bridge clock.
50      - description: PCIe bus clock.
51      - description: PCIe PHY clock.
52      - description: Additional required clock entry for imx6sx-pcie,
53          imx8mq-pcie.
54
55  clock-names:
56    minItems: 3
57    items:
58      - const: pcie
59      - const: pcie_bus
60      - enum: [ pcie_phy, pcie_aux ]
61      - enum: [ pcie_inbound_axi, pcie_aux ]
62
63  num-lanes:
64    const: 1
65
66  fsl,imx7d-pcie-phy:
67    $ref: /schemas/types.yaml#/definitions/phandle
68    description: A phandle to an fsl,imx7d-pcie-phy node. Additional
69      required properties for imx7d-pcie and imx8mq-pcie.
70
71  power-domains:
72    minItems: 1
73    items:
74      - description: The phandle pointing to the DISPLAY domain for
75          imx6sx-pcie, to PCIE_PHY power domain for imx7d-pcie and
76          imx8mq-pcie.
77      - description: The phandle pointing to the PCIE_PHY power domains
78          for imx6sx-pcie.
79
80  power-domain-names:
81    minItems: 1
82    items:
83      - const: pcie
84      - const: pcie_phy
85
86  resets:
87    maxItems: 3
88    description: Phandles to PCIe-related reset lines exposed by SRC
89      IP block. Additional required by imx7d-pcie and imx8mq-pcie.
90
91  reset-names:
92    items:
93      - const: pciephy
94      - const: apps
95      - const: turnoff
96
97  fsl,tx-deemph-gen1:
98    description: Gen1 De-emphasis value (optional required).
99    $ref: /schemas/types.yaml#/definitions/uint32
100    default: 0
101
102  fsl,tx-deemph-gen2-3p5db:
103    description: Gen2 (3.5db) De-emphasis value (optional required).
104    $ref: /schemas/types.yaml#/definitions/uint32
105    default: 0
106
107  fsl,tx-deemph-gen2-6db:
108    description: Gen2 (6db) De-emphasis value (optional required).
109    $ref: /schemas/types.yaml#/definitions/uint32
110    default: 20
111
112  fsl,tx-swing-full:
113    description: Gen2 TX SWING FULL value (optional required).
114    $ref: /schemas/types.yaml#/definitions/uint32
115    default: 127
116
117  fsl,tx-swing-low:
118    description: TX launch amplitude swing_low value (optional required).
119    $ref: /schemas/types.yaml#/definitions/uint32
120    default: 127
121
122  fsl,max-link-speed:
123    description: Specify PCI Gen for link capability (optional required).
124      Note that the IMX6 LVDS clock outputs do not meet gen2 jitter
125      requirements and thus for gen2 capability a gen2 compliant clock
126      generator should be used and configured.
127    $ref: /schemas/types.yaml#/definitions/uint32
128    enum: [1, 2, 3, 4]
129    default: 1
130
131  phys:
132    maxItems: 1
133
134  phy-names:
135    const: pcie-phy
136
137  reset-gpio:
138    description: Should specify the GPIO for controlling the PCI bus device
139      reset signal. It's not polarity aware and defaults to active-low reset
140      sequence (L=reset state, H=operation state) (optional required).
141
142  reset-gpio-active-high:
143    description: If present then the reset sequence using the GPIO
144      specified in the "reset-gpio" property is reversed (H=reset state,
145      L=operation state) (optional required).
146    type: boolean
147
148  vpcie-supply:
149    description: Should specify the regulator in charge of PCIe port power.
150      The regulator will be enabled when initializing the PCIe host and
151      disabled either as part of the init process or when shutting down
152      the host (optional required).
153
154  vph-supply:
155    description: Should specify the regulator in charge of VPH one of
156      the three PCIe PHY powers. This regulator can be supplied by both
157      1.8v and 3.3v voltage supplies (optional required).
158
159required:
160  - compatible
161  - reg
162  - reg-names
163  - "#address-cells"
164  - "#size-cells"
165  - device_type
166  - bus-range
167  - ranges
168  - num-lanes
169  - interrupts
170  - interrupt-names
171  - "#interrupt-cells"
172  - interrupt-map-mask
173  - interrupt-map
174  - clocks
175  - clock-names
176
177allOf:
178  - $ref: /schemas/pci/snps,dw-pcie.yaml#
179  - if:
180      properties:
181        compatible:
182          contains:
183            const: fsl,imx6sx-pcie
184    then:
185      properties:
186        clock-names:
187          items:
188            - {}
189            - {}
190            - const: pcie_phy
191            - const: pcie_inbound_axi
192        power-domains:
193          minItems: 2
194        power-domain-names:
195          minItems: 2
196  - if:
197      properties:
198        compatible:
199          contains:
200            const: fsl,imx8mq-pcie
201    then:
202      properties:
203        clock-names:
204          items:
205            - {}
206            - {}
207            - const: pcie_phy
208            - const: pcie_aux
209  - if:
210      properties:
211        compatible:
212          not:
213            contains:
214              enum:
215                - fsl,imx6sx-pcie
216                - fsl,imx8mq-pcie
217    then:
218      properties:
219        clocks:
220          maxItems: 3
221        clock-names:
222          maxItems: 3
223
224  - if:
225      properties:
226        compatible:
227          contains:
228            enum:
229              - fsl,imx6q-pcie
230              - fsl,imx6qp-pcie
231              - fsl,imx7d-pcie
232    then:
233      properties:
234        clock-names:
235          maxItems: 3
236          contains:
237            const: pcie_phy
238
239  - if:
240      properties:
241        compatible:
242          contains:
243            enum:
244              - fsl,imx8mm-pcie
245              - fsl,imx8mp-pcie
246    then:
247      properties:
248        clock-names:
249          maxItems: 3
250          contains:
251            const: pcie_aux
252  - if:
253      properties:
254        compatible:
255          contains:
256            enum:
257              - fsl,imx6q-pcie
258              - fsl,imx6qp-pcie
259    then:
260      properties:
261        power-domains: false
262        power-domain-names: false
263
264  - if:
265      not:
266        properties:
267          compatible:
268            contains:
269              enum:
270                - fsl,imx6sx-pcie
271                - fsl,imx6q-pcie
272                - fsl,imx6qp-pcie
273    then:
274      properties:
275        power-domains:
276          maxItems: 1
277        power-domain-names: false
278
279unevaluatedProperties: false
280
281examples:
282  - |
283    #include <dt-bindings/clock/imx6qdl-clock.h>
284    #include <dt-bindings/interrupt-controller/arm-gic.h>
285
286    pcie: pcie@1ffc000 {
287        compatible = "fsl,imx6q-pcie";
288        reg = <0x01ffc000 0x04000>,
289              <0x01f00000 0x80000>;
290        reg-names = "dbi", "config";
291        #address-cells = <3>;
292        #size-cells = <2>;
293        device_type = "pci";
294        bus-range = <0x00 0xff>;
295        ranges = <0x81000000 0 0          0x01f80000 0 0x00010000>,
296                 <0x82000000 0 0x01000000 0x01000000 0 0x00f00000>;
297        num-lanes = <1>;
298        interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
299        interrupt-names = "msi";
300        #interrupt-cells = <1>;
301        interrupt-map-mask = <0 0 0 0x7>;
302        interrupt-map = <0 0 0 1 &gpc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
303                        <0 0 0 2 &gpc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
304                        <0 0 0 3 &gpc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
305                        <0 0 0 4 &gpc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
306        clocks = <&clks IMX6QDL_CLK_PCIE_AXI>,
307                <&clks IMX6QDL_CLK_LVDS1_GATE>,
308                <&clks IMX6QDL_CLK_PCIE_REF_125M>;
309        clock-names = "pcie", "pcie_bus", "pcie_phy";
310    };
311...
312